1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K344_FLEXCAN.h 10 * @version 1.9 11 * @date 2021-10-27 12 * @brief Peripheral Access Layer for S32K344_FLEXCAN 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K344_FLEXCAN_H_) /* Check if memory map has not been already included */ 58 #define S32K344_FLEXCAN_H_ 59 60 #include "S32K344_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- FLEXCAN Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup FLEXCAN_Peripheral_Access_Layer FLEXCAN Peripheral Access Layer 68 * @{ 69 */ 70 71 /** FLEXCAN - Size of Registers Arrays */ 72 #define FLEXCAN_RXIMR_COUNT 96u 73 #define FLEXCAN_HR_TIME_STAMP_COUNT 96u 74 #define FLEXCAN_ERFFEL_COUNT 128u 75 76 /** FLEXCAN - Register Layout Typedef */ 77 typedef struct { 78 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ 79 __IO uint32_t CTRL1; /**< Control 1 Register, offset: 0x4 */ 80 __IO uint32_t TIMER; /**< Free Running Timer, offset: 0x8 */ 81 uint8_t RESERVED_0[4]; 82 __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */ 83 __IO uint32_t RX14MASK; /**< Rx 14 Mask Register, offset: 0x14 */ 84 __IO uint32_t RX15MASK; /**< Rx 15 Mask Register, offset: 0x18 */ 85 __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */ 86 __IO uint32_t ESR1; /**< Error and Status 1 Register, offset: 0x20 */ 87 __IO uint32_t IMASK2; /**< Interrupt Masks 2 Register, offset: 0x24 */ 88 __IO uint32_t IMASK1; /**< Interrupt Masks 1 Register, offset: 0x28 */ 89 __IO uint32_t IFLAG2; /**< Interrupt Flags 2 Register, offset: 0x2C */ 90 __IO uint32_t IFLAG1; /**< Interrupt Flags 1 Register, offset: 0x30 */ 91 __IO uint32_t CTRL2; /**< Control 2 Register, offset: 0x34 */ 92 __I uint32_t ESR2; /**< Error and Status 2 Register, offset: 0x38 */ 93 uint8_t RESERVED_1[8]; 94 __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */ 95 __IO uint32_t RXFGMASK; /**< Legacy Rx FIFO Global Mask Register..Rx FIFO Global Mask Register, offset: 0x48 */ 96 __I uint32_t RXFIR; /**< Legacy Rx FIFO Information Register..Rx FIFO Information Register, offset: 0x4C */ 97 __IO uint32_t CBT; /**< CAN Bit Timing Register, offset: 0x50 */ 98 uint8_t RESERVED_2[24]; 99 __IO uint32_t IMASK3; /**< Interrupt Masks 3 Register, offset: 0x6C */ 100 uint8_t RESERVED_3[4]; 101 __IO uint32_t IFLAG3; /**< Interrupt Flags 3 Register, offset: 0x74 */ 102 uint8_t RESERVED_4[2056]; 103 __IO uint32_t RXIMR[FLEXCAN_RXIMR_COUNT]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */ 104 uint8_t RESERVED_5[224]; 105 __IO uint32_t MECR; /**< Memory Error Control Register, offset: 0xAE0 */ 106 __IO uint32_t ERRIAR; /**< Error Injection Address Register, offset: 0xAE4 */ 107 __IO uint32_t ERRIDPR; /**< Error Injection Data Pattern Register, offset: 0xAE8 */ 108 __IO uint32_t ERRIPPR; /**< Error Injection Parity Pattern Register, offset: 0xAEC */ 109 __I uint32_t RERRAR; /**< Error Report Address Register, offset: 0xAF0 */ 110 __I uint32_t RERRDR; /**< Error Report Data Register, offset: 0xAF4 */ 111 __I uint32_t RERRSYNR; /**< Error Report Syndrome Register, offset: 0xAF8 */ 112 __IO uint32_t ERRSR; /**< Error Status Register, offset: 0xAFC */ 113 uint8_t RESERVED_6[240]; 114 __IO uint32_t EPRS; /**< Enhanced CAN Bit Timing Prescalers, offset: 0xBF0 */ 115 __IO uint32_t ENCBT; /**< Enhanced Nominal CAN Bit Timing, offset: 0xBF4 */ 116 __IO uint32_t EDCBT; /**< Enhanced Data Phase CAN bit Timing, offset: 0xBF8 */ 117 __IO uint32_t ETDC; /**< Enhanced Transceiver Delay Compensation, offset: 0xBFC */ 118 __IO uint32_t FDCTRL; /**< CAN FD Control Register, offset: 0xC00 */ 119 __IO uint32_t FDCBT; /**< CAN FD Bit Timing Register, offset: 0xC04 */ 120 __I uint32_t FDCRC; /**< CAN FD CRC Register, offset: 0xC08 */ 121 __IO uint32_t ERFCR; /**< Enhanced Rx FIFO Control Register, offset: 0xC0C */ 122 __IO uint32_t ERFIER; /**< Enhanced Rx FIFO Interrupt Enable Register, offset: 0xC10 */ 123 __IO uint32_t ERFSR; /**< Enhanced Rx FIFO Status Register, offset: 0xC14 */ 124 uint8_t RESERVED_7[24]; 125 __IO uint32_t HR_TIME_STAMP[FLEXCAN_HR_TIME_STAMP_COUNT]; /**< High Resolution Time Stamp, array offset: 0xC30, array step: 0x4 */ 126 uint8_t RESERVED_8[8784]; 127 __IO uint32_t ERFFEL[FLEXCAN_ERFFEL_COUNT]; /**< Enhanced Rx FIFO Filter Element, array offset: 0x3000, array step: 0x4 */ 128 } FLEXCAN_Type, *FLEXCAN_MemMapPtr; 129 130 /** Number of instances of the FLEXCAN module. */ 131 #define FLEXCAN_INSTANCE_COUNT (6u) 132 133 /* FLEXCAN - Peripheral instance base addresses */ 134 /** Peripheral CAN_0 base address */ 135 #define IP_CAN_0_BASE (0x40304000u) 136 /** Peripheral CAN_0 base pointer */ 137 #define IP_CAN_0 ((FLEXCAN_Type *)IP_CAN_0_BASE) 138 /** Peripheral CAN_1 base address */ 139 #define IP_CAN_1_BASE (0x40308000u) 140 /** Peripheral CAN_1 base pointer */ 141 #define IP_CAN_1 ((FLEXCAN_Type *)IP_CAN_1_BASE) 142 /** Peripheral CAN_2 base address */ 143 #define IP_CAN_2_BASE (0x4030C000u) 144 /** Peripheral CAN_2 base pointer */ 145 #define IP_CAN_2 ((FLEXCAN_Type *)IP_CAN_2_BASE) 146 /** Peripheral CAN_3 base address */ 147 #define IP_CAN_3_BASE (0x40310000u) 148 /** Peripheral CAN_3 base pointer */ 149 #define IP_CAN_3 ((FLEXCAN_Type *)IP_CAN_3_BASE) 150 /** Peripheral CAN_4 base address */ 151 #define IP_CAN_4_BASE (0x40314000u) 152 /** Peripheral CAN_4 base pointer */ 153 #define IP_CAN_4 ((FLEXCAN_Type *)IP_CAN_4_BASE) 154 /** Peripheral CAN_5 base address */ 155 #define IP_CAN_5_BASE (0x40318000u) 156 /** Peripheral CAN_5 base pointer */ 157 #define IP_CAN_5 ((FLEXCAN_Type *)IP_CAN_5_BASE) 158 /** Array initializer of FLEXCAN peripheral base addresses */ 159 #define IP_FLEXCAN_BASE_ADDRS { IP_CAN_0_BASE, IP_CAN_1_BASE, IP_CAN_2_BASE, IP_CAN_3_BASE, IP_CAN_4_BASE, IP_CAN_5_BASE } 160 /** Array initializer of FLEXCAN peripheral base pointers */ 161 #define IP_FLEXCAN_BASE_PTRS { IP_CAN_0, IP_CAN_1, IP_CAN_2, IP_CAN_3, IP_CAN_4, IP_CAN_5 } 162 163 /* ---------------------------------------------------------------------------- 164 -- FLEXCAN Register Masks 165 ---------------------------------------------------------------------------- */ 166 167 /*! 168 * @addtogroup FLEXCAN_Register_Masks FLEXCAN Register Masks 169 * @{ 170 */ 171 172 /*! @name MCR - Module Configuration Register */ 173 /*! @{ */ 174 175 #define FLEXCAN_MCR_MAXMB_MASK (0x7FU) 176 #define FLEXCAN_MCR_MAXMB_SHIFT (0U) 177 #define FLEXCAN_MCR_MAXMB_WIDTH (7U) 178 #define FLEXCAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_MAXMB_SHIFT)) & FLEXCAN_MCR_MAXMB_MASK) 179 180 #define FLEXCAN_MCR_IDAM_MASK (0x300U) 181 #define FLEXCAN_MCR_IDAM_SHIFT (8U) 182 #define FLEXCAN_MCR_IDAM_WIDTH (2U) 183 #define FLEXCAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_IDAM_SHIFT)) & FLEXCAN_MCR_IDAM_MASK) 184 185 #define FLEXCAN_MCR_FDEN_MASK (0x800U) 186 #define FLEXCAN_MCR_FDEN_SHIFT (11U) 187 #define FLEXCAN_MCR_FDEN_WIDTH (1U) 188 #define FLEXCAN_MCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_FDEN_SHIFT)) & FLEXCAN_MCR_FDEN_MASK) 189 190 #define FLEXCAN_MCR_AEN_MASK (0x1000U) 191 #define FLEXCAN_MCR_AEN_SHIFT (12U) 192 #define FLEXCAN_MCR_AEN_WIDTH (1U) 193 #define FLEXCAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_AEN_SHIFT)) & FLEXCAN_MCR_AEN_MASK) 194 195 #define FLEXCAN_MCR_LPRIOEN_MASK (0x2000U) 196 #define FLEXCAN_MCR_LPRIOEN_SHIFT (13U) 197 #define FLEXCAN_MCR_LPRIOEN_WIDTH (1U) 198 #define FLEXCAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_LPRIOEN_SHIFT)) & FLEXCAN_MCR_LPRIOEN_MASK) 199 200 #define FLEXCAN_MCR_DMA_MASK (0x8000U) 201 #define FLEXCAN_MCR_DMA_SHIFT (15U) 202 #define FLEXCAN_MCR_DMA_WIDTH (1U) 203 #define FLEXCAN_MCR_DMA(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_DMA_SHIFT)) & FLEXCAN_MCR_DMA_MASK) 204 205 #define FLEXCAN_MCR_IRMQ_MASK (0x10000U) 206 #define FLEXCAN_MCR_IRMQ_SHIFT (16U) 207 #define FLEXCAN_MCR_IRMQ_WIDTH (1U) 208 #define FLEXCAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_IRMQ_SHIFT)) & FLEXCAN_MCR_IRMQ_MASK) 209 210 #define FLEXCAN_MCR_SRXDIS_MASK (0x20000U) 211 #define FLEXCAN_MCR_SRXDIS_SHIFT (17U) 212 #define FLEXCAN_MCR_SRXDIS_WIDTH (1U) 213 #define FLEXCAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_SRXDIS_SHIFT)) & FLEXCAN_MCR_SRXDIS_MASK) 214 215 #define FLEXCAN_MCR_LPMACK_MASK (0x100000U) 216 #define FLEXCAN_MCR_LPMACK_SHIFT (20U) 217 #define FLEXCAN_MCR_LPMACK_WIDTH (1U) 218 #define FLEXCAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_LPMACK_SHIFT)) & FLEXCAN_MCR_LPMACK_MASK) 219 220 #define FLEXCAN_MCR_WRNEN_MASK (0x200000U) 221 #define FLEXCAN_MCR_WRNEN_SHIFT (21U) 222 #define FLEXCAN_MCR_WRNEN_WIDTH (1U) 223 #define FLEXCAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_WRNEN_SHIFT)) & FLEXCAN_MCR_WRNEN_MASK) 224 225 #define FLEXCAN_MCR_SUPV_MASK (0x800000U) 226 #define FLEXCAN_MCR_SUPV_SHIFT (23U) 227 #define FLEXCAN_MCR_SUPV_WIDTH (1U) 228 #define FLEXCAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_SUPV_SHIFT)) & FLEXCAN_MCR_SUPV_MASK) 229 230 #define FLEXCAN_MCR_FRZACK_MASK (0x1000000U) 231 #define FLEXCAN_MCR_FRZACK_SHIFT (24U) 232 #define FLEXCAN_MCR_FRZACK_WIDTH (1U) 233 #define FLEXCAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_FRZACK_SHIFT)) & FLEXCAN_MCR_FRZACK_MASK) 234 235 #define FLEXCAN_MCR_SOFTRST_MASK (0x2000000U) 236 #define FLEXCAN_MCR_SOFTRST_SHIFT (25U) 237 #define FLEXCAN_MCR_SOFTRST_WIDTH (1U) 238 #define FLEXCAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_SOFTRST_SHIFT)) & FLEXCAN_MCR_SOFTRST_MASK) 239 240 #define FLEXCAN_MCR_NOTRDY_MASK (0x8000000U) 241 #define FLEXCAN_MCR_NOTRDY_SHIFT (27U) 242 #define FLEXCAN_MCR_NOTRDY_WIDTH (1U) 243 #define FLEXCAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_NOTRDY_SHIFT)) & FLEXCAN_MCR_NOTRDY_MASK) 244 245 #define FLEXCAN_MCR_HALT_MASK (0x10000000U) 246 #define FLEXCAN_MCR_HALT_SHIFT (28U) 247 #define FLEXCAN_MCR_HALT_WIDTH (1U) 248 #define FLEXCAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_HALT_SHIFT)) & FLEXCAN_MCR_HALT_MASK) 249 250 #define FLEXCAN_MCR_RFEN_MASK (0x20000000U) 251 #define FLEXCAN_MCR_RFEN_SHIFT (29U) 252 #define FLEXCAN_MCR_RFEN_WIDTH (1U) 253 #define FLEXCAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_RFEN_SHIFT)) & FLEXCAN_MCR_RFEN_MASK) 254 255 #define FLEXCAN_MCR_FRZ_MASK (0x40000000U) 256 #define FLEXCAN_MCR_FRZ_SHIFT (30U) 257 #define FLEXCAN_MCR_FRZ_WIDTH (1U) 258 #define FLEXCAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_FRZ_SHIFT)) & FLEXCAN_MCR_FRZ_MASK) 259 260 #define FLEXCAN_MCR_MDIS_MASK (0x80000000U) 261 #define FLEXCAN_MCR_MDIS_SHIFT (31U) 262 #define FLEXCAN_MCR_MDIS_WIDTH (1U) 263 #define FLEXCAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_MDIS_SHIFT)) & FLEXCAN_MCR_MDIS_MASK) 264 /*! @} */ 265 266 /*! @name CTRL1 - Control 1 Register */ 267 /*! @{ */ 268 269 #define FLEXCAN_CTRL1_PROPSEG_MASK (0x7U) 270 #define FLEXCAN_CTRL1_PROPSEG_SHIFT (0U) 271 #define FLEXCAN_CTRL1_PROPSEG_WIDTH (3U) 272 #define FLEXCAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL1_PROPSEG_SHIFT)) & FLEXCAN_CTRL1_PROPSEG_MASK) 273 274 #define FLEXCAN_CTRL1_LOM_MASK (0x8U) 275 #define FLEXCAN_CTRL1_LOM_SHIFT (3U) 276 #define FLEXCAN_CTRL1_LOM_WIDTH (1U) 277 #define FLEXCAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL1_LOM_SHIFT)) & FLEXCAN_CTRL1_LOM_MASK) 278 279 #define FLEXCAN_CTRL1_LBUF_MASK (0x10U) 280 #define FLEXCAN_CTRL1_LBUF_SHIFT (4U) 281 #define FLEXCAN_CTRL1_LBUF_WIDTH (1U) 282 #define FLEXCAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL1_LBUF_SHIFT)) & FLEXCAN_CTRL1_LBUF_MASK) 283 284 #define FLEXCAN_CTRL1_TSYN_MASK (0x20U) 285 #define FLEXCAN_CTRL1_TSYN_SHIFT (5U) 286 #define FLEXCAN_CTRL1_TSYN_WIDTH (1U) 287 #define FLEXCAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL1_TSYN_SHIFT)) & FLEXCAN_CTRL1_TSYN_MASK) 288 289 #define FLEXCAN_CTRL1_BOFFREC_MASK (0x40U) 290 #define FLEXCAN_CTRL1_BOFFREC_SHIFT (6U) 291 #define FLEXCAN_CTRL1_BOFFREC_WIDTH (1U) 292 #define FLEXCAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL1_BOFFREC_SHIFT)) & FLEXCAN_CTRL1_BOFFREC_MASK) 293 294 #define FLEXCAN_CTRL1_SMP_MASK (0x80U) 295 #define FLEXCAN_CTRL1_SMP_SHIFT (7U) 296 #define FLEXCAN_CTRL1_SMP_WIDTH (1U) 297 #define FLEXCAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL1_SMP_SHIFT)) & FLEXCAN_CTRL1_SMP_MASK) 298 299 #define FLEXCAN_CTRL1_RWRNMSK_MASK (0x400U) 300 #define FLEXCAN_CTRL1_RWRNMSK_SHIFT (10U) 301 #define FLEXCAN_CTRL1_RWRNMSK_WIDTH (1U) 302 #define FLEXCAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL1_RWRNMSK_SHIFT)) & FLEXCAN_CTRL1_RWRNMSK_MASK) 303 304 #define FLEXCAN_CTRL1_TWRNMSK_MASK (0x800U) 305 #define FLEXCAN_CTRL1_TWRNMSK_SHIFT (11U) 306 #define FLEXCAN_CTRL1_TWRNMSK_WIDTH (1U) 307 #define FLEXCAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL1_TWRNMSK_SHIFT)) & FLEXCAN_CTRL1_TWRNMSK_MASK) 308 309 #define FLEXCAN_CTRL1_LPB_MASK (0x1000U) 310 #define FLEXCAN_CTRL1_LPB_SHIFT (12U) 311 #define FLEXCAN_CTRL1_LPB_WIDTH (1U) 312 #define FLEXCAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL1_LPB_SHIFT)) & FLEXCAN_CTRL1_LPB_MASK) 313 314 #define FLEXCAN_CTRL1_ERRMSK_MASK (0x4000U) 315 #define FLEXCAN_CTRL1_ERRMSK_SHIFT (14U) 316 #define FLEXCAN_CTRL1_ERRMSK_WIDTH (1U) 317 #define FLEXCAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL1_ERRMSK_SHIFT)) & FLEXCAN_CTRL1_ERRMSK_MASK) 318 319 #define FLEXCAN_CTRL1_BOFFMSK_MASK (0x8000U) 320 #define FLEXCAN_CTRL1_BOFFMSK_SHIFT (15U) 321 #define FLEXCAN_CTRL1_BOFFMSK_WIDTH (1U) 322 #define FLEXCAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL1_BOFFMSK_SHIFT)) & FLEXCAN_CTRL1_BOFFMSK_MASK) 323 324 #define FLEXCAN_CTRL1_PSEG2_MASK (0x70000U) 325 #define FLEXCAN_CTRL1_PSEG2_SHIFT (16U) 326 #define FLEXCAN_CTRL1_PSEG2_WIDTH (3U) 327 #define FLEXCAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL1_PSEG2_SHIFT)) & FLEXCAN_CTRL1_PSEG2_MASK) 328 329 #define FLEXCAN_CTRL1_PSEG1_MASK (0x380000U) 330 #define FLEXCAN_CTRL1_PSEG1_SHIFT (19U) 331 #define FLEXCAN_CTRL1_PSEG1_WIDTH (3U) 332 #define FLEXCAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL1_PSEG1_SHIFT)) & FLEXCAN_CTRL1_PSEG1_MASK) 333 334 #define FLEXCAN_CTRL1_RJW_MASK (0xC00000U) 335 #define FLEXCAN_CTRL1_RJW_SHIFT (22U) 336 #define FLEXCAN_CTRL1_RJW_WIDTH (2U) 337 #define FLEXCAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL1_RJW_SHIFT)) & FLEXCAN_CTRL1_RJW_MASK) 338 339 #define FLEXCAN_CTRL1_PRESDIV_MASK (0xFF000000U) 340 #define FLEXCAN_CTRL1_PRESDIV_SHIFT (24U) 341 #define FLEXCAN_CTRL1_PRESDIV_WIDTH (8U) 342 #define FLEXCAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL1_PRESDIV_SHIFT)) & FLEXCAN_CTRL1_PRESDIV_MASK) 343 /*! @} */ 344 345 /*! @name TIMER - Free Running Timer */ 346 /*! @{ */ 347 348 #define FLEXCAN_TIMER_TIMER_MASK (0xFFFFU) 349 #define FLEXCAN_TIMER_TIMER_SHIFT (0U) 350 #define FLEXCAN_TIMER_TIMER_WIDTH (16U) 351 #define FLEXCAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_TIMER_TIMER_SHIFT)) & FLEXCAN_TIMER_TIMER_MASK) 352 /*! @} */ 353 354 /*! @name RXMGMASK - Rx Mailboxes Global Mask Register */ 355 /*! @{ */ 356 357 #define FLEXCAN_RXMGMASK_MG_MASK (0xFFFFFFFFU) 358 #define FLEXCAN_RXMGMASK_MG_SHIFT (0U) 359 #define FLEXCAN_RXMGMASK_MG_WIDTH (32U) 360 #define FLEXCAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RXMGMASK_MG_SHIFT)) & FLEXCAN_RXMGMASK_MG_MASK) 361 /*! @} */ 362 363 /*! @name RX14MASK - Rx 14 Mask Register */ 364 /*! @{ */ 365 366 #define FLEXCAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU) 367 #define FLEXCAN_RX14MASK_RX14M_SHIFT (0U) 368 #define FLEXCAN_RX14MASK_RX14M_WIDTH (32U) 369 #define FLEXCAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RX14MASK_RX14M_SHIFT)) & FLEXCAN_RX14MASK_RX14M_MASK) 370 /*! @} */ 371 372 /*! @name RX15MASK - Rx 15 Mask Register */ 373 /*! @{ */ 374 375 #define FLEXCAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU) 376 #define FLEXCAN_RX15MASK_RX15M_SHIFT (0U) 377 #define FLEXCAN_RX15MASK_RX15M_WIDTH (32U) 378 #define FLEXCAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RX15MASK_RX15M_SHIFT)) & FLEXCAN_RX15MASK_RX15M_MASK) 379 /*! @} */ 380 381 /*! @name ECR - Error Counter */ 382 /*! @{ */ 383 384 #define FLEXCAN_ECR_TXERRCNT_MASK (0xFFU) 385 #define FLEXCAN_ECR_TXERRCNT_SHIFT (0U) 386 #define FLEXCAN_ECR_TXERRCNT_WIDTH (8U) 387 #define FLEXCAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ECR_TXERRCNT_SHIFT)) & FLEXCAN_ECR_TXERRCNT_MASK) 388 389 #define FLEXCAN_ECR_RXERRCNT_MASK (0xFF00U) 390 #define FLEXCAN_ECR_RXERRCNT_SHIFT (8U) 391 #define FLEXCAN_ECR_RXERRCNT_WIDTH (8U) 392 #define FLEXCAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ECR_RXERRCNT_SHIFT)) & FLEXCAN_ECR_RXERRCNT_MASK) 393 394 #define FLEXCAN_ECR_TXERRCNT_FAST_MASK (0xFF0000U) 395 #define FLEXCAN_ECR_TXERRCNT_FAST_SHIFT (16U) 396 #define FLEXCAN_ECR_TXERRCNT_FAST_WIDTH (8U) 397 #define FLEXCAN_ECR_TXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ECR_TXERRCNT_FAST_SHIFT)) & FLEXCAN_ECR_TXERRCNT_FAST_MASK) 398 399 #define FLEXCAN_ECR_RXERRCNT_FAST_MASK (0xFF000000U) 400 #define FLEXCAN_ECR_RXERRCNT_FAST_SHIFT (24U) 401 #define FLEXCAN_ECR_RXERRCNT_FAST_WIDTH (8U) 402 #define FLEXCAN_ECR_RXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ECR_RXERRCNT_FAST_SHIFT)) & FLEXCAN_ECR_RXERRCNT_FAST_MASK) 403 /*! @} */ 404 405 /*! @name ESR1 - Error and Status 1 Register */ 406 /*! @{ */ 407 408 #define FLEXCAN_ESR1_ERRINT_MASK (0x2U) 409 #define FLEXCAN_ESR1_ERRINT_SHIFT (1U) 410 #define FLEXCAN_ESR1_ERRINT_WIDTH (1U) 411 #define FLEXCAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_ERRINT_SHIFT)) & FLEXCAN_ESR1_ERRINT_MASK) 412 413 #define FLEXCAN_ESR1_BOFFINT_MASK (0x4U) 414 #define FLEXCAN_ESR1_BOFFINT_SHIFT (2U) 415 #define FLEXCAN_ESR1_BOFFINT_WIDTH (1U) 416 #define FLEXCAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_BOFFINT_SHIFT)) & FLEXCAN_ESR1_BOFFINT_MASK) 417 418 #define FLEXCAN_ESR1_RX_MASK (0x8U) 419 #define FLEXCAN_ESR1_RX_SHIFT (3U) 420 #define FLEXCAN_ESR1_RX_WIDTH (1U) 421 #define FLEXCAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_RX_SHIFT)) & FLEXCAN_ESR1_RX_MASK) 422 423 #define FLEXCAN_ESR1_FLTCONF_MASK (0x30U) 424 #define FLEXCAN_ESR1_FLTCONF_SHIFT (4U) 425 #define FLEXCAN_ESR1_FLTCONF_WIDTH (2U) 426 #define FLEXCAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_FLTCONF_SHIFT)) & FLEXCAN_ESR1_FLTCONF_MASK) 427 428 #define FLEXCAN_ESR1_TX_MASK (0x40U) 429 #define FLEXCAN_ESR1_TX_SHIFT (6U) 430 #define FLEXCAN_ESR1_TX_WIDTH (1U) 431 #define FLEXCAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_TX_SHIFT)) & FLEXCAN_ESR1_TX_MASK) 432 433 #define FLEXCAN_ESR1_IDLE_MASK (0x80U) 434 #define FLEXCAN_ESR1_IDLE_SHIFT (7U) 435 #define FLEXCAN_ESR1_IDLE_WIDTH (1U) 436 #define FLEXCAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_IDLE_SHIFT)) & FLEXCAN_ESR1_IDLE_MASK) 437 438 #define FLEXCAN_ESR1_RXWRN_MASK (0x100U) 439 #define FLEXCAN_ESR1_RXWRN_SHIFT (8U) 440 #define FLEXCAN_ESR1_RXWRN_WIDTH (1U) 441 #define FLEXCAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_RXWRN_SHIFT)) & FLEXCAN_ESR1_RXWRN_MASK) 442 443 #define FLEXCAN_ESR1_TXWRN_MASK (0x200U) 444 #define FLEXCAN_ESR1_TXWRN_SHIFT (9U) 445 #define FLEXCAN_ESR1_TXWRN_WIDTH (1U) 446 #define FLEXCAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_TXWRN_SHIFT)) & FLEXCAN_ESR1_TXWRN_MASK) 447 448 #define FLEXCAN_ESR1_STFERR_MASK (0x400U) 449 #define FLEXCAN_ESR1_STFERR_SHIFT (10U) 450 #define FLEXCAN_ESR1_STFERR_WIDTH (1U) 451 #define FLEXCAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_STFERR_SHIFT)) & FLEXCAN_ESR1_STFERR_MASK) 452 453 #define FLEXCAN_ESR1_FRMERR_MASK (0x800U) 454 #define FLEXCAN_ESR1_FRMERR_SHIFT (11U) 455 #define FLEXCAN_ESR1_FRMERR_WIDTH (1U) 456 #define FLEXCAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_FRMERR_SHIFT)) & FLEXCAN_ESR1_FRMERR_MASK) 457 458 #define FLEXCAN_ESR1_CRCERR_MASK (0x1000U) 459 #define FLEXCAN_ESR1_CRCERR_SHIFT (12U) 460 #define FLEXCAN_ESR1_CRCERR_WIDTH (1U) 461 #define FLEXCAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_CRCERR_SHIFT)) & FLEXCAN_ESR1_CRCERR_MASK) 462 463 #define FLEXCAN_ESR1_ACKERR_MASK (0x2000U) 464 #define FLEXCAN_ESR1_ACKERR_SHIFT (13U) 465 #define FLEXCAN_ESR1_ACKERR_WIDTH (1U) 466 #define FLEXCAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_ACKERR_SHIFT)) & FLEXCAN_ESR1_ACKERR_MASK) 467 468 #define FLEXCAN_ESR1_BIT0ERR_MASK (0x4000U) 469 #define FLEXCAN_ESR1_BIT0ERR_SHIFT (14U) 470 #define FLEXCAN_ESR1_BIT0ERR_WIDTH (1U) 471 #define FLEXCAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_BIT0ERR_SHIFT)) & FLEXCAN_ESR1_BIT0ERR_MASK) 472 473 #define FLEXCAN_ESR1_BIT1ERR_MASK (0x8000U) 474 #define FLEXCAN_ESR1_BIT1ERR_SHIFT (15U) 475 #define FLEXCAN_ESR1_BIT1ERR_WIDTH (1U) 476 #define FLEXCAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_BIT1ERR_SHIFT)) & FLEXCAN_ESR1_BIT1ERR_MASK) 477 478 #define FLEXCAN_ESR1_RWRNINT_MASK (0x10000U) 479 #define FLEXCAN_ESR1_RWRNINT_SHIFT (16U) 480 #define FLEXCAN_ESR1_RWRNINT_WIDTH (1U) 481 #define FLEXCAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_RWRNINT_SHIFT)) & FLEXCAN_ESR1_RWRNINT_MASK) 482 483 #define FLEXCAN_ESR1_TWRNINT_MASK (0x20000U) 484 #define FLEXCAN_ESR1_TWRNINT_SHIFT (17U) 485 #define FLEXCAN_ESR1_TWRNINT_WIDTH (1U) 486 #define FLEXCAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_TWRNINT_SHIFT)) & FLEXCAN_ESR1_TWRNINT_MASK) 487 488 #define FLEXCAN_ESR1_SYNCH_MASK (0x40000U) 489 #define FLEXCAN_ESR1_SYNCH_SHIFT (18U) 490 #define FLEXCAN_ESR1_SYNCH_WIDTH (1U) 491 #define FLEXCAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_SYNCH_SHIFT)) & FLEXCAN_ESR1_SYNCH_MASK) 492 493 #define FLEXCAN_ESR1_BOFFDONEINT_MASK (0x80000U) 494 #define FLEXCAN_ESR1_BOFFDONEINT_SHIFT (19U) 495 #define FLEXCAN_ESR1_BOFFDONEINT_WIDTH (1U) 496 #define FLEXCAN_ESR1_BOFFDONEINT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_BOFFDONEINT_SHIFT)) & FLEXCAN_ESR1_BOFFDONEINT_MASK) 497 498 #define FLEXCAN_ESR1_ERRINT_FAST_MASK (0x100000U) 499 #define FLEXCAN_ESR1_ERRINT_FAST_SHIFT (20U) 500 #define FLEXCAN_ESR1_ERRINT_FAST_WIDTH (1U) 501 #define FLEXCAN_ESR1_ERRINT_FAST(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_ERRINT_FAST_SHIFT)) & FLEXCAN_ESR1_ERRINT_FAST_MASK) 502 503 #define FLEXCAN_ESR1_ERROVR_MASK (0x200000U) 504 #define FLEXCAN_ESR1_ERROVR_SHIFT (21U) 505 #define FLEXCAN_ESR1_ERROVR_WIDTH (1U) 506 #define FLEXCAN_ESR1_ERROVR(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_ERROVR_SHIFT)) & FLEXCAN_ESR1_ERROVR_MASK) 507 508 #define FLEXCAN_ESR1_STFERR_FAST_MASK (0x4000000U) 509 #define FLEXCAN_ESR1_STFERR_FAST_SHIFT (26U) 510 #define FLEXCAN_ESR1_STFERR_FAST_WIDTH (1U) 511 #define FLEXCAN_ESR1_STFERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_STFERR_FAST_SHIFT)) & FLEXCAN_ESR1_STFERR_FAST_MASK) 512 513 #define FLEXCAN_ESR1_FRMERR_FAST_MASK (0x8000000U) 514 #define FLEXCAN_ESR1_FRMERR_FAST_SHIFT (27U) 515 #define FLEXCAN_ESR1_FRMERR_FAST_WIDTH (1U) 516 #define FLEXCAN_ESR1_FRMERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_FRMERR_FAST_SHIFT)) & FLEXCAN_ESR1_FRMERR_FAST_MASK) 517 518 #define FLEXCAN_ESR1_CRCERR_FAST_MASK (0x10000000U) 519 #define FLEXCAN_ESR1_CRCERR_FAST_SHIFT (28U) 520 #define FLEXCAN_ESR1_CRCERR_FAST_WIDTH (1U) 521 #define FLEXCAN_ESR1_CRCERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_CRCERR_FAST_SHIFT)) & FLEXCAN_ESR1_CRCERR_FAST_MASK) 522 523 #define FLEXCAN_ESR1_BIT0ERR_FAST_MASK (0x40000000U) 524 #define FLEXCAN_ESR1_BIT0ERR_FAST_SHIFT (30U) 525 #define FLEXCAN_ESR1_BIT0ERR_FAST_WIDTH (1U) 526 #define FLEXCAN_ESR1_BIT0ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_BIT0ERR_FAST_SHIFT)) & FLEXCAN_ESR1_BIT0ERR_FAST_MASK) 527 528 #define FLEXCAN_ESR1_BIT1ERR_FAST_MASK (0x80000000U) 529 #define FLEXCAN_ESR1_BIT1ERR_FAST_SHIFT (31U) 530 #define FLEXCAN_ESR1_BIT1ERR_FAST_WIDTH (1U) 531 #define FLEXCAN_ESR1_BIT1ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_BIT1ERR_FAST_SHIFT)) & FLEXCAN_ESR1_BIT1ERR_FAST_MASK) 532 /*! @} */ 533 534 /*! @name IMASK2 - Interrupt Masks 2 Register */ 535 /*! @{ */ 536 537 #define FLEXCAN_IMASK2_BUF63TO32M_MASK (0xFFFFFFFFU) 538 #define FLEXCAN_IMASK2_BUF63TO32M_SHIFT (0U) 539 #define FLEXCAN_IMASK2_BUF63TO32M_WIDTH (32U) 540 #define FLEXCAN_IMASK2_BUF63TO32M(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_IMASK2_BUF63TO32M_SHIFT)) & FLEXCAN_IMASK2_BUF63TO32M_MASK) 541 /*! @} */ 542 543 /*! @name IMASK1 - Interrupt Masks 1 Register */ 544 /*! @{ */ 545 546 #define FLEXCAN_IMASK1_BUF31TO0M_MASK (0xFFFFFFFFU) 547 #define FLEXCAN_IMASK1_BUF31TO0M_SHIFT (0U) 548 #define FLEXCAN_IMASK1_BUF31TO0M_WIDTH (32U) 549 #define FLEXCAN_IMASK1_BUF31TO0M(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_IMASK1_BUF31TO0M_SHIFT)) & FLEXCAN_IMASK1_BUF31TO0M_MASK) 550 /*! @} */ 551 552 /*! @name IFLAG2 - Interrupt Flags 2 Register */ 553 /*! @{ */ 554 555 #define FLEXCAN_IFLAG2_BUF63TO32I_MASK (0xFFFFFFFFU) 556 #define FLEXCAN_IFLAG2_BUF63TO32I_SHIFT (0U) 557 #define FLEXCAN_IFLAG2_BUF63TO32I_WIDTH (32U) 558 #define FLEXCAN_IFLAG2_BUF63TO32I(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_IFLAG2_BUF63TO32I_SHIFT)) & FLEXCAN_IFLAG2_BUF63TO32I_MASK) 559 /*! @} */ 560 561 /*! @name IFLAG1 - Interrupt Flags 1 Register */ 562 /*! @{ */ 563 564 #define FLEXCAN_IFLAG1_BUF0I_MASK (0x1U) 565 #define FLEXCAN_IFLAG1_BUF0I_SHIFT (0U) 566 #define FLEXCAN_IFLAG1_BUF0I_WIDTH (1U) 567 #define FLEXCAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_IFLAG1_BUF0I_SHIFT)) & FLEXCAN_IFLAG1_BUF0I_MASK) 568 569 #define FLEXCAN_IFLAG1_BUF4TO1I_MASK (0x1EU) 570 #define FLEXCAN_IFLAG1_BUF4TO1I_SHIFT (1U) 571 #define FLEXCAN_IFLAG1_BUF4TO1I_WIDTH (4U) 572 #define FLEXCAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_IFLAG1_BUF4TO1I_SHIFT)) & FLEXCAN_IFLAG1_BUF4TO1I_MASK) 573 574 #define FLEXCAN_IFLAG1_BUF5I_MASK (0x20U) 575 #define FLEXCAN_IFLAG1_BUF5I_SHIFT (5U) 576 #define FLEXCAN_IFLAG1_BUF5I_WIDTH (1U) 577 #define FLEXCAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_IFLAG1_BUF5I_SHIFT)) & FLEXCAN_IFLAG1_BUF5I_MASK) 578 579 #define FLEXCAN_IFLAG1_BUF6I_MASK (0x40U) 580 #define FLEXCAN_IFLAG1_BUF6I_SHIFT (6U) 581 #define FLEXCAN_IFLAG1_BUF6I_WIDTH (1U) 582 #define FLEXCAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_IFLAG1_BUF6I_SHIFT)) & FLEXCAN_IFLAG1_BUF6I_MASK) 583 584 #define FLEXCAN_IFLAG1_BUF7I_MASK (0x80U) 585 #define FLEXCAN_IFLAG1_BUF7I_SHIFT (7U) 586 #define FLEXCAN_IFLAG1_BUF7I_WIDTH (1U) 587 #define FLEXCAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_IFLAG1_BUF7I_SHIFT)) & FLEXCAN_IFLAG1_BUF7I_MASK) 588 589 #define FLEXCAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U) 590 #define FLEXCAN_IFLAG1_BUF31TO8I_SHIFT (8U) 591 #define FLEXCAN_IFLAG1_BUF31TO8I_WIDTH (24U) 592 #define FLEXCAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_IFLAG1_BUF31TO8I_SHIFT)) & FLEXCAN_IFLAG1_BUF31TO8I_MASK) 593 /*! @} */ 594 595 /*! @name CTRL2 - Control 2 Register */ 596 /*! @{ */ 597 598 #define FLEXCAN_CTRL2_TSTAMPCAP_MASK (0xC0U) 599 #define FLEXCAN_CTRL2_TSTAMPCAP_SHIFT (6U) 600 #define FLEXCAN_CTRL2_TSTAMPCAP_WIDTH (2U) 601 #define FLEXCAN_CTRL2_TSTAMPCAP(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL2_TSTAMPCAP_SHIFT)) & FLEXCAN_CTRL2_TSTAMPCAP_MASK) 602 603 #define FLEXCAN_CTRL2_MBTSBASE_MASK (0x300U) 604 #define FLEXCAN_CTRL2_MBTSBASE_SHIFT (8U) 605 #define FLEXCAN_CTRL2_MBTSBASE_WIDTH (2U) 606 #define FLEXCAN_CTRL2_MBTSBASE(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL2_MBTSBASE_SHIFT)) & FLEXCAN_CTRL2_MBTSBASE_MASK) 607 608 #define FLEXCAN_CTRL2_EDFLTDIS_MASK (0x800U) 609 #define FLEXCAN_CTRL2_EDFLTDIS_SHIFT (11U) 610 #define FLEXCAN_CTRL2_EDFLTDIS_WIDTH (1U) 611 #define FLEXCAN_CTRL2_EDFLTDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL2_EDFLTDIS_SHIFT)) & FLEXCAN_CTRL2_EDFLTDIS_MASK) 612 613 #define FLEXCAN_CTRL2_ISOCANFDEN_MASK (0x1000U) 614 #define FLEXCAN_CTRL2_ISOCANFDEN_SHIFT (12U) 615 #define FLEXCAN_CTRL2_ISOCANFDEN_WIDTH (1U) 616 #define FLEXCAN_CTRL2_ISOCANFDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL2_ISOCANFDEN_SHIFT)) & FLEXCAN_CTRL2_ISOCANFDEN_MASK) 617 618 #define FLEXCAN_CTRL2_BTE_MASK (0x2000U) 619 #define FLEXCAN_CTRL2_BTE_SHIFT (13U) 620 #define FLEXCAN_CTRL2_BTE_WIDTH (1U) 621 #define FLEXCAN_CTRL2_BTE(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL2_BTE_SHIFT)) & FLEXCAN_CTRL2_BTE_MASK) 622 623 #define FLEXCAN_CTRL2_PREXCEN_MASK (0x4000U) 624 #define FLEXCAN_CTRL2_PREXCEN_SHIFT (14U) 625 #define FLEXCAN_CTRL2_PREXCEN_WIDTH (1U) 626 #define FLEXCAN_CTRL2_PREXCEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL2_PREXCEN_SHIFT)) & FLEXCAN_CTRL2_PREXCEN_MASK) 627 628 #define FLEXCAN_CTRL2_TIMER_SRC_MASK (0x8000U) 629 #define FLEXCAN_CTRL2_TIMER_SRC_SHIFT (15U) 630 #define FLEXCAN_CTRL2_TIMER_SRC_WIDTH (1U) 631 #define FLEXCAN_CTRL2_TIMER_SRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL2_TIMER_SRC_SHIFT)) & FLEXCAN_CTRL2_TIMER_SRC_MASK) 632 633 #define FLEXCAN_CTRL2_EACEN_MASK (0x10000U) 634 #define FLEXCAN_CTRL2_EACEN_SHIFT (16U) 635 #define FLEXCAN_CTRL2_EACEN_WIDTH (1U) 636 #define FLEXCAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL2_EACEN_SHIFT)) & FLEXCAN_CTRL2_EACEN_MASK) 637 638 #define FLEXCAN_CTRL2_RRS_MASK (0x20000U) 639 #define FLEXCAN_CTRL2_RRS_SHIFT (17U) 640 #define FLEXCAN_CTRL2_RRS_WIDTH (1U) 641 #define FLEXCAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL2_RRS_SHIFT)) & FLEXCAN_CTRL2_RRS_MASK) 642 643 #define FLEXCAN_CTRL2_MRP_MASK (0x40000U) 644 #define FLEXCAN_CTRL2_MRP_SHIFT (18U) 645 #define FLEXCAN_CTRL2_MRP_WIDTH (1U) 646 #define FLEXCAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL2_MRP_SHIFT)) & FLEXCAN_CTRL2_MRP_MASK) 647 648 #define FLEXCAN_CTRL2_TASD_MASK (0xF80000U) 649 #define FLEXCAN_CTRL2_TASD_SHIFT (19U) 650 #define FLEXCAN_CTRL2_TASD_WIDTH (5U) 651 #define FLEXCAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL2_TASD_SHIFT)) & FLEXCAN_CTRL2_TASD_MASK) 652 653 #define FLEXCAN_CTRL2_RFFN_MASK (0xF000000U) 654 #define FLEXCAN_CTRL2_RFFN_SHIFT (24U) 655 #define FLEXCAN_CTRL2_RFFN_WIDTH (4U) 656 #define FLEXCAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL2_RFFN_SHIFT)) & FLEXCAN_CTRL2_RFFN_MASK) 657 658 #define FLEXCAN_CTRL2_WRMFRZ_MASK (0x10000000U) 659 #define FLEXCAN_CTRL2_WRMFRZ_SHIFT (28U) 660 #define FLEXCAN_CTRL2_WRMFRZ_WIDTH (1U) 661 #define FLEXCAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL2_WRMFRZ_SHIFT)) & FLEXCAN_CTRL2_WRMFRZ_MASK) 662 663 #define FLEXCAN_CTRL2_ECRWRE_MASK (0x20000000U) 664 #define FLEXCAN_CTRL2_ECRWRE_SHIFT (29U) 665 #define FLEXCAN_CTRL2_ECRWRE_WIDTH (1U) 666 #define FLEXCAN_CTRL2_ECRWRE(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL2_ECRWRE_SHIFT)) & FLEXCAN_CTRL2_ECRWRE_MASK) 667 668 #define FLEXCAN_CTRL2_BOFFDONEMSK_MASK (0x40000000U) 669 #define FLEXCAN_CTRL2_BOFFDONEMSK_SHIFT (30U) 670 #define FLEXCAN_CTRL2_BOFFDONEMSK_WIDTH (1U) 671 #define FLEXCAN_CTRL2_BOFFDONEMSK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL2_BOFFDONEMSK_SHIFT)) & FLEXCAN_CTRL2_BOFFDONEMSK_MASK) 672 673 #define FLEXCAN_CTRL2_ERRMSK_FAST_MASK (0x80000000U) 674 #define FLEXCAN_CTRL2_ERRMSK_FAST_SHIFT (31U) 675 #define FLEXCAN_CTRL2_ERRMSK_FAST_WIDTH (1U) 676 #define FLEXCAN_CTRL2_ERRMSK_FAST(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL2_ERRMSK_FAST_SHIFT)) & FLEXCAN_CTRL2_ERRMSK_FAST_MASK) 677 /*! @} */ 678 679 /*! @name ESR2 - Error and Status 2 Register */ 680 /*! @{ */ 681 682 #define FLEXCAN_ESR2_IMB_MASK (0x2000U) 683 #define FLEXCAN_ESR2_IMB_SHIFT (13U) 684 #define FLEXCAN_ESR2_IMB_WIDTH (1U) 685 #define FLEXCAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR2_IMB_SHIFT)) & FLEXCAN_ESR2_IMB_MASK) 686 687 #define FLEXCAN_ESR2_VPS_MASK (0x4000U) 688 #define FLEXCAN_ESR2_VPS_SHIFT (14U) 689 #define FLEXCAN_ESR2_VPS_WIDTH (1U) 690 #define FLEXCAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR2_VPS_SHIFT)) & FLEXCAN_ESR2_VPS_MASK) 691 692 #define FLEXCAN_ESR2_LPTM_MASK (0x7F0000U) 693 #define FLEXCAN_ESR2_LPTM_SHIFT (16U) 694 #define FLEXCAN_ESR2_LPTM_WIDTH (7U) 695 #define FLEXCAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR2_LPTM_SHIFT)) & FLEXCAN_ESR2_LPTM_MASK) 696 /*! @} */ 697 698 /*! @name CRCR - CRC Register */ 699 /*! @{ */ 700 701 #define FLEXCAN_CRCR_TXCRC_MASK (0x7FFFU) 702 #define FLEXCAN_CRCR_TXCRC_SHIFT (0U) 703 #define FLEXCAN_CRCR_TXCRC_WIDTH (15U) 704 #define FLEXCAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CRCR_TXCRC_SHIFT)) & FLEXCAN_CRCR_TXCRC_MASK) 705 706 #define FLEXCAN_CRCR_MBCRC_MASK (0x7F0000U) 707 #define FLEXCAN_CRCR_MBCRC_SHIFT (16U) 708 #define FLEXCAN_CRCR_MBCRC_WIDTH (7U) 709 #define FLEXCAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CRCR_MBCRC_SHIFT)) & FLEXCAN_CRCR_MBCRC_MASK) 710 /*! @} */ 711 712 /*! @name RXFGMASK - Legacy Rx FIFO Global Mask Register..Rx FIFO Global Mask Register */ 713 /*! @{ */ 714 715 #define FLEXCAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU) 716 #define FLEXCAN_RXFGMASK_FGM_SHIFT (0U) 717 #define FLEXCAN_RXFGMASK_FGM_WIDTH (32U) 718 #define FLEXCAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RXFGMASK_FGM_SHIFT)) & FLEXCAN_RXFGMASK_FGM_MASK) 719 /*! @} */ 720 721 /*! @name RXFIR - Legacy Rx FIFO Information Register..Rx FIFO Information Register */ 722 /*! @{ */ 723 724 #define FLEXCAN_RXFIR_IDHIT_MASK (0x1FFU) 725 #define FLEXCAN_RXFIR_IDHIT_SHIFT (0U) 726 #define FLEXCAN_RXFIR_IDHIT_WIDTH (9U) 727 #define FLEXCAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RXFIR_IDHIT_SHIFT)) & FLEXCAN_RXFIR_IDHIT_MASK) 728 /*! @} */ 729 730 /*! @name CBT - CAN Bit Timing Register */ 731 /*! @{ */ 732 733 #define FLEXCAN_CBT_EPSEG2_MASK (0x1FU) 734 #define FLEXCAN_CBT_EPSEG2_SHIFT (0U) 735 #define FLEXCAN_CBT_EPSEG2_WIDTH (5U) 736 #define FLEXCAN_CBT_EPSEG2(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CBT_EPSEG2_SHIFT)) & FLEXCAN_CBT_EPSEG2_MASK) 737 738 #define FLEXCAN_CBT_EPSEG1_MASK (0x3E0U) 739 #define FLEXCAN_CBT_EPSEG1_SHIFT (5U) 740 #define FLEXCAN_CBT_EPSEG1_WIDTH (5U) 741 #define FLEXCAN_CBT_EPSEG1(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CBT_EPSEG1_SHIFT)) & FLEXCAN_CBT_EPSEG1_MASK) 742 743 #define FLEXCAN_CBT_EPROPSEG_MASK (0xFC00U) 744 #define FLEXCAN_CBT_EPROPSEG_SHIFT (10U) 745 #define FLEXCAN_CBT_EPROPSEG_WIDTH (6U) 746 #define FLEXCAN_CBT_EPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CBT_EPROPSEG_SHIFT)) & FLEXCAN_CBT_EPROPSEG_MASK) 747 748 #define FLEXCAN_CBT_ERJW_MASK (0x1F0000U) 749 #define FLEXCAN_CBT_ERJW_SHIFT (16U) 750 #define FLEXCAN_CBT_ERJW_WIDTH (5U) 751 #define FLEXCAN_CBT_ERJW(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CBT_ERJW_SHIFT)) & FLEXCAN_CBT_ERJW_MASK) 752 753 #define FLEXCAN_CBT_EPRESDIV_MASK (0x7FE00000U) 754 #define FLEXCAN_CBT_EPRESDIV_SHIFT (21U) 755 #define FLEXCAN_CBT_EPRESDIV_WIDTH (10U) 756 #define FLEXCAN_CBT_EPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CBT_EPRESDIV_SHIFT)) & FLEXCAN_CBT_EPRESDIV_MASK) 757 758 #define FLEXCAN_CBT_BTF_MASK (0x80000000U) 759 #define FLEXCAN_CBT_BTF_SHIFT (31U) 760 #define FLEXCAN_CBT_BTF_WIDTH (1U) 761 #define FLEXCAN_CBT_BTF(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CBT_BTF_SHIFT)) & FLEXCAN_CBT_BTF_MASK) 762 /*! @} */ 763 764 /*! @name IMASK3 - Interrupt Masks 3 Register */ 765 /*! @{ */ 766 767 #define FLEXCAN_IMASK3_BUF95TO64M_MASK (0xFFFFFFFFU) 768 #define FLEXCAN_IMASK3_BUF95TO64M_SHIFT (0U) 769 #define FLEXCAN_IMASK3_BUF95TO64M_WIDTH (32U) 770 #define FLEXCAN_IMASK3_BUF95TO64M(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_IMASK3_BUF95TO64M_SHIFT)) & FLEXCAN_IMASK3_BUF95TO64M_MASK) 771 /*! @} */ 772 773 /*! @name IFLAG3 - Interrupt Flags 3 Register */ 774 /*! @{ */ 775 776 #define FLEXCAN_IFLAG3_BUF95TO64_MASK (0xFFFFFFFFU) 777 #define FLEXCAN_IFLAG3_BUF95TO64_SHIFT (0U) 778 #define FLEXCAN_IFLAG3_BUF95TO64_WIDTH (32U) 779 #define FLEXCAN_IFLAG3_BUF95TO64(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_IFLAG3_BUF95TO64_SHIFT)) & FLEXCAN_IFLAG3_BUF95TO64_MASK) 780 /*! @} */ 781 782 /*! @name RXIMR - Rx Individual Mask Registers */ 783 /*! @{ */ 784 785 #define FLEXCAN_RXIMR_MI_MASK (0xFFFFFFFFU) 786 #define FLEXCAN_RXIMR_MI_SHIFT (0U) 787 #define FLEXCAN_RXIMR_MI_WIDTH (32U) 788 #define FLEXCAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RXIMR_MI_SHIFT)) & FLEXCAN_RXIMR_MI_MASK) 789 /*! @} */ 790 791 /*! @name MECR - Memory Error Control Register */ 792 /*! @{ */ 793 794 #define FLEXCAN_MECR_NCEFAFRZ_MASK (0x80U) 795 #define FLEXCAN_MECR_NCEFAFRZ_SHIFT (7U) 796 #define FLEXCAN_MECR_NCEFAFRZ_WIDTH (1U) 797 #define FLEXCAN_MECR_NCEFAFRZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MECR_NCEFAFRZ_SHIFT)) & FLEXCAN_MECR_NCEFAFRZ_MASK) 798 799 #define FLEXCAN_MECR_ECCDIS_MASK (0x100U) 800 #define FLEXCAN_MECR_ECCDIS_SHIFT (8U) 801 #define FLEXCAN_MECR_ECCDIS_WIDTH (1U) 802 #define FLEXCAN_MECR_ECCDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MECR_ECCDIS_SHIFT)) & FLEXCAN_MECR_ECCDIS_MASK) 803 804 #define FLEXCAN_MECR_RERRDIS_MASK (0x200U) 805 #define FLEXCAN_MECR_RERRDIS_SHIFT (9U) 806 #define FLEXCAN_MECR_RERRDIS_WIDTH (1U) 807 #define FLEXCAN_MECR_RERRDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MECR_RERRDIS_SHIFT)) & FLEXCAN_MECR_RERRDIS_MASK) 808 809 #define FLEXCAN_MECR_EXTERRIE_MASK (0x2000U) 810 #define FLEXCAN_MECR_EXTERRIE_SHIFT (13U) 811 #define FLEXCAN_MECR_EXTERRIE_WIDTH (1U) 812 #define FLEXCAN_MECR_EXTERRIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MECR_EXTERRIE_SHIFT)) & FLEXCAN_MECR_EXTERRIE_MASK) 813 814 #define FLEXCAN_MECR_FAERRIE_MASK (0x4000U) 815 #define FLEXCAN_MECR_FAERRIE_SHIFT (14U) 816 #define FLEXCAN_MECR_FAERRIE_WIDTH (1U) 817 #define FLEXCAN_MECR_FAERRIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MECR_FAERRIE_SHIFT)) & FLEXCAN_MECR_FAERRIE_MASK) 818 819 #define FLEXCAN_MECR_HAERRIE_MASK (0x8000U) 820 #define FLEXCAN_MECR_HAERRIE_SHIFT (15U) 821 #define FLEXCAN_MECR_HAERRIE_WIDTH (1U) 822 #define FLEXCAN_MECR_HAERRIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MECR_HAERRIE_SHIFT)) & FLEXCAN_MECR_HAERRIE_MASK) 823 824 #define FLEXCAN_MECR_CEI_MSK_MASK (0x10000U) 825 #define FLEXCAN_MECR_CEI_MSK_SHIFT (16U) 826 #define FLEXCAN_MECR_CEI_MSK_WIDTH (1U) 827 #define FLEXCAN_MECR_CEI_MSK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MECR_CEI_MSK_SHIFT)) & FLEXCAN_MECR_CEI_MSK_MASK) 828 829 #define FLEXCAN_MECR_FANCEI_MSK_MASK (0x40000U) 830 #define FLEXCAN_MECR_FANCEI_MSK_SHIFT (18U) 831 #define FLEXCAN_MECR_FANCEI_MSK_WIDTH (1U) 832 #define FLEXCAN_MECR_FANCEI_MSK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MECR_FANCEI_MSK_SHIFT)) & FLEXCAN_MECR_FANCEI_MSK_MASK) 833 834 #define FLEXCAN_MECR_HANCEI_MSK_MASK (0x80000U) 835 #define FLEXCAN_MECR_HANCEI_MSK_SHIFT (19U) 836 #define FLEXCAN_MECR_HANCEI_MSK_WIDTH (1U) 837 #define FLEXCAN_MECR_HANCEI_MSK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MECR_HANCEI_MSK_SHIFT)) & FLEXCAN_MECR_HANCEI_MSK_MASK) 838 839 #define FLEXCAN_MECR_ECRWRDIS_MASK (0x80000000U) 840 #define FLEXCAN_MECR_ECRWRDIS_SHIFT (31U) 841 #define FLEXCAN_MECR_ECRWRDIS_WIDTH (1U) 842 #define FLEXCAN_MECR_ECRWRDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MECR_ECRWRDIS_SHIFT)) & FLEXCAN_MECR_ECRWRDIS_MASK) 843 /*! @} */ 844 845 /*! @name ERRIAR - Error Injection Address Register */ 846 /*! @{ */ 847 848 #define FLEXCAN_ERRIAR_INJADDR_L_MASK (0x3U) 849 #define FLEXCAN_ERRIAR_INJADDR_L_SHIFT (0U) 850 #define FLEXCAN_ERRIAR_INJADDR_L_WIDTH (2U) 851 #define FLEXCAN_ERRIAR_INJADDR_L(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERRIAR_INJADDR_L_SHIFT)) & FLEXCAN_ERRIAR_INJADDR_L_MASK) 852 853 #define FLEXCAN_ERRIAR_INJADDR_H_MASK (0x3FFCU) 854 #define FLEXCAN_ERRIAR_INJADDR_H_SHIFT (2U) 855 #define FLEXCAN_ERRIAR_INJADDR_H_WIDTH (12U) 856 #define FLEXCAN_ERRIAR_INJADDR_H(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERRIAR_INJADDR_H_SHIFT)) & FLEXCAN_ERRIAR_INJADDR_H_MASK) 857 /*! @} */ 858 859 /*! @name ERRIDPR - Error Injection Data Pattern Register */ 860 /*! @{ */ 861 862 #define FLEXCAN_ERRIDPR_DFLIP_MASK (0xFFFFFFFFU) 863 #define FLEXCAN_ERRIDPR_DFLIP_SHIFT (0U) 864 #define FLEXCAN_ERRIDPR_DFLIP_WIDTH (32U) 865 #define FLEXCAN_ERRIDPR_DFLIP(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERRIDPR_DFLIP_SHIFT)) & FLEXCAN_ERRIDPR_DFLIP_MASK) 866 /*! @} */ 867 868 /*! @name ERRIPPR - Error Injection Parity Pattern Register */ 869 /*! @{ */ 870 871 #define FLEXCAN_ERRIPPR_PFLIP0_MASK (0x1FU) 872 #define FLEXCAN_ERRIPPR_PFLIP0_SHIFT (0U) 873 #define FLEXCAN_ERRIPPR_PFLIP0_WIDTH (5U) 874 #define FLEXCAN_ERRIPPR_PFLIP0(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERRIPPR_PFLIP0_SHIFT)) & FLEXCAN_ERRIPPR_PFLIP0_MASK) 875 876 #define FLEXCAN_ERRIPPR_PFLIP1_MASK (0x1F00U) 877 #define FLEXCAN_ERRIPPR_PFLIP1_SHIFT (8U) 878 #define FLEXCAN_ERRIPPR_PFLIP1_WIDTH (5U) 879 #define FLEXCAN_ERRIPPR_PFLIP1(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERRIPPR_PFLIP1_SHIFT)) & FLEXCAN_ERRIPPR_PFLIP1_MASK) 880 881 #define FLEXCAN_ERRIPPR_PFLIP2_MASK (0x1F0000U) 882 #define FLEXCAN_ERRIPPR_PFLIP2_SHIFT (16U) 883 #define FLEXCAN_ERRIPPR_PFLIP2_WIDTH (5U) 884 #define FLEXCAN_ERRIPPR_PFLIP2(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERRIPPR_PFLIP2_SHIFT)) & FLEXCAN_ERRIPPR_PFLIP2_MASK) 885 886 #define FLEXCAN_ERRIPPR_PFLIP3_MASK (0x1F000000U) 887 #define FLEXCAN_ERRIPPR_PFLIP3_SHIFT (24U) 888 #define FLEXCAN_ERRIPPR_PFLIP3_WIDTH (5U) 889 #define FLEXCAN_ERRIPPR_PFLIP3(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERRIPPR_PFLIP3_SHIFT)) & FLEXCAN_ERRIPPR_PFLIP3_MASK) 890 /*! @} */ 891 892 /*! @name RERRAR - Error Report Address Register */ 893 /*! @{ */ 894 895 #define FLEXCAN_RERRAR_ERRADDR_MASK (0x3FFFU) 896 #define FLEXCAN_RERRAR_ERRADDR_SHIFT (0U) 897 #define FLEXCAN_RERRAR_ERRADDR_WIDTH (14U) 898 #define FLEXCAN_RERRAR_ERRADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RERRAR_ERRADDR_SHIFT)) & FLEXCAN_RERRAR_ERRADDR_MASK) 899 900 #define FLEXCAN_RERRAR_SAID_MASK (0x70000U) 901 #define FLEXCAN_RERRAR_SAID_SHIFT (16U) 902 #define FLEXCAN_RERRAR_SAID_WIDTH (3U) 903 #define FLEXCAN_RERRAR_SAID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RERRAR_SAID_SHIFT)) & FLEXCAN_RERRAR_SAID_MASK) 904 905 #define FLEXCAN_RERRAR_NCE_MASK (0x1000000U) 906 #define FLEXCAN_RERRAR_NCE_SHIFT (24U) 907 #define FLEXCAN_RERRAR_NCE_WIDTH (1U) 908 #define FLEXCAN_RERRAR_NCE(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RERRAR_NCE_SHIFT)) & FLEXCAN_RERRAR_NCE_MASK) 909 /*! @} */ 910 911 /*! @name RERRDR - Error Report Data Register */ 912 /*! @{ */ 913 914 #define FLEXCAN_RERRDR_RDATA_MASK (0xFFFFFFFFU) 915 #define FLEXCAN_RERRDR_RDATA_SHIFT (0U) 916 #define FLEXCAN_RERRDR_RDATA_WIDTH (32U) 917 #define FLEXCAN_RERRDR_RDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RERRDR_RDATA_SHIFT)) & FLEXCAN_RERRDR_RDATA_MASK) 918 /*! @} */ 919 920 /*! @name RERRSYNR - Error Report Syndrome Register */ 921 /*! @{ */ 922 923 #define FLEXCAN_RERRSYNR_SYND0_MASK (0x1FU) 924 #define FLEXCAN_RERRSYNR_SYND0_SHIFT (0U) 925 #define FLEXCAN_RERRSYNR_SYND0_WIDTH (5U) 926 #define FLEXCAN_RERRSYNR_SYND0(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RERRSYNR_SYND0_SHIFT)) & FLEXCAN_RERRSYNR_SYND0_MASK) 927 928 #define FLEXCAN_RERRSYNR_BE0_MASK (0x80U) 929 #define FLEXCAN_RERRSYNR_BE0_SHIFT (7U) 930 #define FLEXCAN_RERRSYNR_BE0_WIDTH (1U) 931 #define FLEXCAN_RERRSYNR_BE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RERRSYNR_BE0_SHIFT)) & FLEXCAN_RERRSYNR_BE0_MASK) 932 933 #define FLEXCAN_RERRSYNR_SYND1_MASK (0x1F00U) 934 #define FLEXCAN_RERRSYNR_SYND1_SHIFT (8U) 935 #define FLEXCAN_RERRSYNR_SYND1_WIDTH (5U) 936 #define FLEXCAN_RERRSYNR_SYND1(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RERRSYNR_SYND1_SHIFT)) & FLEXCAN_RERRSYNR_SYND1_MASK) 937 938 #define FLEXCAN_RERRSYNR_BE1_MASK (0x8000U) 939 #define FLEXCAN_RERRSYNR_BE1_SHIFT (15U) 940 #define FLEXCAN_RERRSYNR_BE1_WIDTH (1U) 941 #define FLEXCAN_RERRSYNR_BE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RERRSYNR_BE1_SHIFT)) & FLEXCAN_RERRSYNR_BE1_MASK) 942 943 #define FLEXCAN_RERRSYNR_SYND2_MASK (0x1F0000U) 944 #define FLEXCAN_RERRSYNR_SYND2_SHIFT (16U) 945 #define FLEXCAN_RERRSYNR_SYND2_WIDTH (5U) 946 #define FLEXCAN_RERRSYNR_SYND2(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RERRSYNR_SYND2_SHIFT)) & FLEXCAN_RERRSYNR_SYND2_MASK) 947 948 #define FLEXCAN_RERRSYNR_BE2_MASK (0x800000U) 949 #define FLEXCAN_RERRSYNR_BE2_SHIFT (23U) 950 #define FLEXCAN_RERRSYNR_BE2_WIDTH (1U) 951 #define FLEXCAN_RERRSYNR_BE2(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RERRSYNR_BE2_SHIFT)) & FLEXCAN_RERRSYNR_BE2_MASK) 952 953 #define FLEXCAN_RERRSYNR_SYND3_MASK (0x1F000000U) 954 #define FLEXCAN_RERRSYNR_SYND3_SHIFT (24U) 955 #define FLEXCAN_RERRSYNR_SYND3_WIDTH (5U) 956 #define FLEXCAN_RERRSYNR_SYND3(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RERRSYNR_SYND3_SHIFT)) & FLEXCAN_RERRSYNR_SYND3_MASK) 957 958 #define FLEXCAN_RERRSYNR_BE3_MASK (0x80000000U) 959 #define FLEXCAN_RERRSYNR_BE3_SHIFT (31U) 960 #define FLEXCAN_RERRSYNR_BE3_WIDTH (1U) 961 #define FLEXCAN_RERRSYNR_BE3(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RERRSYNR_BE3_SHIFT)) & FLEXCAN_RERRSYNR_BE3_MASK) 962 /*! @} */ 963 964 /*! @name ERRSR - Error Status Register */ 965 /*! @{ */ 966 967 #define FLEXCAN_ERRSR_CEIOF_MASK (0x1U) 968 #define FLEXCAN_ERRSR_CEIOF_SHIFT (0U) 969 #define FLEXCAN_ERRSR_CEIOF_WIDTH (1U) 970 #define FLEXCAN_ERRSR_CEIOF(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERRSR_CEIOF_SHIFT)) & FLEXCAN_ERRSR_CEIOF_MASK) 971 972 #define FLEXCAN_ERRSR_FANCEIOF_MASK (0x4U) 973 #define FLEXCAN_ERRSR_FANCEIOF_SHIFT (2U) 974 #define FLEXCAN_ERRSR_FANCEIOF_WIDTH (1U) 975 #define FLEXCAN_ERRSR_FANCEIOF(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERRSR_FANCEIOF_SHIFT)) & FLEXCAN_ERRSR_FANCEIOF_MASK) 976 977 #define FLEXCAN_ERRSR_HANCEIOF_MASK (0x8U) 978 #define FLEXCAN_ERRSR_HANCEIOF_SHIFT (3U) 979 #define FLEXCAN_ERRSR_HANCEIOF_WIDTH (1U) 980 #define FLEXCAN_ERRSR_HANCEIOF(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERRSR_HANCEIOF_SHIFT)) & FLEXCAN_ERRSR_HANCEIOF_MASK) 981 982 #define FLEXCAN_ERRSR_CEIF_MASK (0x10000U) 983 #define FLEXCAN_ERRSR_CEIF_SHIFT (16U) 984 #define FLEXCAN_ERRSR_CEIF_WIDTH (1U) 985 #define FLEXCAN_ERRSR_CEIF(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERRSR_CEIF_SHIFT)) & FLEXCAN_ERRSR_CEIF_MASK) 986 987 #define FLEXCAN_ERRSR_FANCEIF_MASK (0x40000U) 988 #define FLEXCAN_ERRSR_FANCEIF_SHIFT (18U) 989 #define FLEXCAN_ERRSR_FANCEIF_WIDTH (1U) 990 #define FLEXCAN_ERRSR_FANCEIF(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERRSR_FANCEIF_SHIFT)) & FLEXCAN_ERRSR_FANCEIF_MASK) 991 992 #define FLEXCAN_ERRSR_HANCEIF_MASK (0x80000U) 993 #define FLEXCAN_ERRSR_HANCEIF_SHIFT (19U) 994 #define FLEXCAN_ERRSR_HANCEIF_WIDTH (1U) 995 #define FLEXCAN_ERRSR_HANCEIF(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERRSR_HANCEIF_SHIFT)) & FLEXCAN_ERRSR_HANCEIF_MASK) 996 /*! @} */ 997 998 /*! @name EPRS - Enhanced CAN Bit Timing Prescalers */ 999 /*! @{ */ 1000 1001 #define FLEXCAN_EPRS_ENPRESDIV_MASK (0x3FFU) 1002 #define FLEXCAN_EPRS_ENPRESDIV_SHIFT (0U) 1003 #define FLEXCAN_EPRS_ENPRESDIV_WIDTH (10U) 1004 #define FLEXCAN_EPRS_ENPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_EPRS_ENPRESDIV_SHIFT)) & FLEXCAN_EPRS_ENPRESDIV_MASK) 1005 1006 #define FLEXCAN_EPRS_EDPRESDIV_MASK (0x3FF0000U) 1007 #define FLEXCAN_EPRS_EDPRESDIV_SHIFT (16U) 1008 #define FLEXCAN_EPRS_EDPRESDIV_WIDTH (10U) 1009 #define FLEXCAN_EPRS_EDPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_EPRS_EDPRESDIV_SHIFT)) & FLEXCAN_EPRS_EDPRESDIV_MASK) 1010 /*! @} */ 1011 1012 /*! @name ENCBT - Enhanced Nominal CAN Bit Timing */ 1013 /*! @{ */ 1014 1015 #define FLEXCAN_ENCBT_NTSEG1_MASK (0xFFU) 1016 #define FLEXCAN_ENCBT_NTSEG1_SHIFT (0U) 1017 #define FLEXCAN_ENCBT_NTSEG1_WIDTH (8U) 1018 #define FLEXCAN_ENCBT_NTSEG1(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ENCBT_NTSEG1_SHIFT)) & FLEXCAN_ENCBT_NTSEG1_MASK) 1019 1020 #define FLEXCAN_ENCBT_NTSEG2_MASK (0x7F000U) 1021 #define FLEXCAN_ENCBT_NTSEG2_SHIFT (12U) 1022 #define FLEXCAN_ENCBT_NTSEG2_WIDTH (7U) 1023 #define FLEXCAN_ENCBT_NTSEG2(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ENCBT_NTSEG2_SHIFT)) & FLEXCAN_ENCBT_NTSEG2_MASK) 1024 1025 #define FLEXCAN_ENCBT_NRJW_MASK (0x1FC00000U) 1026 #define FLEXCAN_ENCBT_NRJW_SHIFT (22U) 1027 #define FLEXCAN_ENCBT_NRJW_WIDTH (7U) 1028 #define FLEXCAN_ENCBT_NRJW(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ENCBT_NRJW_SHIFT)) & FLEXCAN_ENCBT_NRJW_MASK) 1029 /*! @} */ 1030 1031 /*! @name EDCBT - Enhanced Data Phase CAN bit Timing */ 1032 /*! @{ */ 1033 1034 #define FLEXCAN_EDCBT_DTSEG1_MASK (0x1FU) 1035 #define FLEXCAN_EDCBT_DTSEG1_SHIFT (0U) 1036 #define FLEXCAN_EDCBT_DTSEG1_WIDTH (5U) 1037 #define FLEXCAN_EDCBT_DTSEG1(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_EDCBT_DTSEG1_SHIFT)) & FLEXCAN_EDCBT_DTSEG1_MASK) 1038 1039 #define FLEXCAN_EDCBT_DTSEG2_MASK (0xF000U) 1040 #define FLEXCAN_EDCBT_DTSEG2_SHIFT (12U) 1041 #define FLEXCAN_EDCBT_DTSEG2_WIDTH (4U) 1042 #define FLEXCAN_EDCBT_DTSEG2(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_EDCBT_DTSEG2_SHIFT)) & FLEXCAN_EDCBT_DTSEG2_MASK) 1043 1044 #define FLEXCAN_EDCBT_DRJW_MASK (0x3C00000U) 1045 #define FLEXCAN_EDCBT_DRJW_SHIFT (22U) 1046 #define FLEXCAN_EDCBT_DRJW_WIDTH (4U) 1047 #define FLEXCAN_EDCBT_DRJW(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_EDCBT_DRJW_SHIFT)) & FLEXCAN_EDCBT_DRJW_MASK) 1048 /*! @} */ 1049 1050 /*! @name ETDC - Enhanced Transceiver Delay Compensation */ 1051 /*! @{ */ 1052 1053 #define FLEXCAN_ETDC_ETDCVAL_MASK (0xFFU) 1054 #define FLEXCAN_ETDC_ETDCVAL_SHIFT (0U) 1055 #define FLEXCAN_ETDC_ETDCVAL_WIDTH (8U) 1056 #define FLEXCAN_ETDC_ETDCVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ETDC_ETDCVAL_SHIFT)) & FLEXCAN_ETDC_ETDCVAL_MASK) 1057 1058 #define FLEXCAN_ETDC_ETDCFAIL_MASK (0x8000U) 1059 #define FLEXCAN_ETDC_ETDCFAIL_SHIFT (15U) 1060 #define FLEXCAN_ETDC_ETDCFAIL_WIDTH (1U) 1061 #define FLEXCAN_ETDC_ETDCFAIL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ETDC_ETDCFAIL_SHIFT)) & FLEXCAN_ETDC_ETDCFAIL_MASK) 1062 1063 #define FLEXCAN_ETDC_ETDCOFF_MASK (0x7F0000U) 1064 #define FLEXCAN_ETDC_ETDCOFF_SHIFT (16U) 1065 #define FLEXCAN_ETDC_ETDCOFF_WIDTH (7U) 1066 #define FLEXCAN_ETDC_ETDCOFF(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ETDC_ETDCOFF_SHIFT)) & FLEXCAN_ETDC_ETDCOFF_MASK) 1067 1068 #define FLEXCAN_ETDC_TDMDIS_MASK (0x40000000U) 1069 #define FLEXCAN_ETDC_TDMDIS_SHIFT (30U) 1070 #define FLEXCAN_ETDC_TDMDIS_WIDTH (1U) 1071 #define FLEXCAN_ETDC_TDMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ETDC_TDMDIS_SHIFT)) & FLEXCAN_ETDC_TDMDIS_MASK) 1072 1073 #define FLEXCAN_ETDC_ETDCEN_MASK (0x80000000U) 1074 #define FLEXCAN_ETDC_ETDCEN_SHIFT (31U) 1075 #define FLEXCAN_ETDC_ETDCEN_WIDTH (1U) 1076 #define FLEXCAN_ETDC_ETDCEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ETDC_ETDCEN_SHIFT)) & FLEXCAN_ETDC_ETDCEN_MASK) 1077 /*! @} */ 1078 1079 /*! @name FDCTRL - CAN FD Control Register */ 1080 /*! @{ */ 1081 1082 #define FLEXCAN_FDCTRL_TDCVAL_MASK (0x3FU) 1083 #define FLEXCAN_FDCTRL_TDCVAL_SHIFT (0U) 1084 #define FLEXCAN_FDCTRL_TDCVAL_WIDTH (6U) 1085 #define FLEXCAN_FDCTRL_TDCVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_FDCTRL_TDCVAL_SHIFT)) & FLEXCAN_FDCTRL_TDCVAL_MASK) 1086 1087 #define FLEXCAN_FDCTRL_TDCOFF_MASK (0x1F00U) 1088 #define FLEXCAN_FDCTRL_TDCOFF_SHIFT (8U) 1089 #define FLEXCAN_FDCTRL_TDCOFF_WIDTH (5U) 1090 #define FLEXCAN_FDCTRL_TDCOFF(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_FDCTRL_TDCOFF_SHIFT)) & FLEXCAN_FDCTRL_TDCOFF_MASK) 1091 1092 #define FLEXCAN_FDCTRL_TDCFAIL_MASK (0x4000U) 1093 #define FLEXCAN_FDCTRL_TDCFAIL_SHIFT (14U) 1094 #define FLEXCAN_FDCTRL_TDCFAIL_WIDTH (1U) 1095 #define FLEXCAN_FDCTRL_TDCFAIL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_FDCTRL_TDCFAIL_SHIFT)) & FLEXCAN_FDCTRL_TDCFAIL_MASK) 1096 1097 #define FLEXCAN_FDCTRL_TDCEN_MASK (0x8000U) 1098 #define FLEXCAN_FDCTRL_TDCEN_SHIFT (15U) 1099 #define FLEXCAN_FDCTRL_TDCEN_WIDTH (1U) 1100 #define FLEXCAN_FDCTRL_TDCEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_FDCTRL_TDCEN_SHIFT)) & FLEXCAN_FDCTRL_TDCEN_MASK) 1101 1102 #define FLEXCAN_FDCTRL_MBDSR0_MASK (0x30000U) 1103 #define FLEXCAN_FDCTRL_MBDSR0_SHIFT (16U) 1104 #define FLEXCAN_FDCTRL_MBDSR0_WIDTH (2U) 1105 #define FLEXCAN_FDCTRL_MBDSR0(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_FDCTRL_MBDSR0_SHIFT)) & FLEXCAN_FDCTRL_MBDSR0_MASK) 1106 1107 #define FLEXCAN_FDCTRL_MBDSR1_MASK (0x180000U) 1108 #define FLEXCAN_FDCTRL_MBDSR1_SHIFT (19U) 1109 #define FLEXCAN_FDCTRL_MBDSR1_WIDTH (2U) 1110 #define FLEXCAN_FDCTRL_MBDSR1(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_FDCTRL_MBDSR1_SHIFT)) & FLEXCAN_FDCTRL_MBDSR1_MASK) 1111 1112 #define FLEXCAN_FDCTRL_MBDSR2_MASK (0xC00000U) 1113 #define FLEXCAN_FDCTRL_MBDSR2_SHIFT (22U) 1114 #define FLEXCAN_FDCTRL_MBDSR2_WIDTH (2U) 1115 #define FLEXCAN_FDCTRL_MBDSR2(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_FDCTRL_MBDSR2_SHIFT)) & FLEXCAN_FDCTRL_MBDSR2_MASK) 1116 1117 #define FLEXCAN_FDCTRL_FDRATE_MASK (0x80000000U) 1118 #define FLEXCAN_FDCTRL_FDRATE_SHIFT (31U) 1119 #define FLEXCAN_FDCTRL_FDRATE_WIDTH (1U) 1120 #define FLEXCAN_FDCTRL_FDRATE(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_FDCTRL_FDRATE_SHIFT)) & FLEXCAN_FDCTRL_FDRATE_MASK) 1121 /*! @} */ 1122 1123 /*! @name FDCBT - CAN FD Bit Timing Register */ 1124 /*! @{ */ 1125 1126 #define FLEXCAN_FDCBT_FPSEG2_MASK (0x7U) 1127 #define FLEXCAN_FDCBT_FPSEG2_SHIFT (0U) 1128 #define FLEXCAN_FDCBT_FPSEG2_WIDTH (3U) 1129 #define FLEXCAN_FDCBT_FPSEG2(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_FDCBT_FPSEG2_SHIFT)) & FLEXCAN_FDCBT_FPSEG2_MASK) 1130 1131 #define FLEXCAN_FDCBT_FPSEG1_MASK (0xE0U) 1132 #define FLEXCAN_FDCBT_FPSEG1_SHIFT (5U) 1133 #define FLEXCAN_FDCBT_FPSEG1_WIDTH (3U) 1134 #define FLEXCAN_FDCBT_FPSEG1(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_FDCBT_FPSEG1_SHIFT)) & FLEXCAN_FDCBT_FPSEG1_MASK) 1135 1136 #define FLEXCAN_FDCBT_FPROPSEG_MASK (0x7C00U) 1137 #define FLEXCAN_FDCBT_FPROPSEG_SHIFT (10U) 1138 #define FLEXCAN_FDCBT_FPROPSEG_WIDTH (5U) 1139 #define FLEXCAN_FDCBT_FPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_FDCBT_FPROPSEG_SHIFT)) & FLEXCAN_FDCBT_FPROPSEG_MASK) 1140 1141 #define FLEXCAN_FDCBT_FRJW_MASK (0x70000U) 1142 #define FLEXCAN_FDCBT_FRJW_SHIFT (16U) 1143 #define FLEXCAN_FDCBT_FRJW_WIDTH (3U) 1144 #define FLEXCAN_FDCBT_FRJW(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_FDCBT_FRJW_SHIFT)) & FLEXCAN_FDCBT_FRJW_MASK) 1145 1146 #define FLEXCAN_FDCBT_FPRESDIV_MASK (0x3FF00000U) 1147 #define FLEXCAN_FDCBT_FPRESDIV_SHIFT (20U) 1148 #define FLEXCAN_FDCBT_FPRESDIV_WIDTH (10U) 1149 #define FLEXCAN_FDCBT_FPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_FDCBT_FPRESDIV_SHIFT)) & FLEXCAN_FDCBT_FPRESDIV_MASK) 1150 /*! @} */ 1151 1152 /*! @name FDCRC - CAN FD CRC Register */ 1153 /*! @{ */ 1154 1155 #define FLEXCAN_FDCRC_FD_TXCRC_MASK (0x1FFFFFU) 1156 #define FLEXCAN_FDCRC_FD_TXCRC_SHIFT (0U) 1157 #define FLEXCAN_FDCRC_FD_TXCRC_WIDTH (21U) 1158 #define FLEXCAN_FDCRC_FD_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_FDCRC_FD_TXCRC_SHIFT)) & FLEXCAN_FDCRC_FD_TXCRC_MASK) 1159 1160 #define FLEXCAN_FDCRC_FD_MBCRC_MASK (0x7F000000U) 1161 #define FLEXCAN_FDCRC_FD_MBCRC_SHIFT (24U) 1162 #define FLEXCAN_FDCRC_FD_MBCRC_WIDTH (7U) 1163 #define FLEXCAN_FDCRC_FD_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_FDCRC_FD_MBCRC_SHIFT)) & FLEXCAN_FDCRC_FD_MBCRC_MASK) 1164 /*! @} */ 1165 1166 /*! @name ERFCR - Enhanced Rx FIFO Control Register */ 1167 /*! @{ */ 1168 1169 #define FLEXCAN_ERFCR_ERFWM_MASK (0x1FU) 1170 #define FLEXCAN_ERFCR_ERFWM_SHIFT (0U) 1171 #define FLEXCAN_ERFCR_ERFWM_WIDTH (5U) 1172 #define FLEXCAN_ERFCR_ERFWM(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERFCR_ERFWM_SHIFT)) & FLEXCAN_ERFCR_ERFWM_MASK) 1173 1174 #define FLEXCAN_ERFCR_NFE_MASK (0x3F00U) 1175 #define FLEXCAN_ERFCR_NFE_SHIFT (8U) 1176 #define FLEXCAN_ERFCR_NFE_WIDTH (6U) 1177 #define FLEXCAN_ERFCR_NFE(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERFCR_NFE_SHIFT)) & FLEXCAN_ERFCR_NFE_MASK) 1178 1179 #define FLEXCAN_ERFCR_NEXIF_MASK (0x7F0000U) 1180 #define FLEXCAN_ERFCR_NEXIF_SHIFT (16U) 1181 #define FLEXCAN_ERFCR_NEXIF_WIDTH (7U) 1182 #define FLEXCAN_ERFCR_NEXIF(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERFCR_NEXIF_SHIFT)) & FLEXCAN_ERFCR_NEXIF_MASK) 1183 1184 #define FLEXCAN_ERFCR_DMALW_MASK (0x7C000000U) 1185 #define FLEXCAN_ERFCR_DMALW_SHIFT (26U) 1186 #define FLEXCAN_ERFCR_DMALW_WIDTH (5U) 1187 #define FLEXCAN_ERFCR_DMALW(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERFCR_DMALW_SHIFT)) & FLEXCAN_ERFCR_DMALW_MASK) 1188 1189 #define FLEXCAN_ERFCR_ERFEN_MASK (0x80000000U) 1190 #define FLEXCAN_ERFCR_ERFEN_SHIFT (31U) 1191 #define FLEXCAN_ERFCR_ERFEN_WIDTH (1U) 1192 #define FLEXCAN_ERFCR_ERFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERFCR_ERFEN_SHIFT)) & FLEXCAN_ERFCR_ERFEN_MASK) 1193 /*! @} */ 1194 1195 /*! @name ERFIER - Enhanced Rx FIFO Interrupt Enable Register */ 1196 /*! @{ */ 1197 1198 #define FLEXCAN_ERFIER_ERFDAIE_MASK (0x10000000U) 1199 #define FLEXCAN_ERFIER_ERFDAIE_SHIFT (28U) 1200 #define FLEXCAN_ERFIER_ERFDAIE_WIDTH (1U) 1201 #define FLEXCAN_ERFIER_ERFDAIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERFIER_ERFDAIE_SHIFT)) & FLEXCAN_ERFIER_ERFDAIE_MASK) 1202 1203 #define FLEXCAN_ERFIER_ERFWMIIE_MASK (0x20000000U) 1204 #define FLEXCAN_ERFIER_ERFWMIIE_SHIFT (29U) 1205 #define FLEXCAN_ERFIER_ERFWMIIE_WIDTH (1U) 1206 #define FLEXCAN_ERFIER_ERFWMIIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERFIER_ERFWMIIE_SHIFT)) & FLEXCAN_ERFIER_ERFWMIIE_MASK) 1207 1208 #define FLEXCAN_ERFIER_ERFOVFIE_MASK (0x40000000U) 1209 #define FLEXCAN_ERFIER_ERFOVFIE_SHIFT (30U) 1210 #define FLEXCAN_ERFIER_ERFOVFIE_WIDTH (1U) 1211 #define FLEXCAN_ERFIER_ERFOVFIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERFIER_ERFOVFIE_SHIFT)) & FLEXCAN_ERFIER_ERFOVFIE_MASK) 1212 1213 #define FLEXCAN_ERFIER_ERFUFWIE_MASK (0x80000000U) 1214 #define FLEXCAN_ERFIER_ERFUFWIE_SHIFT (31U) 1215 #define FLEXCAN_ERFIER_ERFUFWIE_WIDTH (1U) 1216 #define FLEXCAN_ERFIER_ERFUFWIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERFIER_ERFUFWIE_SHIFT)) & FLEXCAN_ERFIER_ERFUFWIE_MASK) 1217 /*! @} */ 1218 1219 /*! @name ERFSR - Enhanced Rx FIFO Status Register */ 1220 /*! @{ */ 1221 1222 #define FLEXCAN_ERFSR_ERFEL_MASK (0x3FU) 1223 #define FLEXCAN_ERFSR_ERFEL_SHIFT (0U) 1224 #define FLEXCAN_ERFSR_ERFEL_WIDTH (6U) 1225 #define FLEXCAN_ERFSR_ERFEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERFSR_ERFEL_SHIFT)) & FLEXCAN_ERFSR_ERFEL_MASK) 1226 1227 #define FLEXCAN_ERFSR_ERFF_MASK (0x10000U) 1228 #define FLEXCAN_ERFSR_ERFF_SHIFT (16U) 1229 #define FLEXCAN_ERFSR_ERFF_WIDTH (1U) 1230 #define FLEXCAN_ERFSR_ERFF(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERFSR_ERFF_SHIFT)) & FLEXCAN_ERFSR_ERFF_MASK) 1231 1232 #define FLEXCAN_ERFSR_ERFE_MASK (0x20000U) 1233 #define FLEXCAN_ERFSR_ERFE_SHIFT (17U) 1234 #define FLEXCAN_ERFSR_ERFE_WIDTH (1U) 1235 #define FLEXCAN_ERFSR_ERFE(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERFSR_ERFE_SHIFT)) & FLEXCAN_ERFSR_ERFE_MASK) 1236 1237 #define FLEXCAN_ERFSR_ERFCLR_MASK (0x8000000U) 1238 #define FLEXCAN_ERFSR_ERFCLR_SHIFT (27U) 1239 #define FLEXCAN_ERFSR_ERFCLR_WIDTH (1U) 1240 #define FLEXCAN_ERFSR_ERFCLR(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERFSR_ERFCLR_SHIFT)) & FLEXCAN_ERFSR_ERFCLR_MASK) 1241 1242 #define FLEXCAN_ERFSR_ERFDA_MASK (0x10000000U) 1243 #define FLEXCAN_ERFSR_ERFDA_SHIFT (28U) 1244 #define FLEXCAN_ERFSR_ERFDA_WIDTH (1U) 1245 #define FLEXCAN_ERFSR_ERFDA(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERFSR_ERFDA_SHIFT)) & FLEXCAN_ERFSR_ERFDA_MASK) 1246 1247 #define FLEXCAN_ERFSR_ERFWMI_MASK (0x20000000U) 1248 #define FLEXCAN_ERFSR_ERFWMI_SHIFT (29U) 1249 #define FLEXCAN_ERFSR_ERFWMI_WIDTH (1U) 1250 #define FLEXCAN_ERFSR_ERFWMI(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERFSR_ERFWMI_SHIFT)) & FLEXCAN_ERFSR_ERFWMI_MASK) 1251 1252 #define FLEXCAN_ERFSR_ERFOVF_MASK (0x40000000U) 1253 #define FLEXCAN_ERFSR_ERFOVF_SHIFT (30U) 1254 #define FLEXCAN_ERFSR_ERFOVF_WIDTH (1U) 1255 #define FLEXCAN_ERFSR_ERFOVF(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERFSR_ERFOVF_SHIFT)) & FLEXCAN_ERFSR_ERFOVF_MASK) 1256 1257 #define FLEXCAN_ERFSR_ERFUFW_MASK (0x80000000U) 1258 #define FLEXCAN_ERFSR_ERFUFW_SHIFT (31U) 1259 #define FLEXCAN_ERFSR_ERFUFW_WIDTH (1U) 1260 #define FLEXCAN_ERFSR_ERFUFW(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERFSR_ERFUFW_SHIFT)) & FLEXCAN_ERFSR_ERFUFW_MASK) 1261 /*! @} */ 1262 1263 /*! @name HR_TIME_STAMP - High Resolution Time Stamp */ 1264 /*! @{ */ 1265 1266 #define FLEXCAN_HR_TIME_STAMP_TS_MASK (0xFFFFFFFFU) 1267 #define FLEXCAN_HR_TIME_STAMP_TS_SHIFT (0U) 1268 #define FLEXCAN_HR_TIME_STAMP_TS_WIDTH (32U) 1269 #define FLEXCAN_HR_TIME_STAMP_TS(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_HR_TIME_STAMP_TS_SHIFT)) & FLEXCAN_HR_TIME_STAMP_TS_MASK) 1270 /*! @} */ 1271 1272 /*! @name ERFFEL - Enhanced Rx FIFO Filter Element */ 1273 /*! @{ */ 1274 1275 #define FLEXCAN_ERFFEL_FEL_MASK (0xFFFFFFFFU) 1276 #define FLEXCAN_ERFFEL_FEL_SHIFT (0U) 1277 #define FLEXCAN_ERFFEL_FEL_WIDTH (32U) 1278 #define FLEXCAN_ERFFEL_FEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERFFEL_FEL_SHIFT)) & FLEXCAN_ERFFEL_FEL_MASK) 1279 /*! @} */ 1280 1281 /*! 1282 * @} 1283 */ /* end of group FLEXCAN_Register_Masks */ 1284 1285 /*! 1286 * @} 1287 */ /* end of group FLEXCAN_Peripheral_Access_Layer */ 1288 1289 #endif /* #if !defined(S32K344_FLEXCAN_H_) */ 1290
