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Searched refs:EPDC_IRQ_WB_CMPLT_IRQ_MASK (Results 1 – 8 of 8) sorted by relevance

/hal_nxp-3.7.0/imx/devices/MCIMX7D/
DMCIMX7D_M4.h16034 #define EPDC_IRQ_WB_CMPLT_IRQ_MASK 0x10000u macro
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8UD3/
DMIMX8UD3_cm33.h15625 #define EPDC_IRQ_WB_CMPLT_IRQ_MASK (0x10000U) macro
15627 … (((uint32_t)(((uint32_t)(x)) << EPDC_IRQ_WB_CMPLT_IRQ_SHIFT)) & EPDC_IRQ_WB_CMPLT_IRQ_MASK)
DMIMX8UD3_dsp0.h15030 #define EPDC_IRQ_WB_CMPLT_IRQ_MASK (0x10000U) macro
15032 … (((uint32_t)(((uint32_t)(x)) << EPDC_IRQ_WB_CMPLT_IRQ_SHIFT)) & EPDC_IRQ_WB_CMPLT_IRQ_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8UD7/
DMIMX8UD7_cm33.h15625 #define EPDC_IRQ_WB_CMPLT_IRQ_MASK (0x10000U) macro
15627 … (((uint32_t)(((uint32_t)(x)) << EPDC_IRQ_WB_CMPLT_IRQ_SHIFT)) & EPDC_IRQ_WB_CMPLT_IRQ_MASK)
DMIMX8UD7_dsp1.h15027 #define EPDC_IRQ_WB_CMPLT_IRQ_MASK (0x10000U) macro
15029 … (((uint32_t)(((uint32_t)(x)) << EPDC_IRQ_WB_CMPLT_IRQ_SHIFT)) & EPDC_IRQ_WB_CMPLT_IRQ_MASK)
DMIMX8UD7_dsp0.h15030 #define EPDC_IRQ_WB_CMPLT_IRQ_MASK (0x10000U) macro
15032 … (((uint32_t)(((uint32_t)(x)) << EPDC_IRQ_WB_CMPLT_IRQ_SHIFT)) & EPDC_IRQ_WB_CMPLT_IRQ_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8US3/
DMIMX8US3_cm33.h15625 #define EPDC_IRQ_WB_CMPLT_IRQ_MASK (0x10000U) macro
15627 … (((uint32_t)(((uint32_t)(x)) << EPDC_IRQ_WB_CMPLT_IRQ_SHIFT)) & EPDC_IRQ_WB_CMPLT_IRQ_MASK)
DMIMX8US3_dsp0.h15030 #define EPDC_IRQ_WB_CMPLT_IRQ_MASK (0x10000U) macro
15032 … (((uint32_t)(((uint32_t)(x)) << EPDC_IRQ_WB_CMPLT_IRQ_SHIFT)) & EPDC_IRQ_WB_CMPLT_IRQ_MASK)