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Searched refs:EPDC_CTRL_CLKGATE_MASK (Results 1 – 9 of 9) sorted by relevance

/hal_nxp-3.7.0/mcux/mcux-sdk/drivers/epdc/
Dfsl_epdc.c87 while ((base->CTRL.RW & EPDC_CTRL_CLKGATE_MASK) == 0U) in EPDC_ResetToInit()
91 base->CTRL.CLR = (EPDC_CTRL_SFTRST_MASK | EPDC_CTRL_CLKGATE_MASK); in EPDC_ResetToInit()
93 while ((base->CTRL.RW & (EPDC_CTRL_CLKGATE_MASK | EPDC_CTRL_SFTRST_MASK)) != 0U) in EPDC_ResetToInit()
/hal_nxp-3.7.0/imx/devices/MCIMX7D/
DMCIMX7D_M4.h14904 #define EPDC_CTRL_CLKGATE_MASK 0x40000000u macro
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8UD3/
DMIMX8UD3_cm33.h14843 #define EPDC_CTRL_CLKGATE_MASK (0x40000000U) macro
14845 … (((uint32_t)(((uint32_t)(x)) << EPDC_CTRL_CLKGATE_SHIFT)) & EPDC_CTRL_CLKGATE_MASK)
DMIMX8UD3_dsp0.h14248 #define EPDC_CTRL_CLKGATE_MASK (0x40000000U) macro
14250 … (((uint32_t)(((uint32_t)(x)) << EPDC_CTRL_CLKGATE_SHIFT)) & EPDC_CTRL_CLKGATE_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8UD7/
DMIMX8UD7_cm33.h14843 #define EPDC_CTRL_CLKGATE_MASK (0x40000000U) macro
14845 … (((uint32_t)(((uint32_t)(x)) << EPDC_CTRL_CLKGATE_SHIFT)) & EPDC_CTRL_CLKGATE_MASK)
DMIMX8UD7_dsp1.h14245 #define EPDC_CTRL_CLKGATE_MASK (0x40000000U) macro
14247 … (((uint32_t)(((uint32_t)(x)) << EPDC_CTRL_CLKGATE_SHIFT)) & EPDC_CTRL_CLKGATE_MASK)
DMIMX8UD7_dsp0.h14248 #define EPDC_CTRL_CLKGATE_MASK (0x40000000U) macro
14250 … (((uint32_t)(((uint32_t)(x)) << EPDC_CTRL_CLKGATE_SHIFT)) & EPDC_CTRL_CLKGATE_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8US3/
DMIMX8US3_cm33.h14843 #define EPDC_CTRL_CLKGATE_MASK (0x40000000U) macro
14845 … (((uint32_t)(((uint32_t)(x)) << EPDC_CTRL_CLKGATE_SHIFT)) & EPDC_CTRL_CLKGATE_MASK)
DMIMX8US3_dsp0.h14248 #define EPDC_CTRL_CLKGATE_MASK (0x40000000U) macro
14250 … (((uint32_t)(((uint32_t)(x)) << EPDC_CTRL_CLKGATE_SHIFT)) & EPDC_CTRL_CLKGATE_MASK)