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Searched refs:DSPCPUCLKSELB (Results 1 – 19 of 19) sorted by relevance

/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT633S/drivers/
Dfsl_power.c859 dspclk_sel[1] = CLKCTL1->DSPCPUCLKSELB; in POWER_EnterDeepSleep()
924 CLKCTL1->DSPCPUCLKSELB = CLKCTL1_DSPCPUCLKSELB_SEL(0); in POWER_EnterDeepSleep()
1010 CLKCTL1->DSPCPUCLKSELB = dspclk_sel[1] & CLKCTL1_DSPCPUCLKSELB_SEL_MASK; in POWER_EnterDeepSleep()
Dfsl_clock.c375 switch ((CLKCTL1->DSPCPUCLKSELB) & CLKCTL1_DSPCPUCLKSELB_SEL_MASK) in CLOCK_GetDspMainClkFreq()
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT685S/drivers/
Dfsl_power.c859 dspclk_sel[1] = CLKCTL1->DSPCPUCLKSELB; in POWER_EnterDeepSleep()
924 CLKCTL1->DSPCPUCLKSELB = CLKCTL1_DSPCPUCLKSELB_SEL(0); in POWER_EnterDeepSleep()
1010 CLKCTL1->DSPCPUCLKSELB = dspclk_sel[1] & CLKCTL1_DSPCPUCLKSELB_SEL_MASK; in POWER_EnterDeepSleep()
Dfsl_clock.c375 switch ((CLKCTL1->DSPCPUCLKSELB) & CLKCTL1_DSPCPUCLKSELB_SEL_MASK) in CLOCK_GetDspMainClkFreq()
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT595S/
Dsystem_MIMXRT595S_dsp.c104 switch ((CLKCTL1->DSPCPUCLKSELB) & CLKCTL1_DSPCPUCLKSELB_SEL_MASK) in SystemCoreClockUpdate()
DMIMXRT595S_dsp.h4129 __IO uint32_t DSPCPUCLKSELB; /**< DSP CPU Clock Select B, offset: 0x434 */ member
DMIMXRT595S_cm33.h10386 __IO uint32_t DSPCPUCLKSELB; /**< DSP CPU Clock Select B, offset: 0x434 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT685S/
Dsystem_MIMXRT685S_dsp.c130 switch ((CLKCTL1->DSPCPUCLKSELB) & CLKCTL1_DSPCPUCLKSELB_SEL_MASK) in SystemCoreClockUpdate()
DMIMXRT685S_dsp.h2740 __IO uint32_t DSPCPUCLKSELB; /**< DSP clock selection B, offset: 0x434 */ member
DMIMXRT685S_cm33.h8470 __IO uint32_t DSPCPUCLKSELB; /**< DSP clock selection B, offset: 0x434 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT595S/drivers/
Dfsl_power.c899 dspclk_sel[1] = CLKCTL1->DSPCPUCLKSELB; in AT_QUICKACCESS_SECTION_CODE()
1018 CLKCTL1->DSPCPUCLKSELB = CLKCTL1_DSPCPUCLKSELB_SEL(0); in AT_QUICKACCESS_SECTION_CODE()
1108 CLKCTL1->DSPCPUCLKSELB = dspclk_sel[1] & CLKCTL1_DSPCPUCLKSELB_SEL_MASK; in AT_QUICKACCESS_SECTION_CODE()
Dfsl_clock.c381 switch ((CLKCTL1->DSPCPUCLKSELB) & CLKCTL1_DSPCPUCLKSELB_SEL_MASK) in CLOCK_GetDspMainClkFreq()
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT533S/drivers/
Dfsl_power.c899 dspclk_sel[1] = CLKCTL1->DSPCPUCLKSELB; in AT_QUICKACCESS_SECTION_CODE()
1018 CLKCTL1->DSPCPUCLKSELB = CLKCTL1_DSPCPUCLKSELB_SEL(0); in AT_QUICKACCESS_SECTION_CODE()
1108 CLKCTL1->DSPCPUCLKSELB = dspclk_sel[1] & CLKCTL1_DSPCPUCLKSELB_SEL_MASK; in AT_QUICKACCESS_SECTION_CODE()
Dfsl_clock.c381 switch ((CLKCTL1->DSPCPUCLKSELB) & CLKCTL1_DSPCPUCLKSELB_SEL_MASK) in CLOCK_GetDspMainClkFreq()
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT555S/drivers/
Dfsl_power.c899 dspclk_sel[1] = CLKCTL1->DSPCPUCLKSELB; in AT_QUICKACCESS_SECTION_CODE()
1018 CLKCTL1->DSPCPUCLKSELB = CLKCTL1_DSPCPUCLKSELB_SEL(0); in AT_QUICKACCESS_SECTION_CODE()
1108 CLKCTL1->DSPCPUCLKSELB = dspclk_sel[1] & CLKCTL1_DSPCPUCLKSELB_SEL_MASK; in AT_QUICKACCESS_SECTION_CODE()
Dfsl_clock.c381 switch ((CLKCTL1->DSPCPUCLKSELB) & CLKCTL1_DSPCPUCLKSELB_SEL_MASK) in CLOCK_GetDspMainClkFreq()
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h8470 __IO uint32_t DSPCPUCLKSELB; /**< DSP clock selection B, offset: 0x434 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h10382 __IO uint32_t DSPCPUCLKSELB; /**< DSP CPU Clock Select B, offset: 0x434 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h10385 __IO uint32_t DSPCPUCLKSELB; /**< DSP CPU Clock Select B, offset: 0x434 */ member