1 /*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016-2020 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #ifndef FSL_DMIC_H_
10 #define FSL_DMIC_H_
11
12 #include "fsl_common.h"
13
14 /*!
15 * @addtogroup dmic_driver
16 * @{
17 */
18
19 /*! @file*/
20
21 /*******************************************************************************
22 * Definitions
23 ******************************************************************************/
24
25 /*!
26 * @name DMIC version
27 * @{
28 */
29
30 /*! @brief DMIC driver version 2.3.2. */
31 #define FSL_DMIC_DRIVER_VERSION (MAKE_VERSION(2, 3, 2))
32 /*! @} */
33
34 /*! @brief _dmic_status DMIC transfer status.*/
35 enum
36 {
37 kStatus_DMIC_Busy = MAKE_STATUS(kStatusGroup_DMIC, 0), /*!< DMIC is busy */
38 kStatus_DMIC_Idle = MAKE_STATUS(kStatusGroup_DMIC, 1), /*!< DMIC is idle */
39 kStatus_DMIC_OverRunError = MAKE_STATUS(kStatusGroup_DMIC, 2), /*!< DMIC over run Error */
40 kStatus_DMIC_UnderRunError = MAKE_STATUS(kStatusGroup_DMIC, 3), /*!< DMIC under run Error */
41 };
42
43 /*! @brief DMIC different operation modes. */
44 typedef enum _operation_mode
45 {
46 kDMIC_OperationModeInterrupt = 1U, /*!< Interrupt mode */
47 kDMIC_OperationModeDma = 2U, /*!< DMA mode */
48 } operation_mode_t;
49
50 /*! @brief DMIC left/right values. */
51 typedef enum _stereo_side
52 {
53 kDMIC_Left = 0U, /*!< Left Stereo channel */
54 kDMIC_Right = 1U, /*!< Right Stereo channel */
55 } stereo_side_t;
56
57 /*! @brief DMIC Clock pre-divider values. */
58 typedef enum
59 {
60 kDMIC_PdmDiv1 = 0U, /*!< DMIC pre-divider set in divide by 1 */
61 kDMIC_PdmDiv2 = 1U, /*!< DMIC pre-divider set in divide by 2 */
62 kDMIC_PdmDiv3 = 2U, /*!< DMIC pre-divider set in divide by 3 */
63 kDMIC_PdmDiv4 = 3U, /*!< DMIC pre-divider set in divide by 4 */
64 kDMIC_PdmDiv6 = 4U, /*!< DMIC pre-divider set in divide by 6 */
65 kDMIC_PdmDiv8 = 5U, /*!< DMIC pre-divider set in divide by 8 */
66 kDMIC_PdmDiv12 = 6U, /*!< DMIC pre-divider set in divide by 12 */
67 kDMIC_PdmDiv16 = 7U, /*!< DMIC pre-divider set in divide by 16*/
68 kDMIC_PdmDiv24 = 8U, /*!< DMIC pre-divider set in divide by 24*/
69 kDMIC_PdmDiv32 = 9U, /*!< DMIC pre-divider set in divide by 32 */
70 kDMIC_PdmDiv48 = 10U, /*!< DMIC pre-divider set in divide by 48 */
71 kDMIC_PdmDiv64 = 11U, /*!< DMIC pre-divider set in divide by 64*/
72 kDMIC_PdmDiv96 = 12U, /*!< DMIC pre-divider set in divide by 96*/
73 kDMIC_PdmDiv128 = 13U, /*!< DMIC pre-divider set in divide by 128 */
74 } pdm_div_t;
75
76 /*! @brief Pre-emphasis Filter coefficient value for 2FS and 4FS modes. */
77 typedef enum _compensation
78 {
79 kDMIC_CompValueZero = 0U, /*!< Compensation 0 */
80 kDMIC_CompValueNegativePoint16 = 1U, /*!< Compensation -0.16 */
81 kDMIC_CompValueNegativePoint15 = 2U, /*!< Compensation -0.15 */
82 kDMIC_CompValueNegativePoint13 = 3U, /*!< Compensation -0.13 */
83 } compensation_t;
84
85 /*! @brief DMIC DC filter control values. */
86 typedef enum _dc_removal
87 {
88 kDMIC_DcNoRemove = 0U, /*!< Flat response no filter */
89 kDMIC_DcCut155 = 1U, /*!< Cut off Frequency is 155 Hz */
90 kDMIC_DcCut78 = 2U, /*!< Cut off Frequency is 78 Hz */
91 kDMIC_DcCut39 = 3U, /*!< Cut off Frequency is 39 Hz */
92 } dc_removal_t;
93
94 #if !(defined(FSL_FEATURE_DMIC_HAS_NO_IOCFG) && FSL_FEATURE_DMIC_HAS_NO_IOCFG)
95 /*! @brief DMIC IO configiration. */
96 typedef enum _dmic_io
97 {
98 kDMIC_PdmDual = 0, /*!< Two separate pairs of PDM wires */
99 kDMIC_PdmStereo = 4, /*!< Stereo data0 */
100
101 #if !(defined(FSL_FEATURE_DMIC_IO_HAS_NO_BYPASS) && (FSL_FEATURE_DMIC_IO_HAS_NO_BYPASS))
102 kDMIC_PdmBypass = 3, /*!< Clk Bypass clocks both channels */
103 kDMIC_PdmBypassClk0 = 1, /*!< Clk Bypass clocks only channel0 */
104 kDMIC_PdmBypassClk1 = 2, /*!< Clk Bypas clocks only channel1 */
105 #endif
106
107 #if defined(FSL_FEATURE_DMIC_IO_HAS_STEREO_2_4_6) && (FSL_FEATURE_DMIC_IO_HAS_STEREO_2_4_6)
108 kDMIC_PdmStereo2 = 8, /*!< Stereo data2 */
109 kDMIC_PdmStereo4 = 16, /*!< Stereo data4 */
110 kDMIC_PdmStereo6 = 32, /*!< Stereo data6 */
111 #endif
112 } dmic_io_t;
113 #endif
114
115 /*! @brief DMIC Channel number. */
116 typedef enum _dmic_channel
117 {
118 kDMIC_Channel0 = 0U, /*!< DMIC channel 0 */
119 kDMIC_Channel1 = 1U, /*!< DMIC channel 1 */
120 #if defined(FSL_FEATURE_DMIC_CHANNEL_NUM) && (FSL_FEATURE_DMIC_CHANNEL_NUM > 2U)
121 kDMIC_Channel2 = 2U, /*!< DMIC channel 2 */
122 kDMIC_Channel3 = 3U, /*!< DMIC channel 3 */
123 #endif
124 #if defined(FSL_FEATURE_DMIC_CHANNEL_NUM) && (FSL_FEATURE_DMIC_CHANNEL_NUM > 4U)
125 kDMIC_Channel4 = 4U, /*!< DMIC channel 4 */
126 kDMIC_Channel5 = 5U, /*!< DMIC channel 5 */
127 kDMIC_Channel6 = 6U, /*!< DMIC channel 6 */
128 kDMIC_Channel7 = 7U, /*!< DMIC channel 7 */
129 #endif
130 } dmic_channel_t;
131
132 /*! @brief _dmic_channel_mask DMIC Channel mask. */
133 enum
134 {
135 kDMIC_EnableChannel0 = 1 << 0U, /*!< DMIC channel 0 mask */
136 kDMIC_EnableChannel1 = 1 << 1U, /*!< DMIC channel 1 mask */
137 #if defined(FSL_FEATURE_DMIC_CHANNEL_NUM) && (FSL_FEATURE_DMIC_CHANNEL_NUM > 2U)
138 kDMIC_EnableChannel2 = 1 << 2U, /*!< DMIC channel 2 mask */
139 kDMIC_EnableChannel3 = 1 << 3U, /*!< DMIC channel 3 mask */
140 #endif
141 #if defined(FSL_FEATURE_DMIC_CHANNEL_NUM) && (FSL_FEATURE_DMIC_CHANNEL_NUM > 4U)
142 kDMIC_EnableChannel4 = 1 << 4U, /*!< DMIC channel 4 mask */
143 kDMIC_EnableChannel5 = 1 << 5U, /*!< DMIC channel 5 mask */
144 kDMIC_EnableChannel6 = 1 << 6U, /*!< DMIC channel 6 mask */
145 kDMIC_EnableChannel7 = 1 << 7U, /*!< DMIC channel 7 mask */
146 #endif
147 };
148
149 /*! @brief DMIC and decimator sample rates. */
150 typedef enum _dmic_phy_sample_rate
151 {
152 kDMIC_PhyFullSpeed = 0U, /*!< Decimator gets one sample per each chosen clock edge of PDM interface */
153 kDMIC_PhyHalfSpeed = 1U, /*!< PDM clock to Microphone is halved, decimator receives each sample twice */
154 } dmic_phy_sample_rate_t;
155
156 /*! @brief DMIC Channel configuration structure. */
157 typedef struct _dmic_channel_config
158 {
159 pdm_div_t divhfclk; /*!< DMIC Clock pre-divider values */
160 uint32_t osr; /*!< oversampling rate(CIC decimation rate) for PCM */
161 int32_t gainshft; /*!< 4FS PCM data gain control */
162 compensation_t preac2coef; /*!< Pre-emphasis Filter coefficient value for 2FS */
163 compensation_t preac4coef; /*!< Pre-emphasis Filter coefficient value for 4FS */
164 dc_removal_t dc_cut_level; /*!< DMIC DC filter control values. */
165 uint32_t post_dc_gain_reduce; /*!< Fine gain adjustment in the form of a number of bits to downshift */
166 dmic_phy_sample_rate_t sample_rate; /*!< DMIC and decimator sample rates */
167 bool saturate16bit; /*!< Selects 16-bit saturation. 0 means results roll over if out range and do not saturate.
168 1 means if the result overflows, it saturates at 0xFFFF for positive overflow and
169 0x8000 for negative overflow.*/
170 #if defined(FSL_FEATURE_DMIC_CHANNEL_HAS_SIGNEXTEND) && (FSL_FEATURE_DMIC_CHANNEL_HAS_SIGNEXTEND)
171 bool enableSignExtend; /*!< sign extend feature which allows processing of 24bit audio data on 32bit machine */
172 #endif
173 } dmic_channel_config_t;
174
175 /*! @brief DMIC Callback function. */
176 typedef void (*dmic_callback_t)(void);
177
178 /*! @brief HWVAD Callback function. */
179 typedef void (*dmic_hwvad_callback_t)(void);
180
181 /*******************************************************************************
182 * API
183 ******************************************************************************/
184 #ifdef __cplusplus
185 extern "C" {
186 #endif
187
188 /*!
189 * @name Initialization and deinitialization
190 * @{
191 */
192
193 /*!
194 * @brief Get the DMIC instance from peripheral base address.
195 *
196 * @param base DMIC peripheral base address.
197 * @return DMIC instance.
198 */
199 uint32_t DMIC_GetInstance(DMIC_Type *base);
200
201 /*!
202 * @brief Turns DMIC Clock on
203 * @param base : DMIC base
204 * @return Nothing
205 */
206 void DMIC_Init(DMIC_Type *base);
207
208 /*!
209 * @brief Turns DMIC Clock off
210 * @param base : DMIC base
211 * @return Nothing
212 */
213 void DMIC_DeInit(DMIC_Type *base);
214
215 #if !(defined(FSL_FEATURE_DMIC_HAS_NO_IOCFG) && FSL_FEATURE_DMIC_HAS_NO_IOCFG)
216 /*!
217 * @brief Configure DMIC io
218 * @deprecated Do not use this function. It has been superceded by @ref DMIC_SetIOCFG
219 * @param base : The base address of DMIC interface
220 * @param config : DMIC io configuration
221 * @return Nothing
222 */
223 void DMIC_ConfigIO(DMIC_Type *base, dmic_io_t config);
224
225 /*!
226 * @brief Stereo PDM select.
227 * @param base : The base address of DMIC interface
228 * @param sel : Reference dmic_io_t, can be a single or combination value of dmic_io_t.
229 * @return Nothing
230 */
DMIC_SetIOCFG(DMIC_Type * base,uint32_t sel)231 static inline void DMIC_SetIOCFG(DMIC_Type *base, uint32_t sel)
232 {
233 base->IOCFG = sel;
234 }
235 #endif
236
237 /*!
238 * @brief Set DMIC operating mode
239 * @deprecated Do not use this function. It has been superceded by
240 * @ref DMIC_EnableChannelInterrupt, @ref DMIC_EnableChannelDma.
241 * @param base : The base address of DMIC interface
242 * @param mode : DMIC mode
243 * @return Nothing
244 */
245 void DMIC_SetOperationMode(DMIC_Type *base, operation_mode_t mode);
246
247 /*!
248 * @brief Configure Clock scaling
249 * @param base : The base address of DMIC interface
250 * @param use2fs : clock scaling
251 * @return Nothing
252 */
253 void DMIC_Use2fs(DMIC_Type *base, bool use2fs);
254
255 /*! @} */
256
257 /*!
258 * @name Channel configuration
259 * @{
260 */
261
262 /*!
263 * @brief Configure DMIC channel
264 * @param base : The base address of DMIC interface
265 * @param channel : DMIC channel
266 * @param dc_cut_level : dc_removal_t, Cut off Frequency
267 * @param post_dc_gain_reduce : Fine gain adjustment in the form of a number of bits to downshift.
268 * @param saturate16bit : If selects 16-bit saturation.
269 */
270 void DMIC_CfgChannelDc(DMIC_Type *base,
271 dmic_channel_t channel,
272 dc_removal_t dc_cut_level,
273 uint32_t post_dc_gain_reduce,
274 bool saturate16bit);
275
276 #if defined(FSL_FEATURE_DMIC_CHANNEL_HAS_SIGNEXTEND) && (FSL_FEATURE_DMIC_CHANNEL_HAS_SIGNEXTEND)
277 /*!
278 * @brief Enbale channel sign extend which allows processing of 24bit audio data on 32bit machines.
279 * @param base : The base address of DMIC interface
280 * @param channel : DMIC channel
281 * @param enable : true is enable sign extend, false is disable sign extend
282 */
DMIC_EnableChannelSignExtend(DMIC_Type * base,dmic_channel_t channel,bool enable)283 static inline void DMIC_EnableChannelSignExtend(DMIC_Type *base, dmic_channel_t channel, bool enable)
284 {
285 if (enable)
286 {
287 base->CHANNEL[channel].DC_CTRL |= DMIC_CHANNEL_DC_CTRL_SIGNEXTEND_MASK;
288 }
289 else
290 {
291 base->CHANNEL[channel].DC_CTRL &= ~DMIC_CHANNEL_DC_CTRL_SIGNEXTEND_MASK;
292 }
293 }
294 #endif
295
296 /*!
297 * @brief Configure DMIC channel
298 *
299 * @param base : The base address of DMIC interface
300 * @param channel : DMIC channel
301 * @param side : stereo_side_t, choice of left or right
302 * @param channel_config : Channel configuration
303 * @return Nothing
304 */
305 void DMIC_ConfigChannel(DMIC_Type *base,
306 dmic_channel_t channel,
307 stereo_side_t side,
308 dmic_channel_config_t *channel_config);
309
310 /*!
311 * @brief Enable a particualr channel
312 * @param base : The base address of DMIC interface
313 * @param channelmask reference _dmic_channel_mask
314 * @return Nothing
315 */
316 void DMIC_EnableChannnel(DMIC_Type *base, uint32_t channelmask);
317
318 /*!
319 * @brief Configure fifo settings for DMIC channel
320 * @param base : The base address of DMIC interface
321 * @param channel : DMIC channel
322 * @param trig_level : FIFO trigger level
323 * @param enable : FIFO level
324 * @param resetn : FIFO reset
325 * @return Nothing
326 */
327 void DMIC_FifoChannel(DMIC_Type *base, uint32_t channel, uint32_t trig_level, uint32_t enable, uint32_t resetn);
328
329 /*!
330 * @brief Enable a particualr channel interrupt request.
331 * @param base : The base address of DMIC interface
332 * @param channel : Channel selection
333 * @param enable : true is enable, false is disable
334 */
DMIC_EnableChannelInterrupt(DMIC_Type * base,dmic_channel_t channel,bool enable)335 static inline void DMIC_EnableChannelInterrupt(DMIC_Type *base, dmic_channel_t channel, bool enable)
336 {
337 if (enable)
338 {
339 base->CHANNEL[channel].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK;
340 }
341 else
342 {
343 base->CHANNEL[channel].FIFO_CTRL &= ~DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK;
344 }
345 }
346
347 /*!
348 * @brief Enable a particualr channel dma request.
349 * @param base : The base address of DMIC interface
350 * @param channel : Channel selection
351 * @param enable : true is enable, false is disable
352 */
DMIC_EnableChannelDma(DMIC_Type * base,dmic_channel_t channel,bool enable)353 static inline void DMIC_EnableChannelDma(DMIC_Type *base, dmic_channel_t channel, bool enable)
354 {
355 if (enable)
356 {
357 base->CHANNEL[channel].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK;
358 }
359 else
360 {
361 base->CHANNEL[channel].FIFO_CTRL &= ~DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK;
362 }
363 }
364
365 /*!
366 * @brief Enable a particualr channel fifo.
367 * @param base : The base address of DMIC interface
368 * @param channel : Channel selection
369 * @param enable : true is enable, false is disable
370 */
DMIC_EnableChannelFifo(DMIC_Type * base,dmic_channel_t channel,bool enable)371 static inline void DMIC_EnableChannelFifo(DMIC_Type *base, dmic_channel_t channel, bool enable)
372 {
373 if (enable)
374 {
375 base->CHANNEL[channel].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK;
376 }
377 else
378 {
379 base->CHANNEL[channel].FIFO_CTRL &= ~DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK;
380 }
381 }
382
383 /*!
384 * @brief Channel fifo reset.
385 * @param base : The base address of DMIC interface
386 * @param channel : Channel selection
387 */
DMIC_DoFifoReset(DMIC_Type * base,dmic_channel_t channel)388 static inline void DMIC_DoFifoReset(DMIC_Type *base, dmic_channel_t channel)
389 {
390 /* reset FIFO */
391 base->CHANNEL[channel].FIFO_CTRL &= ~DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK;
392 /* normal operation */
393 base->CHANNEL[channel].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK;
394 }
395
396 /*!
397 * @brief Get FIFO status
398 * @param base : The base address of DMIC interface
399 * @param channel : DMIC channel
400 * @return FIFO status
401 */
DMIC_FifoGetStatus(DMIC_Type * base,uint32_t channel)402 static inline uint32_t DMIC_FifoGetStatus(DMIC_Type *base, uint32_t channel)
403 {
404 return base->CHANNEL[channel].FIFO_STATUS;
405 }
406
407 /*!
408 * @brief Clear FIFO status
409 * @param base : The base address of DMIC interface
410 * @param channel : DMIC channel
411 * @param mask : Bits to be cleared
412 * @return FIFO status
413 */
DMIC_FifoClearStatus(DMIC_Type * base,uint32_t channel,uint32_t mask)414 static inline void DMIC_FifoClearStatus(DMIC_Type *base, uint32_t channel, uint32_t mask)
415 {
416 base->CHANNEL[channel].FIFO_STATUS = mask;
417 }
418
419 /*!
420 * @brief Get FIFO data
421 * @param base : The base address of DMIC interface
422 * @param channel : DMIC channel
423 * @return FIFO data
424 */
DMIC_FifoGetData(DMIC_Type * base,uint32_t channel)425 static inline uint32_t DMIC_FifoGetData(DMIC_Type *base, uint32_t channel)
426 {
427 return base->CHANNEL[channel].FIFO_DATA;
428 }
429
430 /*!
431 * @brief Get FIFO address
432 * @param base : The base address of DMIC interface
433 * @param channel : DMIC channel
434 * @return FIFO data
435 */
DMIC_FifoGetAddress(DMIC_Type * base,uint32_t channel)436 static inline uint32_t DMIC_FifoGetAddress(DMIC_Type *base, uint32_t channel)
437 {
438 return (uint32_t)(&(base->CHANNEL[channel].FIFO_DATA));
439 }
440
441 #if defined(FSL_FEATURE_DMIC_HAS_DECIMATOR_RESET_FUNC) && FSL_FEATURE_DMIC_HAS_DECIMATOR_RESET_FUNC
442 /*!
443 * @brief DMIC channel Decimator reset
444 * @param base : The base address of DMIC interface
445 * @param channelMask : DMIC channel mask, reference _dmic_channel_mask
446 * @param reset : true is reset decimator, false is release decimator.
447 */
448 void DMIC_ResetChannelDecimator(DMIC_Type *base, uint32_t channelMask, bool reset);
449 #endif
450
451 #if defined(FSL_FEATURE_DMIC_HAS_GLOBAL_SYNC_FUNC) && FSL_FEATURE_DMIC_HAS_GLOBAL_SYNC_FUNC
452 /*!
453 * @brief Enable DMIC channel global sync function.
454 * @param base : The base address of DMIC interface
455 * @param channelMask : DMIC channel mask, reference _dmic_channel_mask
456 * @param syncCounter :sync counter will trigger a pulse whenever count reaches CCOUNTVAL. If CCOUNTVAL is set to 0,
457 * there will be a pulse on every cycle
458 */
DMIC_EnableChannelGlobalSync(DMIC_Type * base,uint32_t channelMask,uint32_t syncCounter)459 static inline void DMIC_EnableChannelGlobalSync(DMIC_Type *base, uint32_t channelMask, uint32_t syncCounter)
460 {
461 base->GLOBAL_COUNT_VAL = syncCounter;
462 base->GLOBAL_SYNC_EN = channelMask;
463 }
464
465 /*!
466 * @brief Disbale DMIC channel global sync function.
467 * @param base : The base address of DMIC interface
468 * @param channelMask : DMIC channel mask, reference _dmic_channel_mask
469 */
DMIC_DisableChannelGlobalSync(DMIC_Type * base,uint32_t channelMask)470 static inline void DMIC_DisableChannelGlobalSync(DMIC_Type *base, uint32_t channelMask)
471 {
472 base->GLOBAL_SYNC_EN &= ~channelMask;
473 }
474 #endif
475
476 /*! @} */
477
478 /*!
479 * @name Register callback.
480 * @{
481 */
482
483 /*!
484 * @brief Enable callback.
485
486 * This function enables the interrupt for the selected DMIC peripheral.
487 * The callback function is not enabled until this function is called.
488 *
489 * @param base Base address of the DMIC peripheral.
490 * @param cb callback Pointer to store callback function.
491 * @retval None.
492 */
493 void DMIC_EnableIntCallback(DMIC_Type *base, dmic_callback_t cb);
494
495 /*!
496 * @brief Disable callback.
497
498 * This function disables the interrupt for the selected DMIC peripheral.
499 *
500 * @param base Base address of the DMIC peripheral.
501 * @param cb callback Pointer to store callback function..
502 * @retval None.
503 */
504 void DMIC_DisableIntCallback(DMIC_Type *base, dmic_callback_t cb);
505 /*! @} */
506
507 /*!
508 * @name HWVAD
509 * @{
510 */
511
512 /*!
513 * @brief Sets the gain value for the noise estimator.
514 *
515 * @param base DMIC base pointer
516 * @param value gain value for the noise estimator.
517 * @retval None.
518 */
DMIC_SetGainNoiseEstHwvad(DMIC_Type * base,uint32_t value)519 static inline void DMIC_SetGainNoiseEstHwvad(DMIC_Type *base, uint32_t value)
520 {
521 assert(NULL != base);
522 base->HWVADTHGN = value & 0xFUL;
523 }
524
525 /*!
526 * @brief Sets the gain value for the signal estimator.
527 *
528 * @param base DMIC base pointer
529 * @param value gain value for the signal estimator.
530 * @retval None.
531 */
DMIC_SetGainSignalEstHwvad(DMIC_Type * base,uint32_t value)532 static inline void DMIC_SetGainSignalEstHwvad(DMIC_Type *base, uint32_t value)
533 {
534 assert(NULL != base);
535 base->HWVADTHGS = value & 0xFUL;
536 }
537
538 /*!
539 * @brief Sets the hwvad filter cutoff frequency parameter.
540 *
541 * @param base DMIC base pointer
542 * @param value cut off frequency value.
543 * @retval None.
544 */
DMIC_SetFilterCtrlHwvad(DMIC_Type * base,uint32_t value)545 static inline void DMIC_SetFilterCtrlHwvad(DMIC_Type *base, uint32_t value)
546 {
547 assert(NULL != base);
548 base->HWVADHPFS = value & 0x3UL;
549 }
550
551 /*!
552 * @brief Sets the input gain of hwvad.
553 *
554 * @param base DMIC base pointer
555 * @param value input gain value for hwvad.
556 * @retval None.
557 */
DMIC_SetInputGainHwvad(DMIC_Type * base,uint32_t value)558 static inline void DMIC_SetInputGainHwvad(DMIC_Type *base, uint32_t value)
559 {
560 assert(NULL != base);
561 base->HWVADGAIN = value & 0xFUL;
562 }
563
564 /*!
565 * @brief Clears hwvad internal interrupt flag.
566 *
567 * @param base DMIC base pointer
568 * @param st10 bit value.
569 * @retval None.
570 */
DMIC_CtrlClrIntrHwvad(DMIC_Type * base,bool st10)571 static inline void DMIC_CtrlClrIntrHwvad(DMIC_Type *base, bool st10)
572 {
573 assert(NULL != base);
574 base->HWVADST10 = (st10) ? 0x1UL : 0x0UL;
575 }
576
577 /*!
578 * @brief Resets hwvad filters.
579 *
580 * @param base DMIC base pointer
581 * @param rstt Reset bit value.
582 * @retval None.
583 */
DMIC_FilterResetHwvad(DMIC_Type * base,bool rstt)584 static inline void DMIC_FilterResetHwvad(DMIC_Type *base, bool rstt)
585 {
586 assert(NULL != base);
587 base->HWVADRSTT = (rstt) ? 0x1UL : 0x0UL;
588 }
589
590 /*!
591 * @brief Gets the value from output of the filter z7.
592 *
593 * @param base DMIC base pointer
594 * @retval output of filter z7.
595 */
DMIC_GetNoiseEnvlpEst(DMIC_Type * base)596 static inline uint16_t DMIC_GetNoiseEnvlpEst(DMIC_Type *base)
597 {
598 assert(NULL != base);
599 return (uint16_t)(base->HWVADLOWZ & 0xFFFFU);
600 }
601
602 /*!
603 * @brief Enable hwvad callback.
604
605 * This function enables the hwvad interrupt for the selected DMIC peripheral.
606 * The callback function is not enabled until this function is called.
607 *
608 * @param base Base address of the DMIC peripheral.
609 * @param vadcb callback Pointer to store callback function.
610 * @retval None.
611 */
612 void DMIC_HwvadEnableIntCallback(DMIC_Type *base, dmic_hwvad_callback_t vadcb);
613
614 /*!
615 * @brief Disable callback.
616
617 * This function disables the hwvad interrupt for the selected DMIC peripheral.
618 *
619 * @param base Base address of the DMIC peripheral.
620 * @param vadcb callback Pointer to store callback function..
621 * @retval None.
622 */
623 void DMIC_HwvadDisableIntCallback(DMIC_Type *base, dmic_hwvad_callback_t vadcb);
624
625 /*! @} */
626
627 #ifdef __cplusplus
628 }
629 #endif
630
631 /*! @}*/
632
633 #endif /* FSL_DMIC_H_ */
634
