1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K344_CONFIGURATION_GPR.h 10 * @version 1.9 11 * @date 2021-10-27 12 * @brief Peripheral Access Layer for S32K344_CONFIGURATION_GPR 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K344_CONFIGURATION_GPR_H_) /* Check if memory map has not been already included */ 58 #define S32K344_CONFIGURATION_GPR_H_ 59 60 #include "S32K344_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- CONFIGURATION_GPR Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup CONFIGURATION_GPR_Peripheral_Access_Layer CONFIGURATION_GPR Peripheral Access Layer 68 * @{ 69 */ 70 71 /** CONFIGURATION_GPR - Register Layout Typedef */ 72 typedef struct { 73 uint8_t RESERVED_0[28]; 74 __I uint32_t CONFIG_REG0; /**< General Purpose Configuration 0, offset: 0x1C */ 75 uint8_t RESERVED_1[20]; 76 __I uint32_t CONFIG_REG6; /**< General Purpose Configuration 6, offset: 0x34 */ 77 __I uint32_t CONFIG_RAMPR; /**< Configuration RAM Protected Region, offset: 0x38 */ 78 __I uint32_t CONFIG_CFPRL; /**< Configuration Code Flash Memory Active Block, offset: 0x3C */ 79 __I uint32_t CONFIG_CFPRH; /**< Configuration Code Flash Memory Passive Block, offset: 0x40 */ 80 __I uint32_t CONFIG_DFPR; /**< Configuration Data Flash Memory Protected Region, offset: 0x44 */ 81 uint8_t RESERVED_2[8]; 82 __I uint32_t CONFIG_PE_LOCK; /**< Configuration Program and Erase Lock, offset: 0x50 */ 83 __I uint32_t CONFIG_RAMPR_ALT; /**< Configuration RAM Protected Region Alternate, offset: 0x54 */ 84 __I uint32_t CONFIG_CFPRL_ALT; /**< Configuration Code Flash Memory Active Block Alternate, offset: 0x58 */ 85 __I uint32_t CONFIG_CFPRH_ALT; /**< Configuration Code Flash Memory Passive Block Alternate, offset: 0x5C */ 86 __I uint32_t CONFIG_DFPR_ALT; /**< Configuration Data Flash Memory Protected Region Alternate, offset: 0x60 */ 87 __IO uint32_t CONFIG_REG_GPR; /**< Configuration REG_GPR, offset: 0x64 */ 88 } CONFIGURATION_GPR_Type, *CONFIGURATION_GPR_MemMapPtr; 89 90 /** Number of instances of the CONFIGURATION_GPR module. */ 91 #define CONFIGURATION_GPR_INSTANCE_COUNT (1u) 92 93 /* CONFIGURATION_GPR - Peripheral instance base addresses */ 94 /** Peripheral CONFIGURATION_GPR base address */ 95 #define IP_CONFIGURATION_GPR_BASE (0x4039C000u) 96 /** Peripheral CONFIGURATION_GPR base pointer */ 97 #define IP_CONFIGURATION_GPR ((CONFIGURATION_GPR_Type *)IP_CONFIGURATION_GPR_BASE) 98 /** Array initializer of CONFIGURATION_GPR peripheral base addresses */ 99 #define IP_CONFIGURATION_GPR_BASE_ADDRS { IP_CONFIGURATION_GPR_BASE } 100 /** Array initializer of CONFIGURATION_GPR peripheral base pointers */ 101 #define IP_CONFIGURATION_GPR_BASE_PTRS { IP_CONFIGURATION_GPR } 102 103 /* ---------------------------------------------------------------------------- 104 -- CONFIGURATION_GPR Register Masks 105 ---------------------------------------------------------------------------- */ 106 107 /*! 108 * @addtogroup CONFIGURATION_GPR_Register_Masks CONFIGURATION_GPR Register Masks 109 * @{ 110 */ 111 112 /*! @name CONFIG_REG0 - General Purpose Configuration 0 */ 113 /*! @{ */ 114 115 #define CONFIGURATION_GPR_CONFIG_REG0_EDB_MASK (0x40U) 116 #define CONFIGURATION_GPR_CONFIG_REG0_EDB_SHIFT (6U) 117 #define CONFIGURATION_GPR_CONFIG_REG0_EDB_WIDTH (1U) 118 #define CONFIGURATION_GPR_CONFIG_REG0_EDB(x) (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_REG0_EDB_SHIFT)) & CONFIGURATION_GPR_CONFIG_REG0_EDB_MASK) 119 /*! @} */ 120 121 /*! @name CONFIG_REG6 - General Purpose Configuration 6 */ 122 /*! @{ */ 123 124 #define CONFIGURATION_GPR_CONFIG_REG6_QUADSPI_SDID_PCTL_MASK (0x1U) 125 #define CONFIGURATION_GPR_CONFIG_REG6_QUADSPI_SDID_PCTL_SHIFT (0U) 126 #define CONFIGURATION_GPR_CONFIG_REG6_QUADSPI_SDID_PCTL_WIDTH (1U) 127 #define CONFIGURATION_GPR_CONFIG_REG6_QUADSPI_SDID_PCTL(x) (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_REG6_QUADSPI_SDID_PCTL_SHIFT)) & CONFIGURATION_GPR_CONFIG_REG6_QUADSPI_SDID_PCTL_MASK) 128 129 #define CONFIGURATION_GPR_CONFIG_REG6_EMAC_CLOCK_GATE_MASK (0x4U) 130 #define CONFIGURATION_GPR_CONFIG_REG6_EMAC_CLOCK_GATE_SHIFT (2U) 131 #define CONFIGURATION_GPR_CONFIG_REG6_EMAC_CLOCK_GATE_WIDTH (1U) 132 #define CONFIGURATION_GPR_CONFIG_REG6_EMAC_CLOCK_GATE(x) (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_REG6_EMAC_CLOCK_GATE_SHIFT)) & CONFIGURATION_GPR_CONFIG_REG6_EMAC_CLOCK_GATE_MASK) 133 134 #define CONFIGURATION_GPR_CONFIG_REG6_FLEXIO_CLOCK_GATE_MASK (0x10U) 135 #define CONFIGURATION_GPR_CONFIG_REG6_FLEXIO_CLOCK_GATE_SHIFT (4U) 136 #define CONFIGURATION_GPR_CONFIG_REG6_FLEXIO_CLOCK_GATE_WIDTH (1U) 137 #define CONFIGURATION_GPR_CONFIG_REG6_FLEXIO_CLOCK_GATE(x) (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_REG6_FLEXIO_CLOCK_GATE_SHIFT)) & CONFIGURATION_GPR_CONFIG_REG6_FLEXIO_CLOCK_GATE_MASK) 138 139 #define CONFIGURATION_GPR_CONFIG_REG6_SAI_SDID_PCTL_MASK (0x20U) 140 #define CONFIGURATION_GPR_CONFIG_REG6_SAI_SDID_PCTL_SHIFT (5U) 141 #define CONFIGURATION_GPR_CONFIG_REG6_SAI_SDID_PCTL_WIDTH (1U) 142 #define CONFIGURATION_GPR_CONFIG_REG6_SAI_SDID_PCTL(x) (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_REG6_SAI_SDID_PCTL_SHIFT)) & CONFIGURATION_GPR_CONFIG_REG6_SAI_SDID_PCTL_MASK) 143 144 #define CONFIGURATION_GPR_CONFIG_REG6_HL_MASK (0x80000000U) 145 #define CONFIGURATION_GPR_CONFIG_REG6_HL_SHIFT (31U) 146 #define CONFIGURATION_GPR_CONFIG_REG6_HL_WIDTH (1U) 147 #define CONFIGURATION_GPR_CONFIG_REG6_HL(x) (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_REG6_HL_SHIFT)) & CONFIGURATION_GPR_CONFIG_REG6_HL_MASK) 148 /*! @} */ 149 150 /*! @name CONFIG_RAMPR - Configuration RAM Protected Region */ 151 /*! @{ */ 152 153 #define CONFIGURATION_GPR_CONFIG_RAMPR_SECURE_SIZE_MASK (0x1FFFE0U) 154 #define CONFIGURATION_GPR_CONFIG_RAMPR_SECURE_SIZE_SHIFT (5U) 155 #define CONFIGURATION_GPR_CONFIG_RAMPR_SECURE_SIZE_WIDTH (16U) 156 #define CONFIGURATION_GPR_CONFIG_RAMPR_SECURE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_RAMPR_SECURE_SIZE_SHIFT)) & CONFIGURATION_GPR_CONFIG_RAMPR_SECURE_SIZE_MASK) 157 158 #define CONFIGURATION_GPR_CONFIG_RAMPR_SOFT_LOCK_MASK (0x40000000U) 159 #define CONFIGURATION_GPR_CONFIG_RAMPR_SOFT_LOCK_SHIFT (30U) 160 #define CONFIGURATION_GPR_CONFIG_RAMPR_SOFT_LOCK_WIDTH (1U) 161 #define CONFIGURATION_GPR_CONFIG_RAMPR_SOFT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_RAMPR_SOFT_LOCK_SHIFT)) & CONFIGURATION_GPR_CONFIG_RAMPR_SOFT_LOCK_MASK) 162 163 #define CONFIGURATION_GPR_CONFIG_RAMPR_HARD_LOCK_MASK (0x80000000U) 164 #define CONFIGURATION_GPR_CONFIG_RAMPR_HARD_LOCK_SHIFT (31U) 165 #define CONFIGURATION_GPR_CONFIG_RAMPR_HARD_LOCK_WIDTH (1U) 166 #define CONFIGURATION_GPR_CONFIG_RAMPR_HARD_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_RAMPR_HARD_LOCK_SHIFT)) & CONFIGURATION_GPR_CONFIG_RAMPR_HARD_LOCK_MASK) 167 /*! @} */ 168 169 /*! @name CONFIG_CFPRL - Configuration Code Flash Memory Active Block */ 170 /*! @{ */ 171 172 #define CONFIGURATION_GPR_CONFIG_CFPRL_SECURE_SIZE_MASK (0x1FE000U) 173 #define CONFIGURATION_GPR_CONFIG_CFPRL_SECURE_SIZE_SHIFT (13U) 174 #define CONFIGURATION_GPR_CONFIG_CFPRL_SECURE_SIZE_WIDTH (8U) 175 #define CONFIGURATION_GPR_CONFIG_CFPRL_SECURE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_CFPRL_SECURE_SIZE_SHIFT)) & CONFIGURATION_GPR_CONFIG_CFPRL_SECURE_SIZE_MASK) 176 177 #define CONFIGURATION_GPR_CONFIG_CFPRL_SOFT_LOCK_MASK (0x40000000U) 178 #define CONFIGURATION_GPR_CONFIG_CFPRL_SOFT_LOCK_SHIFT (30U) 179 #define CONFIGURATION_GPR_CONFIG_CFPRL_SOFT_LOCK_WIDTH (1U) 180 #define CONFIGURATION_GPR_CONFIG_CFPRL_SOFT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_CFPRL_SOFT_LOCK_SHIFT)) & CONFIGURATION_GPR_CONFIG_CFPRL_SOFT_LOCK_MASK) 181 182 #define CONFIGURATION_GPR_CONFIG_CFPRL_HARD_LOCK_MASK (0x80000000U) 183 #define CONFIGURATION_GPR_CONFIG_CFPRL_HARD_LOCK_SHIFT (31U) 184 #define CONFIGURATION_GPR_CONFIG_CFPRL_HARD_LOCK_WIDTH (1U) 185 #define CONFIGURATION_GPR_CONFIG_CFPRL_HARD_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_CFPRL_HARD_LOCK_SHIFT)) & CONFIGURATION_GPR_CONFIG_CFPRL_HARD_LOCK_MASK) 186 /*! @} */ 187 188 /*! @name CONFIG_CFPRH - Configuration Code Flash Memory Passive Block */ 189 /*! @{ */ 190 191 #define CONFIGURATION_GPR_CONFIG_CFPRH_SECURE_SIZE_MASK (0x1FE000U) 192 #define CONFIGURATION_GPR_CONFIG_CFPRH_SECURE_SIZE_SHIFT (13U) 193 #define CONFIGURATION_GPR_CONFIG_CFPRH_SECURE_SIZE_WIDTH (8U) 194 #define CONFIGURATION_GPR_CONFIG_CFPRH_SECURE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_CFPRH_SECURE_SIZE_SHIFT)) & CONFIGURATION_GPR_CONFIG_CFPRH_SECURE_SIZE_MASK) 195 196 #define CONFIGURATION_GPR_CONFIG_CFPRH_SOFT_LOCK_MASK (0x40000000U) 197 #define CONFIGURATION_GPR_CONFIG_CFPRH_SOFT_LOCK_SHIFT (30U) 198 #define CONFIGURATION_GPR_CONFIG_CFPRH_SOFT_LOCK_WIDTH (1U) 199 #define CONFIGURATION_GPR_CONFIG_CFPRH_SOFT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_CFPRH_SOFT_LOCK_SHIFT)) & CONFIGURATION_GPR_CONFIG_CFPRH_SOFT_LOCK_MASK) 200 201 #define CONFIGURATION_GPR_CONFIG_CFPRH_HARD_LOCK_MASK (0x80000000U) 202 #define CONFIGURATION_GPR_CONFIG_CFPRH_HARD_LOCK_SHIFT (31U) 203 #define CONFIGURATION_GPR_CONFIG_CFPRH_HARD_LOCK_WIDTH (1U) 204 #define CONFIGURATION_GPR_CONFIG_CFPRH_HARD_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_CFPRH_HARD_LOCK_SHIFT)) & CONFIGURATION_GPR_CONFIG_CFPRH_HARD_LOCK_MASK) 205 /*! @} */ 206 207 /*! @name CONFIG_DFPR - Configuration Data Flash Memory Protected Region */ 208 /*! @{ */ 209 210 #define CONFIGURATION_GPR_CONFIG_DFPR_SECURE_SIZE_MASK (0x1FE000U) 211 #define CONFIGURATION_GPR_CONFIG_DFPR_SECURE_SIZE_SHIFT (13U) 212 #define CONFIGURATION_GPR_CONFIG_DFPR_SECURE_SIZE_WIDTH (8U) 213 #define CONFIGURATION_GPR_CONFIG_DFPR_SECURE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_DFPR_SECURE_SIZE_SHIFT)) & CONFIGURATION_GPR_CONFIG_DFPR_SECURE_SIZE_MASK) 214 215 #define CONFIGURATION_GPR_CONFIG_DFPR_SOFT_LOCK_MASK (0x40000000U) 216 #define CONFIGURATION_GPR_CONFIG_DFPR_SOFT_LOCK_SHIFT (30U) 217 #define CONFIGURATION_GPR_CONFIG_DFPR_SOFT_LOCK_WIDTH (1U) 218 #define CONFIGURATION_GPR_CONFIG_DFPR_SOFT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_DFPR_SOFT_LOCK_SHIFT)) & CONFIGURATION_GPR_CONFIG_DFPR_SOFT_LOCK_MASK) 219 220 #define CONFIGURATION_GPR_CONFIG_DFPR_HARD_LOCK_MASK (0x80000000U) 221 #define CONFIGURATION_GPR_CONFIG_DFPR_HARD_LOCK_SHIFT (31U) 222 #define CONFIGURATION_GPR_CONFIG_DFPR_HARD_LOCK_WIDTH (1U) 223 #define CONFIGURATION_GPR_CONFIG_DFPR_HARD_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_DFPR_HARD_LOCK_SHIFT)) & CONFIGURATION_GPR_CONFIG_DFPR_HARD_LOCK_MASK) 224 /*! @} */ 225 226 /*! @name CONFIG_PE_LOCK - Configuration Program and Erase Lock */ 227 /*! @{ */ 228 229 #define CONFIGURATION_GPR_CONFIG_PE_LOCK_PE_LOCK_BLOCK_0_MASK (0x1000U) 230 #define CONFIGURATION_GPR_CONFIG_PE_LOCK_PE_LOCK_BLOCK_0_SHIFT (12U) 231 #define CONFIGURATION_GPR_CONFIG_PE_LOCK_PE_LOCK_BLOCK_0_WIDTH (1U) 232 #define CONFIGURATION_GPR_CONFIG_PE_LOCK_PE_LOCK_BLOCK_0(x) (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_PE_LOCK_PE_LOCK_BLOCK_0_SHIFT)) & CONFIGURATION_GPR_CONFIG_PE_LOCK_PE_LOCK_BLOCK_0_MASK) 233 234 #define CONFIGURATION_GPR_CONFIG_PE_LOCK_PE_LOCK_BLOCK_1_MASK (0x2000U) 235 #define CONFIGURATION_GPR_CONFIG_PE_LOCK_PE_LOCK_BLOCK_1_SHIFT (13U) 236 #define CONFIGURATION_GPR_CONFIG_PE_LOCK_PE_LOCK_BLOCK_1_WIDTH (1U) 237 #define CONFIGURATION_GPR_CONFIG_PE_LOCK_PE_LOCK_BLOCK_1(x) (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_PE_LOCK_PE_LOCK_BLOCK_1_SHIFT)) & CONFIGURATION_GPR_CONFIG_PE_LOCK_PE_LOCK_BLOCK_1_MASK) 238 239 #define CONFIGURATION_GPR_CONFIG_PE_LOCK_PE_LOCK_BLOCK_2_MASK (0x4000U) 240 #define CONFIGURATION_GPR_CONFIG_PE_LOCK_PE_LOCK_BLOCK_2_SHIFT (14U) 241 #define CONFIGURATION_GPR_CONFIG_PE_LOCK_PE_LOCK_BLOCK_2_WIDTH (1U) 242 #define CONFIGURATION_GPR_CONFIG_PE_LOCK_PE_LOCK_BLOCK_2(x) (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_PE_LOCK_PE_LOCK_BLOCK_2_SHIFT)) & CONFIGURATION_GPR_CONFIG_PE_LOCK_PE_LOCK_BLOCK_2_MASK) 243 244 #define CONFIGURATION_GPR_CONFIG_PE_LOCK_PE_LOCK_BLOCK_3_MASK (0x8000U) 245 #define CONFIGURATION_GPR_CONFIG_PE_LOCK_PE_LOCK_BLOCK_3_SHIFT (15U) 246 #define CONFIGURATION_GPR_CONFIG_PE_LOCK_PE_LOCK_BLOCK_3_WIDTH (1U) 247 #define CONFIGURATION_GPR_CONFIG_PE_LOCK_PE_LOCK_BLOCK_3(x) (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_PE_LOCK_PE_LOCK_BLOCK_3_SHIFT)) & CONFIGURATION_GPR_CONFIG_PE_LOCK_PE_LOCK_BLOCK_3_MASK) 248 249 #define CONFIGURATION_GPR_CONFIG_PE_LOCK_PE_LOCK_BLOCK_4_MASK (0x10000U) 250 #define CONFIGURATION_GPR_CONFIG_PE_LOCK_PE_LOCK_BLOCK_4_SHIFT (16U) 251 #define CONFIGURATION_GPR_CONFIG_PE_LOCK_PE_LOCK_BLOCK_4_WIDTH (1U) 252 #define CONFIGURATION_GPR_CONFIG_PE_LOCK_PE_LOCK_BLOCK_4(x) (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_PE_LOCK_PE_LOCK_BLOCK_4_SHIFT)) & CONFIGURATION_GPR_CONFIG_PE_LOCK_PE_LOCK_BLOCK_4_MASK) 253 254 #define CONFIGURATION_GPR_CONFIG_PE_LOCK_PE_LOCK_UTEST_MASK (0x40000U) 255 #define CONFIGURATION_GPR_CONFIG_PE_LOCK_PE_LOCK_UTEST_SHIFT (18U) 256 #define CONFIGURATION_GPR_CONFIG_PE_LOCK_PE_LOCK_UTEST_WIDTH (1U) 257 #define CONFIGURATION_GPR_CONFIG_PE_LOCK_PE_LOCK_UTEST(x) (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_PE_LOCK_PE_LOCK_UTEST_SHIFT)) & CONFIGURATION_GPR_CONFIG_PE_LOCK_PE_LOCK_UTEST_MASK) 258 /*! @} */ 259 260 /*! @name CONFIG_RAMPR_ALT - Configuration RAM Protected Region Alternate */ 261 /*! @{ */ 262 263 #define CONFIGURATION_GPR_CONFIG_RAMPR_ALT_INVERT_VALUE_RAMPR_MASK (0xFFFFFFFFU) 264 #define CONFIGURATION_GPR_CONFIG_RAMPR_ALT_INVERT_VALUE_RAMPR_SHIFT (0U) 265 #define CONFIGURATION_GPR_CONFIG_RAMPR_ALT_INVERT_VALUE_RAMPR_WIDTH (32U) 266 #define CONFIGURATION_GPR_CONFIG_RAMPR_ALT_INVERT_VALUE_RAMPR(x) (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_RAMPR_ALT_INVERT_VALUE_RAMPR_SHIFT)) & CONFIGURATION_GPR_CONFIG_RAMPR_ALT_INVERT_VALUE_RAMPR_MASK) 267 /*! @} */ 268 269 /*! @name CONFIG_CFPRL_ALT - Configuration Code Flash Memory Active Block Alternate */ 270 /*! @{ */ 271 272 #define CONFIGURATION_GPR_CONFIG_CFPRL_ALT_INVERT_VALUE_CFPRAB_MASK (0xFFFFFFFFU) 273 #define CONFIGURATION_GPR_CONFIG_CFPRL_ALT_INVERT_VALUE_CFPRAB_SHIFT (0U) 274 #define CONFIGURATION_GPR_CONFIG_CFPRL_ALT_INVERT_VALUE_CFPRAB_WIDTH (32U) 275 #define CONFIGURATION_GPR_CONFIG_CFPRL_ALT_INVERT_VALUE_CFPRAB(x) (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_CFPRL_ALT_INVERT_VALUE_CFPRAB_SHIFT)) & CONFIGURATION_GPR_CONFIG_CFPRL_ALT_INVERT_VALUE_CFPRAB_MASK) 276 /*! @} */ 277 278 /*! @name CONFIG_CFPRH_ALT - Configuration Code Flash Memory Passive Block Alternate */ 279 /*! @{ */ 280 281 #define CONFIGURATION_GPR_CONFIG_CFPRH_ALT_INVERT_VALUE_CFPRP_MASK (0xFFFFFFFFU) 282 #define CONFIGURATION_GPR_CONFIG_CFPRH_ALT_INVERT_VALUE_CFPRP_SHIFT (0U) 283 #define CONFIGURATION_GPR_CONFIG_CFPRH_ALT_INVERT_VALUE_CFPRP_WIDTH (32U) 284 #define CONFIGURATION_GPR_CONFIG_CFPRH_ALT_INVERT_VALUE_CFPRP(x) (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_CFPRH_ALT_INVERT_VALUE_CFPRP_SHIFT)) & CONFIGURATION_GPR_CONFIG_CFPRH_ALT_INVERT_VALUE_CFPRP_MASK) 285 /*! @} */ 286 287 /*! @name CONFIG_DFPR_ALT - Configuration Data Flash Memory Protected Region Alternate */ 288 /*! @{ */ 289 290 #define CONFIGURATION_GPR_CONFIG_DFPR_ALT_INVERT_VALUE_DFPR_MASK (0xFFFFFFFFU) 291 #define CONFIGURATION_GPR_CONFIG_DFPR_ALT_INVERT_VALUE_DFPR_SHIFT (0U) 292 #define CONFIGURATION_GPR_CONFIG_DFPR_ALT_INVERT_VALUE_DFPR_WIDTH (32U) 293 #define CONFIGURATION_GPR_CONFIG_DFPR_ALT_INVERT_VALUE_DFPR(x) (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_DFPR_ALT_INVERT_VALUE_DFPR_SHIFT)) & CONFIGURATION_GPR_CONFIG_DFPR_ALT_INVERT_VALUE_DFPR_MASK) 294 /*! @} */ 295 296 /*! @name CONFIG_REG_GPR - Configuration REG_GPR */ 297 /*! @{ */ 298 299 #define CONFIGURATION_GPR_CONFIG_REG_GPR_FIRC_DIV_SEL_MASK (0x3U) 300 #define CONFIGURATION_GPR_CONFIG_REG_GPR_FIRC_DIV_SEL_SHIFT (0U) 301 #define CONFIGURATION_GPR_CONFIG_REG_GPR_FIRC_DIV_SEL_WIDTH (2U) 302 #define CONFIGURATION_GPR_CONFIG_REG_GPR_FIRC_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_REG_GPR_FIRC_DIV_SEL_SHIFT)) & CONFIGURATION_GPR_CONFIG_REG_GPR_FIRC_DIV_SEL_MASK) 303 304 #define CONFIGURATION_GPR_CONFIG_REG_GPR_APP_CORE_ACC_MASK (0xE0000000U) 305 #define CONFIGURATION_GPR_CONFIG_REG_GPR_APP_CORE_ACC_SHIFT (29U) 306 #define CONFIGURATION_GPR_CONFIG_REG_GPR_APP_CORE_ACC_WIDTH (3U) 307 #define CONFIGURATION_GPR_CONFIG_REG_GPR_APP_CORE_ACC(x) (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_REG_GPR_APP_CORE_ACC_SHIFT)) & CONFIGURATION_GPR_CONFIG_REG_GPR_APP_CORE_ACC_MASK) 308 /*! @} */ 309 310 /*! 311 * @} 312 */ /* end of group CONFIGURATION_GPR_Register_Masks */ 313 314 /*! 315 * @} 316 */ /* end of group CONFIGURATION_GPR_Peripheral_Access_Layer */ 317 318 #endif /* #if !defined(S32K344_CONFIGURATION_GPR_H_) */ 319
