1 /* 2 * Copyright 2021-2023 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 /** 7 * @file Clock_Ip_Data.c 8 * @version 1.0.0 9 * 10 * @brief CLOCK driver implementations. 11 * @details CLOCK driver implementations. 12 * 13 * @addtogroup CLOCK_DRIVER Clock Driver 14 * @{ 15 */ 16 17 18 #ifdef __cplusplus 19 extern "C"{ 20 #endif 21 22 23 /*================================================================================================== 24 * INCLUDE FILES 25 * 1) system and project includes 26 * 2) needed interfaces from external units 27 * 3) internal and external interfaces from this unit 28 ==================================================================================================*/ 29 30 31 #include "Clock_Ip_Private.h" 32 33 #if (defined(CLOCK_IP_ENABLE_USER_MODE_SUPPORT)) 34 #if (STD_ON == CLOCK_IP_ENABLE_USER_MODE_SUPPORT) 35 #define USER_MODE_REG_PROT_ENABLED (STD_ON) 36 #include "RegLockMacros.h" 37 #endif 38 #endif /* CLOCK_IP_ENABLE_USER_MODE_SUPPORT */ 39 40 /*================================================================================================== 41 SOURCE FILE VERSION INFORMATION 42 ==================================================================================================*/ 43 #define CLOCK_IP_DATA_VENDOR_ID_C 43 44 #define CLOCK_IP_DATA_AR_RELEASE_MAJOR_VERSION_C 4 45 #define CLOCK_IP_DATA_AR_RELEASE_MINOR_VERSION_C 7 46 #define CLOCK_IP_DATA_AR_RELEASE_REVISION_VERSION_C 0 47 #define CLOCK_IP_DATA_SW_MAJOR_VERSION_C 1 48 #define CLOCK_IP_DATA_SW_MINOR_VERSION_C 0 49 #define CLOCK_IP_DATA_SW_PATCH_VERSION_C 0 50 51 /*================================================================================================== 52 * FILE VERSION CHECKS 53 ==================================================================================================*/ 54 /* Check if Clock_Ip_Data.c file and Clock_Ip_Private.h file are of the same vendor */ 55 #if (CLOCK_IP_DATA_VENDOR_ID_C != CLOCK_IP_PRIVATE_VENDOR_ID) 56 #error "Clock_Ip_Data.c and Clock_Ip_Private.h have different vendor ids" 57 #endif 58 59 /* Check if Clock_Ip_Data.c file and Clock_Ip_Private.h file are of the same Autosar version */ 60 #if ((CLOCK_IP_DATA_AR_RELEASE_MAJOR_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_MAJOR_VERSION) || \ 61 (CLOCK_IP_DATA_AR_RELEASE_MINOR_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_MINOR_VERSION) || \ 62 (CLOCK_IP_DATA_AR_RELEASE_REVISION_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_REVISION_VERSION) \ 63 ) 64 #error "AutoSar Version Numbers of Clock_Ip_Data.c and Clock_Ip_Private.h are different" 65 #endif 66 67 /* Check if Clock_Ip_Data.c file and Clock_Ip_Private.h file are of the same Software version */ 68 #if ((CLOCK_IP_DATA_SW_MAJOR_VERSION_C != CLOCK_IP_PRIVATE_SW_MAJOR_VERSION) || \ 69 (CLOCK_IP_DATA_SW_MINOR_VERSION_C != CLOCK_IP_PRIVATE_SW_MINOR_VERSION) || \ 70 (CLOCK_IP_DATA_SW_PATCH_VERSION_C != CLOCK_IP_PRIVATE_SW_PATCH_VERSION) \ 71 ) 72 #error "Software Version Numbers of Clock_Ip_Data.c and Clock_Ip_Private.h are different" 73 #endif 74 75 #if (defined(CLOCK_IP_ENABLE_USER_MODE_SUPPORT)) 76 #if (STD_ON == CLOCK_IP_ENABLE_USER_MODE_SUPPORT) 77 #ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK 78 /* Check if Clock_Ip_Data.c file and RegLockMacros.h file are of the same Autosar version */ 79 #if ((CLOCK_IP_DATA_AR_RELEASE_MAJOR_VERSION_C != REGLOCKMACROS_AR_RELEASE_MAJOR_VERSION) || \ 80 (CLOCK_IP_DATA_AR_RELEASE_MINOR_VERSION_C != REGLOCKMACROS_AR_RELEASE_MINOR_VERSION)) 81 #error "AutoSar Version Numbers of Clock_Ip_Data.c and RegLockMacros.h are different" 82 #endif 83 #endif 84 #endif 85 #endif /* CLOCK_IP_ENABLE_USER_MODE_SUPPORT */ 86 87 /*================================================================================================== 88 LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS) 89 ==================================================================================================*/ 90 91 /*================================================================================================== 92 * LOCAL MACROS 93 ==================================================================================================*/ 94 95 96 97 #define CLOCK_IP_NO_CALLBACK 0U 98 #define CLOCK_IP_HWMUX_DIV_CMU 1U 99 #define CLOCK_IP_PCFS_DFS 1U 100 #define CLOCK_IP_PLL_MOD 1U 101 #define CLOCK_IP_GATE 1U 102 #define CLOCK_IP_HWMUX_CMU 2U 103 #define CLOCK_IP_PCFS_PLL_OUT 2U 104 #define CLOCK_IP_PLL 2U 105 #define CLOCK_IP_DFS 2U 106 #define CLOCK_IP_HWMUX_CMU_GATE 3U 107 #define CLOCK_IP_PLL_OUT 3U 108 #define CLOCK_IP_LFASTPLL 3U 109 #define CLOCK_IP_CMU 4U 110 #define CLOCK_IP_HWMUX 4U 111 #define CLOCK_IP_FAST_XOSC_CMU 5U 112 #define CLOCK_IP_HWMUX_DIV 5U 113 #define CLOCK_IP_HWMUX_AE 6U 114 #define CLOCK_IP_HWMUX_DIV_TRIGGER 7U 115 #define CLOCK_IP_SWMUX_DIV 8U 116 #define CLOCK_IP_CLKOUT 9U 117 #define CLOCK_IP_CLKOUT_CMU 9U 118 #define CLOCK_IP_HWMUX_MUL_DIV 10U 119 120 #define CLOCK_IP_DDR_EXTENSION 0U 121 #define CLOCK_IP_P0_SYS_EXTENSION 1U 122 #define CLOCK_IP_P1_SYS_EXTENSION 2U 123 #define CLOCK_IP_P1_SYS_DIV2_EXTENSION 3U 124 #define CLOCK_IP_P1_SYS_DIV4_EXTENSION 4U 125 #define CLOCK_IP_P2_SYS_EXTENSION 5U 126 #define CLOCK_IP_CORE_M33_EXTENSION 6U 127 #define CLOCK_IP_P2_SYS_DIV2_EXTENSION 7U 128 #define CLOCK_IP_P2_SYS_DIV4_EXTENSION 8U 129 #define CLOCK_IP_P3_SYS_EXTENSION 9U 130 #define CLOCK_IP_CE_SYS_DIV2_EXTENSION 10U 131 #define CLOCK_IP_CE_SYS_DIV4_EXTENSION 11U 132 #define CLOCK_IP_P3_SYS_DIV2_NOC_EXTENSION 12U 133 #define CLOCK_IP_P3_SYS_DIV4_EXTENSION 13U 134 #define CLOCK_IP_P4_SYS_EXTENSION 14U 135 #define CLOCK_IP_P4_SYS_DIV2_EXTENSION 15U 136 #define CLOCK_IP_HSE_SYS_DIV2_EXTENSION 16U 137 #define CLOCK_IP_P5_SYS_EXTENSION 17U 138 #define CLOCK_IP_P5_SYS_DIV2_EXTENSION 18U 139 #define CLOCK_IP_P5_SYS_DIV4_EXTENSION 19U 140 #define CLOCK_IP_P2_MATH_EXTENSION 20U 141 #define CLOCK_IP_P2_MATH_DIV3_EXTENSION 21U 142 #define CLOCK_IP_GLB_LBIST_EXTENSION 22U 143 #define CLOCK_IP_RTU0_CORE_EXTENSION 23U 144 #define CLOCK_IP_RTU0_CORE_DIV2_EXTENSION 24U 145 #define CLOCK_IP_RTU1_CORE_EXTENSION 25U 146 #define CLOCK_IP_RTU1_CORE_DIV2_EXTENSION 26U 147 #define CLOCK_IP_P0_PSI5_S_UTIL_EXTENSION 27U 148 #define CLOCK_IP_P4_PSI5_S_UTIL_EXTENSION 28U 149 #define CLOCK_IP_CLKOUT0_EXTENSION 29U 150 #define CLOCK_IP_CLKOUT1_EXTENSION 30U 151 #define CLOCK_IP_CLKOUT2_EXTENSION 31U 152 #define CLOCK_IP_CLKOUT3_EXTENSION 32U 153 #define CLOCK_IP_CLKOUT4_EXTENSION 33U 154 #define CLOCK_IP_ETH0_TX_MII_EXTENSION 34U 155 #define CLOCK_IP_P3_CAN_PE_EXTENSION 35U 156 #define CLOCK_IP_P0_FR_PE_EXTENSION 36U 157 #define CLOCK_IP_P0_LIN_BAUD_EXTENSION 37U 158 #define CLOCK_IP_P1_LIN_BAUD_EXTENSION 38U 159 #define CLOCK_IP_P4_LIN_BAUD_EXTENSION 39U 160 #define CLOCK_IP_P5_LIN_BAUD_EXTENSION 40U 161 #define CLOCK_IP_P0_CLKOUT_SRC_EXTENSION 41U 162 #define CLOCK_IP_P0_CTU_PER_EXTENSION 42U 163 #define CLOCK_IP_P0_DSPI_MSC_EXTENSION 43U 164 #define CLOCK_IP_P0_EMIOS_LCU_EXTENSION 44U 165 #define CLOCK_IP_P0_GTM_EXTENSION 45U 166 #define CLOCK_IP_P0_GTM_NOC_EXTENSION 46U 167 #define CLOCK_IP_P0_GTM_TS_EXTENSION 47U 168 #define CLOCK_IP_P0_LIN_EXTENSION 48U 169 #define CLOCK_IP_P0_NANO_EXTENSION 49U 170 #define CLOCK_IP_P0_PSI5_125K_EXTENSION 50U 171 #define CLOCK_IP_P0_PSI5_189K_EXTENSION 51U 172 #define CLOCK_IP_P0_PSI5_S_BAUD_EXTENSION 52U 173 #define CLOCK_IP_P0_PSI5_S_CORE_EXTENSION 53U 174 #define CLOCK_IP_P0_PSI5_S_TRIG0_EXTENSION 54U 175 #define CLOCK_IP_P0_PSI5_S_TRIG1_EXTENSION 55U 176 #define CLOCK_IP_P0_PSI5_S_TRIG2_EXTENSION 56U 177 #define CLOCK_IP_P0_PSI5_S_TRIG3_EXTENSION 57U 178 #define CLOCK_IP_P0_PSI5_S_UART_EXTENSION 58U 179 #define CLOCK_IP_P0_PSI5_S_WDOG0_EXTENSION 59U 180 #define CLOCK_IP_P0_PSI5_S_WDOG1_EXTENSION 60U 181 #define CLOCK_IP_P0_PSI5_S_WDOG2_EXTENSION 61U 182 #define CLOCK_IP_P0_PSI5_S_WDOG3_EXTENSION 62U 183 #define CLOCK_IP_P0_REG_INTF_2X_EXTENSION 63U 184 #define CLOCK_IP_P0_REG_INTF_EXTENSION 64U 185 #define CLOCK_IP_P1_CLKOUT_SRC_EXTENSION 65U 186 #define CLOCK_IP_P1_DSPI60_EXTENSION 66U 187 #define CLOCK_IP_P1_LFAST0_REF_EXTENSION 67U 188 #define CLOCK_IP_P1_LFAST1_REF_EXTENSION 68U 189 #define CLOCK_IP_P1_NETC_AXI_EXTENSION 69U 190 #define CLOCK_IP_P1_LIN_EXTENSION 70U 191 #define CLOCK_IP_ETH_TS_EXTENSION 71U 192 #define CLOCK_IP_ETH_TS_DIV4_EXTENSION 72U 193 #define CLOCK_IP_ETH0_REF_RMII_EXTENSION 73U 194 #define CLOCK_IP_ETH0_RX_MII_EXTENSION 74U 195 #define CLOCK_IP_ETH0_RX_RGMII_EXTENSION 75U 196 #define CLOCK_IP_ETH0_TX_RGMII_EXTENSION 76U 197 #define CLOCK_IP_ETH0_TX_RGMII_LPBK_EXTENSION 77U 198 #define CLOCK_IP_ETH1_REF_RMII_EXTENSION 78U 199 #define CLOCK_IP_ETH1_RX_MII_EXTENSION 79U 200 #define CLOCK_IP_ETH1_RX_RGMII_EXTENSION 80U 201 #define CLOCK_IP_ETH1_TX_MII_EXTENSION 81U 202 #define CLOCK_IP_ETH1_TX_RGMII_EXTENSION 82U 203 #define CLOCK_IP_ETH1_TX_RGMII_LPBK_EXTENSION 83U 204 #define CLOCK_IP_P1_REG_INTF_EXTENSION 84U 205 #define CLOCK_IP_P2_DBG_ATB_EXTENSION 85U 206 #define CLOCK_IP_P2_REG_INTF_EXTENSION 86U 207 #define CLOCK_IP_P3_AES_EXTENSION 87U 208 #define CLOCK_IP_P3_CLKOUT_SRC_EXTENSION 88U 209 #define CLOCK_IP_P3_DBG_TS_EXTENSION 89U 210 #define CLOCK_IP_P3_REG_INTF_EXTENSION 90U 211 #define CLOCK_IP_P4_CLKOUT_SRC_EXTENSION 91U 212 #define CLOCK_IP_P4_DSPI60_EXTENSION 92U 213 #define CLOCK_IP_P4_EMIOS_LCU_EXTENSION 93U 214 #define CLOCK_IP_P4_LIN_EXTENSION 94U 215 #define CLOCK_IP_P4_PSI5_125K_EXTENSION 95U 216 #define CLOCK_IP_P4_PSI5_189K_EXTENSION 96U 217 #define CLOCK_IP_P4_PSI5_S_BAUD_EXTENSION 97U 218 #define CLOCK_IP_P4_PSI5_S_CORE_EXTENSION 98U 219 #define CLOCK_IP_P4_PSI5_S_TRIG0_EXTENSION 99U 220 #define CLOCK_IP_P4_PSI5_S_TRIG1_EXTENSION 100U 221 #define CLOCK_IP_P4_PSI5_S_TRIG2_EXTENSION 101U 222 #define CLOCK_IP_P4_PSI5_S_TRIG3_EXTENSION 102U 223 #define CLOCK_IP_P4_PSI5_S_UART_EXTENSION 103U 224 #define CLOCK_IP_P4_PSI5_S_WDOG0_EXTENSION 104U 225 #define CLOCK_IP_P4_PSI5_S_WDOG1_EXTENSION 105U 226 #define CLOCK_IP_P4_PSI5_S_WDOG2_EXTENSION 106U 227 #define CLOCK_IP_P4_PSI5_S_WDOG3_EXTENSION 107U 228 #define CLOCK_IP_P4_QSPI0_2X_EXTENSION 108U 229 #define CLOCK_IP_P4_QSPI0_1X_EXTENSION 109U 230 #define CLOCK_IP_P4_QSPI1_2X_EXTENSION 110U 231 #define CLOCK_IP_P4_QSPI1_1X_EXTENSION 111U 232 #define CLOCK_IP_P4_REG_INTF_2X_EXTENSION 112U 233 #define CLOCK_IP_P4_REG_INTF_EXTENSION 113U 234 #define CLOCK_IP_P4_SDHC_IP_EXTENSION 114U 235 #define CLOCK_IP_P4_SDHC_IP_DIV2_EXTENSION 115U 236 #define CLOCK_IP_P5_AE_EXTENSION 116U 237 #define CLOCK_IP_P5_CANXL_PE_EXTENSION 117U 238 #define CLOCK_IP_P5_CANXL_CHI_EXTENSION 118U 239 #define CLOCK_IP_P5_CLKOUT_SRC_EXTENSION 119U 240 #define CLOCK_IP_P5_LIN_EXTENSION 120U 241 #define CLOCK_IP_P5_REG_INTF_EXTENSION 121U 242 #define CLOCK_IP_P6_REG_INTF_EXTENSION 122U 243 #define CLOCK_IP_P0_PSI5_1US_EXTENSION 123U 244 #define CLOCK_IP_P4_PSI5_1US_EXTENSION 124U 245 #define CLOCK_IP_RTU0_REG_INTF_EXTENSION 125U 246 #define CLOCK_IP_RTU1_REG_INTF_EXTENSION 126U 247 #define CLOCK_IP_P4_SDHC_EXTENSION 127U 248 #define CLOCK_IP_P0_DSPI_EXTENSION 128U 249 #define CLOCK_IP_P1_DSPI_EXTENSION 129U 250 #define CLOCK_IP_P4_DSPI_EXTENSION 130U 251 #define CLOCK_IP_P5_DSPI_EXTENSION 131U 252 253 #define CLOCK_IP_COREPLL_INSTANCE 0U 254 #define CLOCK_IP_PERIPHPLL_INSTANCE 1U 255 #define CLOCK_IP_DDRPLL_INSTANCE 2U 256 257 #define CLOCK_IP_COREDFS_INSTANCE 0U 258 #define CLOCK_IP_PERIPHDFS_INSTANCE 1U 259 260 #define CLOCK_IP_LFAST0_PLL_INSTANCE 0U 261 #define CLOCK_IP_LFAST1_PLL_INSTANCE 1U 262 263 #define CLOCK_IP_CGM0_INSTANCE 0U 264 #define CLOCK_IP_CGM1_INSTANCE 1U 265 #define CLOCK_IP_CGM2_INSTANCE 2U 266 #define CLOCK_IP_CGM3_INSTANCE 3U 267 #define CLOCK_IP_CGM4_INSTANCE 4U 268 #define CLOCK_IP_CGM5_INSTANCE 5U 269 #define CLOCK_IP_CGM6_INSTANCE 6U 270 #define CLOCK_IP_CGM7_INSTANCE 7U 271 #define CLOCK_IP_CGM8_INSTANCE 8U 272 #define CLOCK_IP_CGM_AE_INSTANCE 9U 273 274 #define CLOCK_IP_GPR0_INSTANCE 0U 275 #define CLOCK_IP_GPR1_INSTANCE 1U 276 #define CLOCK_IP_GPR3_INSTANCE 3U 277 #define CLOCK_IP_GPR4_INSTANCE 4U 278 #define CLOCK_IP_GPR5_INSTANCE 5U 279 280 #define CLOCK_IP_SMU_CMU_FC_INSTANCE 0U 281 #define CLOCK_IP_CMU_FC_0_INSTANCE 1U 282 #define CLOCK_IP_CMU_FC_1_INSTANCE 2U 283 #define CLOCK_IP_CMU_FC_2A_INSTANCE 3U 284 #define CLOCK_IP_CMU_FC_2B_INSTANCE 4U 285 #define CLOCK_IP_CMU_FC_2C_INSTANCE 5U 286 #define CLOCK_IP_CMU_FC_3_INSTANCE 6U 287 #define CLOCK_IP_CMU_FC_4_INSTANCE 7U 288 #define CLOCK_IP_CMU_FC_5_INSTANCE 8U 289 #define CLOCK_IP_CMU_FC_6_INSTANCE 9U 290 #define CLOCK_IP_CE_CMU_FC_0_INSTANCE 10U 291 #define CLOCK_IP_CE_CMU_FC_1_INSTANCE 11U 292 #define CLOCK_IP_CE_CMU_FC_2_INSTANCE 12U 293 #define CLOCK_IP_RTU0_CMU_FC_0_INSTANCE 13U 294 #define CLOCK_IP_RTU0_CMU_FC_1_INSTANCE 14U 295 #define CLOCK_IP_RTU0_CMU_FC_2_INSTANCE 15U 296 #define CLOCK_IP_RTU0_CMU_FC_3_INSTANCE 16U 297 #define CLOCK_IP_RTU0_CMU_FC_4_INSTANCE 17U 298 #define CLOCK_IP_RTU1_CMU_FC_0_INSTANCE 18U 299 #define CLOCK_IP_RTU1_CMU_FC_1_INSTANCE 19U 300 #define CLOCK_IP_RTU1_CMU_FC_2_INSTANCE 20U 301 #define CLOCK_IP_RTU1_CMU_FC_3_INSTANCE 21U 302 #define CLOCK_IP_RTU1_CMU_FC_4_INSTANCE 22U 303 #define CLOCK_IP_CMU_FC_DEBUG_1_INSTANCE 23U 304 #define CLOCK_IP_CMU_FC_DEBUG_2_INSTANCE 24U 305 #define CLOCK_IP_CMU_FC_AE_1_INSTANCE 25U 306 #define CLOCK_IP_CMU_FC_AE_2_INSTANCE 26U 307 #define CLOCK_IP_CMU_FC_AE_3_INSTANCE 27U 308 309 #define CLOCK_IP_P6_GROUP_0_BIT0_INDEX 0U 310 #define CLOCK_IP_P0_GROUP_13_BIT0_INDEX 1U 311 #define CLOCK_IP_P0_GROUP_12_BIT0_INDEX 2U 312 #define CLOCK_IP_P3_GROUP_1_BIT0_INDEX 3U 313 #define CLOCK_IP_P3_GROUP_27_BIT0_INDEX 4U 314 #define CLOCK_IP_P3_GROUP_28_BIT0_INDEX 5U 315 #define CLOCK_IP_P3_GROUP_29_BIT0_INDEX 6U 316 #define CLOCK_IP_P3_GROUP_30_BIT0_INDEX 7U 317 #define CLOCK_IP_P3_GROUP_31_BIT0_INDEX 8U 318 #define CLOCK_IP_P3_GROUP_32_BIT0_INDEX 9U 319 #define CLOCK_IP_P0_GROUP_20_BIT0_INDEX 10U 320 #define CLOCK_IP_P0_GROUP_5_BIT1_INDEX 11U 321 #define CLOCK_IP_P1_GROUP_1_BIT1_INDEX 12U 322 #define CLOCK_IP_P4_GROUP_2_BIT1_INDEX 13U 323 #define CLOCK_IP_P5_GROUP_0_BIT1_INDEX 14U 324 #define CLOCK_IP_P0_GROUP_5_BIT2_INDEX 15U 325 #define CLOCK_IP_P1_GROUP_1_BIT2_INDEX 16U 326 #define CLOCK_IP_P4_GROUP_2_BIT2_INDEX 17U 327 #define CLOCK_IP_P5_GROUP_0_BIT2_INDEX 18U 328 #define CLOCK_IP_P0_GROUP_5_BIT0_INDEX 19U 329 #define CLOCK_IP_P1_GROUP_1_BIT0_INDEX 20U 330 #define CLOCK_IP_P3_GROUP_0_BIT0_INDEX 21U 331 #define CLOCK_IP_P4_GROUP_2_BIT0_INDEX 22U 332 #define CLOCK_IP_P5_GROUP_0_BIT0_INDEX 23U 333 #define CLOCK_IP_P1_GROUP_12_BIT0_INDEX 24U 334 #define CLOCK_IP_P3_GROUP_3_BIT0_INDEX 25U 335 #define CLOCK_IP_P3_GROUP_4_BIT0_INDEX 26U 336 #define CLOCK_IP_P3_GROUP_5_BIT0_INDEX 27U 337 #define CLOCK_IP_P3_GROUP_6_BIT0_INDEX 28U 338 #define CLOCK_IP_P3_GROUP_7_BIT0_INDEX 29U 339 #define CLOCK_IP_P3_GROUP_8_BIT0_INDEX 30U 340 #define CLOCK_IP_P3_GROUP_9_BIT0_INDEX 31U 341 #define CLOCK_IP_P3_GROUP_10_BIT0_INDEX 32U 342 #define CLOCK_IP_P3_GROUP_11_BIT0_INDEX 33U 343 #define CLOCK_IP_P3_GROUP_12_BIT0_INDEX 34U 344 #define CLOCK_IP_P3_GROUP_13_BIT0_INDEX 35U 345 #define CLOCK_IP_P3_GROUP_14_BIT0_INDEX 36U 346 #define CLOCK_IP_P3_GROUP_15_BIT0_INDEX 37U 347 #define CLOCK_IP_P3_GROUP_16_BIT0_INDEX 38U 348 #define CLOCK_IP_P3_GROUP_17_BIT0_INDEX 39U 349 #define CLOCK_IP_P3_GROUP_18_BIT0_INDEX 40U 350 #define CLOCK_IP_P3_GROUP_19_BIT0_INDEX 41U 351 #define CLOCK_IP_P3_GROUP_20_BIT0_INDEX 42U 352 #define CLOCK_IP_P3_GROUP_21_BIT0_INDEX 43U 353 #define CLOCK_IP_P3_GROUP_22_BIT0_INDEX 44U 354 #define CLOCK_IP_P3_GROUP_23_BIT0_INDEX 45U 355 #define CLOCK_IP_P3_GROUP_24_BIT0_INDEX 46U 356 #define CLOCK_IP_P3_GROUP_25_BIT0_INDEX 47U 357 #define CLOCK_IP_P3_GROUP_26_BIT0_INDEX 48U 358 #define CLOCK_IP_P0_GROUP_2_BIT0_INDEX 49U 359 #define CLOCK_IP_P0_GROUP_3_BIT0_INDEX 50U 360 #define CLOCK_IP_P0_GROUP_22_BIT0_INDEX 51U 361 #define CLOCK_IP_P0_GROUP_4_BIT0_INDEX 52U 362 #define CLOCK_IP_P1_GROUP_0_BIT0_INDEX 53U 363 #define CLOCK_IP_P4_GROUP_11_BIT0_INDEX 54U 364 #define CLOCK_IP_P0_GROUP_8_BIT0_INDEX 55U 365 #define CLOCK_IP_P0_GROUP_9_BIT0_INDEX 56U 366 #define CLOCK_IP_P0_GROUP_10_BIT0_INDEX 57U 367 #define CLOCK_IP_P1_GROUP_5_BIT0_INDEX 58U 368 #define CLOCK_IP_P1_GROUP_6_BIT0_INDEX 59U 369 #define CLOCK_IP_P1_GROUP_7_BIT0_INDEX 60U 370 #define CLOCK_IP_P4_GROUP_6_BIT0_INDEX 61U 371 #define CLOCK_IP_P4_GROUP_7_BIT0_INDEX 62U 372 #define CLOCK_IP_P4_GROUP_8_BIT0_INDEX 63U 373 #define CLOCK_IP_P5_GROUP_3_BIT0_INDEX 64U 374 #define CLOCK_IP_P5_GROUP_4_BIT0_INDEX 65U 375 #define CLOCK_IP_P5_GROUP_5_BIT0_INDEX 66U 376 #define CLOCK_IP_P0_GROUP_6_BIT0_INDEX 67U 377 #define CLOCK_IP_P0_GROUP_11_BIT0_INDEX 68U 378 #define CLOCK_IP_P0_GROUP_22_BIT1_INDEX 69U 379 #define CLOCK_IP_P0_GROUP_5_BIT3_INDEX 70U 380 #define CLOCK_IP_P1_GROUP_1_BIT3_INDEX 71U 381 #define CLOCK_IP_P4_GROUP_2_BIT3_INDEX 72U 382 #define CLOCK_IP_P5_GROUP_0_BIT3_INDEX 73U 383 #define CLOCK_IP_P0_GROUP_19_BIT0_INDEX 74U 384 #define CLOCK_IP_P4_GROUP_12_BIT0_INDEX 75U 385 #define CLOCK_IP_P0_GROUP_23_BIT0_INDEX 76U 386 #define CLOCK_IP_P4_GROUP_14_BIT0_INDEX 77U 387 #define CLOCK_IP_P4_GROUP_0_BIT0_INDEX 78U 388 #define CLOCK_IP_P4_GROUP_1_BIT0_INDEX 79U 389 #define CLOCK_IP_P3_GROUP_33_BIT0_INDEX 80U 390 #define CLOCK_IP_P4_GROUP_9_BIT0_INDEX 81U 391 #define CLOCK_IP_P0_GROUP_24_BIT0_INDEX 82U 392 #define CLOCK_IP_P1_GROUP_8_BIT0_INDEX 83U 393 #define CLOCK_IP_P1_GROUP_9_BIT0_INDEX 84U 394 #define CLOCK_IP_P0_GROUP_21_BIT0_INDEX 85U 395 #define CLOCK_IP_P1_GROUP_14_BIT0_INDEX 86U 396 #define CLOCK_IP_P4_GROUP_13_BIT0_INDEX 87U 397 #define CLOCK_IP_P5_GROUP_6_BIT0_INDEX 88U 398 #define CLOCK_IP_P0_GROUP_1_BIT0_INDEX 89U 399 #define CLOCK_IP_P0_GROUP_7_BIT0_INDEX 90U 400 #define CLOCK_IP_P1_GROUP_2_BIT0_INDEX 91U 401 #define CLOCK_IP_P1_GROUP_3_BIT0_INDEX 92U 402 #define CLOCK_IP_P1_GROUP_4_BIT0_INDEX 93U 403 #define CLOCK_IP_P4_GROUP_3_BIT0_INDEX 94U 404 #define CLOCK_IP_P4_GROUP_4_BIT0_INDEX 95U 405 #define CLOCK_IP_P4_GROUP_5_BIT0_INDEX 96U 406 #define CLOCK_IP_P5_GROUP_1_BIT0_INDEX 97U 407 #define CLOCK_IP_P5_GROUP_2_BIT0_INDEX 98U 408 #define CLOCK_IP_P1_GROUP_10_BIT0_INDEX 99U 409 #define CLOCK_IP_P4_GROUP_10_BIT0_INDEX 100U 410 411 #define CLOCK_IP_GATE_0_INDEX 0U 412 #define CLOCK_IP_GATE_1_INDEX 1U 413 #define CLOCK_IP_GATE_2_INDEX 2U 414 #define CLOCK_IP_GATE_3_INDEX 3U 415 #define CLOCK_IP_GATE_4_INDEX 4U 416 #define CLOCK_IP_GATE_5_INDEX 5U 417 #define CLOCK_IP_GATE_6_INDEX 6U 418 #define CLOCK_IP_GATE_7_INDEX 7U 419 #define CLOCK_IP_GATE_8_INDEX 8U 420 #define CLOCK_IP_GATE_9_INDEX 9U 421 #define CLOCK_IP_GATE_10_INDEX 10U 422 #define CLOCK_IP_GATE_11_INDEX 11U 423 #define CLOCK_IP_GATE_12_INDEX 12U 424 #define CLOCK_IP_GATE_13_INDEX 13U 425 #define CLOCK_IP_GATE_14_INDEX 14U 426 #define CLOCK_IP_GATE_15_INDEX 15U 427 #define CLOCK_IP_GATE_16_INDEX 16U 428 #define CLOCK_IP_GATE_17_INDEX 17U 429 #define CLOCK_IP_GATE_18_INDEX 18U 430 #define CLOCK_IP_GATE_19_INDEX 19U 431 #define CLOCK_IP_GATE_20_INDEX 20U 432 #define CLOCK_IP_GATE_21_INDEX 21U 433 #define CLOCK_IP_GATE_22_INDEX 22U 434 #define CLOCK_IP_GATE_23_INDEX 23U 435 #define CLOCK_IP_GATE_24_INDEX 24U 436 #define CLOCK_IP_GATE_25_INDEX 25U 437 #define CLOCK_IP_GATE_26_INDEX 26U 438 #define CLOCK_IP_GATE_27_INDEX 27U 439 #define CLOCK_IP_GATE_28_INDEX 28U 440 #define CLOCK_IP_GATE_29_INDEX 29U 441 #define CLOCK_IP_GATE_30_INDEX 30U 442 #define CLOCK_IP_GATE_31_INDEX 31U 443 #define CLOCK_IP_GATE_32_INDEX 32U 444 #define CLOCK_IP_GATE_33_INDEX 33U 445 446 #define CLOCK_IP_GROUP_0_INDEX 0U 447 #define CLOCK_IP_GROUP_1_INDEX 1U 448 #define CLOCK_IP_GROUP_3_INDEX 3U 449 #define CLOCK_IP_GROUP_4_INDEX 4U 450 #define CLOCK_IP_GROUP_5_INDEX 5U 451 #define CLOCK_IP_GROUP_6_INDEX 6U 452 453 #define CLOCK_IP_DIV_0_INDEX 0U 454 #define CLOCK_IP_DIV_1_INDEX 1U 455 #define CLOCK_IP_DIV_2_INDEX 2U 456 #define CLOCK_IP_DIV_3_INDEX 3U 457 #define CLOCK_IP_DIV_4_INDEX 4U 458 #define CLOCK_IP_DIV_5_INDEX 5U 459 #define CLOCK_IP_DIV_6_INDEX 6U 460 #define CLOCK_IP_DIV_7_INDEX 7U 461 462 #define CLOCK_IP_GATE_PCTL_0 0U 463 #define CLOCK_IP_GATE_PCTL_1 1U 464 #define CLOCK_IP_GATE_PCTL_2 2U 465 #define CLOCK_IP_GATE_PCTL_3 3U 466 467 468 #define CLOCK_IP_SEL_0_INDEX 0U 469 #define CLOCK_IP_SEL_1_INDEX 1U 470 #define CLOCK_IP_SEL_2_INDEX 2U 471 #define CLOCK_IP_SEL_3_INDEX 3U 472 #define CLOCK_IP_SEL_4_INDEX 4U 473 #define CLOCK_IP_SEL_5_INDEX 5U 474 #define CLOCK_IP_SEL_6_INDEX 6U 475 #define CLOCK_IP_SEL_7_INDEX 7U 476 #define CLOCK_IP_SEL_8_INDEX 8U 477 #define CLOCK_IP_SEL_9_INDEX 9U 478 #define CLOCK_IP_SEL_10_INDEX 10 479 #define CLOCK_IP_SEL_11_INDEX 11 480 #define CLOCK_IP_SEL_12_INDEX 12 481 #define CLOCK_IP_SEL_13_INDEX 13 482 #define CLOCK_IP_SEL_14_INDEX 14 483 484 #if defined(CLOCK_IP_HAS_FIRC_AE_CLK) 485 #define CLOCK_IP_PCFS_1_INDEX 1U 486 #endif 487 #define CLOCK_IP_PCFS_2_INDEX 2U 488 #define CLOCK_IP_PCFS_9_INDEX 9U 489 #define CLOCK_IP_PCFS_10_INDEX 10U 490 #define CLOCK_IP_PCFS_11_INDEX 11U 491 #define CLOCK_IP_PCFS_14_INDEX 14U 492 #define CLOCK_IP_PCFS_39_INDEX 39U 493 494 #if defined(IP_RTU0__MC_CGM) 495 #define CLOCK_IP_RTU0__MC_CGM IP_RTU0__MC_CGM 496 #endif 497 #if defined(IP_RTU1__MC_CGM) 498 #define CLOCK_IP_RTU1__MC_CGM IP_RTU1__MC_CGM 499 #endif 500 501 #if defined(CLOCK_IP_HAS_SYSTEM_SAFE_CLK) 502 #define CLOCK_IP_SAFE_POWER_MODE 0U 503 #endif 504 #if defined(CLOCK_IP_HAS_SYSTEM_DRUN_CLK) 505 #define CLOCK_IP_DRUN_POWER_MODE 1U 506 #endif 507 #if defined(CLOCK_IP_HAS_SYSTEM_RUN0_CLK) 508 #define CLOCK_IP_RUN0_POWER_MODE 2U 509 #endif 510 511 #define CLOCK_IP_COREPLL_DIVIDER_COUNT 1U 512 #define CLOCK_IP_PERIPHPLL_DIVIDER_COUNT 7U 513 #define CLOCK_IP_DDRPLL_DIVIDER_COUNT 1U 514 /*================================================================================================== 515 LOCAL CONSTANTS 516 ==================================================================================================*/ 517 518 519 /*================================================================================================== 520 LOCAL VARIABLES 521 ==================================================================================================*/ 522 523 524 /*================================================================================================== 525 GLOBAL CONSTANTS 526 ==================================================================================================*/ 527 528 /* Clock start constant section data */ 529 #define MCU_START_SEC_CONST_8 530 #include "Mcu_MemMap.h" 531 532 const uint8 Clock_Ip_au8DividerCallbackIndex[CLOCK_IP_ALL_CALLBACKS_COUNT] = { 533 CLOCK_IP_NO_CALLBACK, /* No callback */ 534 CLOCK_IP_CGM_X_DE_DIV_STAT_WITHOUT_PHASE, /* CLOCK_IP_HWMUX_DIV_CMU */ 535 CLOCK_IP_PLLDIG_PLL0DIV_DE_DIV_OUTPUT, /* CLOCK_IP_PCFS_PLL_OUT */ 536 CLOCK_IP_PLLDIG_PLL0DIV_DE_DIV_OUTPUT, /* CLOCK_IP_PLL_OUT */ 537 CLOCK_IP_NO_CALLBACK, /* No callback */ 538 CLOCK_IP_CGM_X_DE_DIV_STAT_WITHOUT_PHASE, /* CLOCK_IP_HWMUX_DIV */ 539 CLOCK_IP_NO_CALLBACK, /* No callback */ 540 CLOCK_IP_CGM_X_DE_DIV_STAT_WITHOUT_PHASE_WITH_TRIGGER, /* CLOCK_IP_HWMUX_DIV_TRIGGER */ 541 CLOCK_IP_CGM_X_DE_DIV_STAT_WITHOUT_PHASE, /*CLOCK_IP_SWMUX_DIV */ 542 CLOCK_IP_NO_CALLBACK, /* No callback */ 543 CLOCK_IP_CGM_X_DE_DIV_FMT_STAT_WITHOUT_PHASE, /* CLOCK_IP_HWMUX_MUL_DIV */ 544 }; 545 const uint8 Clock_Ip_au8DividerTriggerCallbackIndex[CLOCK_IP_ALL_CALLBACKS_COUNT] = { 546 CLOCK_IP_NO_CALLBACK, /* No callback */ 547 CLOCK_IP_NO_CALLBACK, /* No callback */ 548 CLOCK_IP_NO_CALLBACK, /* No callback */ 549 CLOCK_IP_NO_CALLBACK, /* No callback */ 550 CLOCK_IP_NO_CALLBACK, /* No callback */ 551 CLOCK_IP_NO_CALLBACK, /* No callback */ 552 CLOCK_IP_NO_CALLBACK, /* No callback */ 553 CLOCK_IP_CGM_X_DIV_TRIG_CTRL_TCTL_HHEN_UPD_STAT, /* CLOCK_IP_HWMUX_DIV_TRIGGER */ 554 CLOCK_IP_NO_CALLBACK, /* No callback */ 555 CLOCK_IP_NO_CALLBACK, /* No callback */ 556 CLOCK_IP_NO_CALLBACK, /* No callback */ 557 }; 558 const uint8 Clock_Ip_au8XoscCallbackIndex[CLOCK_IP_ALL_CALLBACKS_COUNT] = { 559 CLOCK_IP_NO_CALLBACK, /* No callback */ 560 CLOCK_IP_NO_CALLBACK, /* No callback */ 561 CLOCK_IP_NO_CALLBACK, /* No callback */ 562 CLOCK_IP_NO_CALLBACK, /* No callback */ 563 CLOCK_IP_NO_CALLBACK, /* No callback */ 564 CLOCK_IP_FXOSC_OSCON_BYP_EOCV_GM_SEL, /* CLOCK_IP_FAST_XOSC_CMU */ 565 CLOCK_IP_NO_CALLBACK, /* No callback */ 566 CLOCK_IP_NO_CALLBACK, /* No callback */ 567 CLOCK_IP_NO_CALLBACK, /* No callback */ 568 CLOCK_IP_NO_CALLBACK, /* No callback */ 569 CLOCK_IP_NO_CALLBACK, /* No callback */ 570 }; 571 const uint8 Clock_Ip_au8IrcoscCallbackIndex[CLOCK_IP_ALL_CALLBACKS_COUNT] = { 572 CLOCK_IP_NO_CALLBACK, /* No callback */ 573 CLOCK_IP_NO_CALLBACK, /* No callback */ 574 CLOCK_IP_NO_CALLBACK, /* No callback */ 575 CLOCK_IP_NO_CALLBACK, /* No callback */ 576 CLOCK_IP_NO_CALLBACK, /* No callback */ 577 CLOCK_IP_NO_CALLBACK, /* No callback */ 578 CLOCK_IP_NO_CALLBACK, /* No callback */ 579 CLOCK_IP_NO_CALLBACK, /* No callback */ 580 CLOCK_IP_NO_CALLBACK, /* No callback */ 581 CLOCK_IP_NO_CALLBACK, /* No callback */ 582 CLOCK_IP_NO_CALLBACK, /* No callback */ 583 }; 584 const uint8 Clock_Ip_au8GateCallbackIndex[CLOCK_IP_ALL_CALLBACKS_COUNT] = { 585 CLOCK_IP_NO_CALLBACK, /* No callback */ 586 CLOCK_IP_CONTROL_ENABLE_GPR_PCTL, /* CLOCK_IP_GATE */ 587 CLOCK_IP_NO_CALLBACK, /* No callback */ 588 CLOCK_IP_CONTROL_ENABLE_GPR_PCTL, /* CLOCK_IP_HWMUX_CMU_GATE */ 589 CLOCK_IP_NO_CALLBACK, /* No callback */ 590 CLOCK_IP_NO_CALLBACK, /* No callback */ 591 CLOCK_IP_NO_CALLBACK, /* No callback */ 592 CLOCK_IP_NO_CALLBACK, /* No callback */ 593 CLOCK_IP_NO_CALLBACK, /* No callback */ 594 CLOCK_IP_NO_CALLBACK, /* No callback */ 595 CLOCK_IP_NO_CALLBACK, /* No callback */ 596 }; 597 const uint8 Clock_Ip_au8FractionalDividerCallbackIndex[CLOCK_IP_ALL_CALLBACKS_COUNT] = { 598 CLOCK_IP_NO_CALLBACK, /* No callback */ 599 CLOCK_IP_DFS_MFI_MFN, /* CLOCK_IP_PCFS_DFS */ 600 CLOCK_IP_DFS_MFI_MFN, /* CLOCK_IP_DFS */ 601 CLOCK_IP_NO_CALLBACK, /* No callback */ 602 CLOCK_IP_NO_CALLBACK, /* No callback */ 603 CLOCK_IP_NO_CALLBACK, /* No callback */ 604 CLOCK_IP_NO_CALLBACK, /* No callback */ 605 CLOCK_IP_NO_CALLBACK, /* No callback */ 606 CLOCK_IP_NO_CALLBACK, /* No callback */ 607 CLOCK_IP_NO_CALLBACK, /* No callback */ 608 CLOCK_IP_NO_CALLBACK, /* No callback */ 609 }; 610 const uint8 Clock_Ip_au8PllCallbackIndex[CLOCK_IP_ALL_CALLBACKS_COUNT] = { 611 CLOCK_IP_NO_CALLBACK, /* No callback */ 612 CLOCK_IP_PLLDIG_RDIV_MFI_MFN_SDMEN_SSCGBYP_SPREADCTL_STEPNO_STEPSIZE,/* CLOCK_IP_PLL_MOD */ 613 CLOCK_IP_PLLDIG_RDIV_MFI_MFN_SDMEN, /* CLOCK_IP_PLL */ 614 CLOCK_IP_LFASTPLL_ENABLE, /* CLOCK_IP_LFASTPLL */ 615 CLOCK_IP_NO_CALLBACK, /* No callback */ 616 CLOCK_IP_NO_CALLBACK, /* No callback */ 617 CLOCK_IP_NO_CALLBACK, /* No callback */ 618 CLOCK_IP_NO_CALLBACK, /* No callback */ 619 CLOCK_IP_NO_CALLBACK, /* No callback */ 620 CLOCK_IP_NO_CALLBACK, /* No callback */ 621 CLOCK_IP_NO_CALLBACK, /* No callback */ 622 }; 623 const uint8 Clock_Ip_au8SelectorCallbackIndex[CLOCK_IP_ALL_CALLBACKS_COUNT] = { 624 CLOCK_IP_NO_CALLBACK, /* No callback */ 625 CLOCK_IP_CGM_X_CSC_CSS_CLK_SW_SWIP, /* CLOCK_IP_HWMUX_DIV_CMU */ 626 CLOCK_IP_CGM_X_CSC_CSS_CLK_SW_SWIP, /* CLOCK_IP_HWMUX_CMU */ 627 CLOCK_IP_CGM_X_CSC_CSS_CLK_SW_SWIP, /* CLOCK_IP_HWMUX_CMU_GATE */ 628 CLOCK_IP_CGM_X_CSC_CSS_CLK_SW_SWIP, /* CLOCK_IP_HWMUX */ 629 CLOCK_IP_CGM_X_CSC_CSS_CLK_SW_SWIP, /* CLOCK_IP_HWMUX_DIV */ 630 #if defined(CLOCK_IP_MC_ME_AE_GS_S_SYSCLK) 631 CLOCK_IP_MC_ME_AE_GS_S_SYSCLK, /* CLOCK_IP_HWMUX_AE */ 632 #else 633 CLOCK_IP_NO_CALLBACK, /* No callback */ 634 #endif 635 CLOCK_IP_CGM_X_CSC_CSS_CLK_SW_SWIP, /* CLOCK_IP_HWMUX_DIV_TRIGGER */ 636 CLOCK_IP_CGM_X_CSC_CSS_CS_GRIP, /* CLOCK_IP_SWMUX_DIV */ 637 CLOCK_IP_GPR_X_CLKOUT_SEL_MUXSEL, /* CLOCK_IP_CLKOUT */ 638 CLOCK_IP_CGM_X_CSC_CSS_CLK_SW_SWIP, /* CLOCK_IP_HWMUX_MUL_DIV */ 639 }; 640 const uint8 Clock_Ip_au8PcfsCallbackIndex[CLOCK_IP_ALL_CALLBACKS_COUNT] = { 641 CLOCK_IP_NO_CALLBACK, /* No callback */ 642 CLOCK_IP_CGM_X_PCFS_SDUR_DIVC_DIVE_DIVS, /* CLOCK_IP_PCFS_DFS */ 643 CLOCK_IP_CGM_X_PCFS_SDUR_DIVC_DIVE_DIVS, /* CLOCK_IP_PCFS_PLL_OUT */ 644 CLOCK_IP_NO_CALLBACK, /* No callback */ 645 CLOCK_IP_NO_CALLBACK, /* No callback */ 646 CLOCK_IP_NO_CALLBACK, /* No callback */ 647 CLOCK_IP_NO_CALLBACK, /* No callback */ 648 CLOCK_IP_NO_CALLBACK, /* No callback */ 649 CLOCK_IP_NO_CALLBACK, /* No callback */ 650 CLOCK_IP_NO_CALLBACK, /* No callback */ 651 CLOCK_IP_NO_CALLBACK, /* No callback */ 652 }; 653 const uint8 Clock_Ip_au8CmuCallbackIndex[CLOCK_IP_ALL_CALLBACKS_COUNT] = { 654 CLOCK_IP_NO_CALLBACK, /* No callback */ 655 CLOCK_IP_CMU_FC_FCE_REF_CNT_LFREF_HFREF, /* CLOCK_IP_HWMUX_DIV_CMU */ 656 CLOCK_IP_CMU_FC_FCE_REF_CNT_LFREF_HFREF, /* CLOCK_IP_HWMUX_CMU */ 657 CLOCK_IP_CMU_FC_FCE_REF_CNT_LFREF_HFREF, /* CLOCK_IP_HWMUX_CMU_GATE */ 658 CLOCK_IP_CMU_FC_FCE_REF_CNT_LFREF_HFREF, /* CLOCK_IP_CMU */ 659 CLOCK_IP_CMU_FC_FCE_REF_CNT_LFREF_HFREF, /* CLOCK_IP_FAST_XOSC_CMU */ 660 CLOCK_IP_NO_CALLBACK, /* No callback */ 661 CLOCK_IP_NO_CALLBACK, /* No callback */ 662 CLOCK_IP_NO_CALLBACK, /* No callback */ 663 CLOCK_IP_CMU_FC_FCE_REF_CNT_LFREF_HFREF, /* CLOCK_IP_CLKOUT_CMU */ 664 CLOCK_IP_NO_CALLBACK, /* No callback */ 665 }; 666 667 668 669 670 /* Clock features mapping */ 671 const uint8 Clock_Ip_au8ClockFeatures[CLOCK_IP_NAMES_NO][CLOCK_IP_FEATURES_NO] = 672 /* \ 673 *************************************************************************************************************************************************************************************************************************************************************************************************************************************** \ 674 ************************************ ****************************** ******************************** E ******************************** ************* ********************** *********************** **************************** ********************** **************************** \ 675 ************************************ I ****************************** C ******************************** X ******************************** ************* S ********************** D *********************** **************************** ********************** **************************** \ 676 ************************************ N ****************************** A ******************************** T ******************************** P ************* E ********************** I *********************** G **************************** P ********************** **************************** \ 677 ************************************ S ****************************** L ******************************** E ******************************** O ************* L ********************** V *********************** A **************************** C ********************** C **************************** \ 678 ************************************ T ****************************** L ******************************** N ******************************** W ************* E ********************** I *********************** T **************************** F ********************** M **************************** \ 679 ************************************ A ****************************** B ******************************** S ******************************** E ************* C ********************** D *********************** E **************************** S ********************** U **************************** \ 680 ************************************ N ****************************** A ******************************** I ******************************** R ************* T ********************** E *********************** **************************** ********************** **************************** \ 681 ************************************ C ****************************** C ******************************** O ******************************** ************* O ********************** R *********************** **************************** ********************** **************************** \ 682 ************************************ E ****************************** K ******************************** N ******************************** ************* R ********************** *********************** **************************** ********************** **************************** \ 683 ************************************ ****************************** ******************************** ******************************* ************* ********************** *********************** **************************** ********************** **************************** \ 684 ***************************************************************************************************************************************************************************************************************************************************************************************************************************************/ 685 { 686 /* CLOCK_IS_OFF clock */ {0U, CLOCK_IP_NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* CLOCK_IS_OFF */ 687 /* FIRC_CLK clock */ {0U, CLOCK_IP_CMU, 0U, 0U, 0U, 0U, 0U, 0U, CLOCK_IP_CMU_FC_2A_INSTANCE}, /* FIRC_CLK clock */ 688 /* FXOSC_CLK clock */ {0U, CLOCK_IP_FAST_XOSC_CMU, 0U, 0U, 0U, 0U, 0U, 0U, CLOCK_IP_CMU_FC_2B_INSTANCE}, /* FXOSC_CLK clock */ 689 /* SIRC_CLK clock */ {0U, CLOCK_IP_NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* SIRC_CLK clock */ 690 #if defined(CLOCK_IP_HAS_FIRC_AE_CLK) 691 /* FIRC_AE_CLK clock */ {0U, CLOCK_IP_CMU, 0U, 0U, 0U, 0U, 0U, CLOCK_IP_PCFS_1_INDEX, CLOCK_IP_CMU_FC_2A_INSTANCE}, /* FIRC_AE_CLK clock */ 692 #endif 693 /* COREPLL_CLK clock */ {CLOCK_IP_COREPLL_INSTANCE, CLOCK_IP_PLL_MOD, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* COREPLL_CLK clock */ 694 /* PERIPHPLL_CLK clock */ {CLOCK_IP_PERIPHPLL_INSTANCE, CLOCK_IP_PLL, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* PERIPHPLL_CLK clock */ 695 /* DDRPLL_CLK clock */ {CLOCK_IP_DDRPLL_INSTANCE, CLOCK_IP_PLL_MOD, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* DDRPLL_CLK clock */ 696 /* LFAST0_PLL_CLK clock */ {CLOCK_IP_LFAST0_PLL_INSTANCE, CLOCK_IP_LFASTPLL, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* LFAST0_PLL_CLK clock */ 697 /* LFAST1_PLL_CLK clock */ {CLOCK_IP_LFAST1_PLL_INSTANCE, CLOCK_IP_LFASTPLL, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* LFAST1_PLL_CLK clock */ 698 /* COREPLL_PHI0 clock */ {CLOCK_IP_COREPLL_INSTANCE, CLOCK_IP_PCFS_PLL_OUT, 0U, 0U, 0U, CLOCK_IP_DIV_0_INDEX, 0U, CLOCK_IP_PCFS_9_INDEX, 0U}, /* COREPLL_PHI0 clock */ 699 /* COREPLL_DFS0 clock */ {CLOCK_IP_COREDFS_INSTANCE, CLOCK_IP_PCFS_DFS, 0U, 0U, 0U, CLOCK_IP_DIV_0_INDEX, 0U, CLOCK_IP_PCFS_10_INDEX, 0U}, /* COREPLL_DFS0 clock */ 700 /* COREPLL_DFS1 clock */ {CLOCK_IP_COREDFS_INSTANCE, CLOCK_IP_PCFS_DFS, 0U, 0U, 0U, CLOCK_IP_DIV_1_INDEX, 0U, CLOCK_IP_PCFS_11_INDEX, 0U}, /* COREPLL_DFS1 clock */ 701 /* COREPLL_DFS2 clock */ {CLOCK_IP_COREDFS_INSTANCE, CLOCK_IP_DFS, 0U, 0U, 0U, CLOCK_IP_DIV_2_INDEX, 0U, 0U, 0U}, /* COREPLL_DFS2 clock */ 702 /* COREPLL_DFS3 clock */ {CLOCK_IP_COREDFS_INSTANCE, CLOCK_IP_DFS, 0U, 0U, 0U, CLOCK_IP_DIV_3_INDEX, 0U, 0U, 0U}, /* COREPLL_DFS3 clock */ 703 /* COREPLL_DFS4 clock */ {CLOCK_IP_COREDFS_INSTANCE, CLOCK_IP_PCFS_DFS, 0U, 0U, 0U, CLOCK_IP_DIV_4_INDEX, 0U, CLOCK_IP_PCFS_14_INDEX, 0U}, /* COREPLL_DFS4 clock */ 704 /* COREPLL_DFS5 clock */ {CLOCK_IP_COREDFS_INSTANCE, CLOCK_IP_DFS, 0U, 0U, 0U, CLOCK_IP_DIV_5_INDEX, 0U, 0U, 0U}, /* COREPLL_DFS5 clock */ 705 /* PERIPHPLL_PHI0 clock */ {CLOCK_IP_PERIPHPLL_INSTANCE, CLOCK_IP_PLL_OUT, 0U, 0U, 0U, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* PERIPHPLL_PHI0 clock */ 706 /* PERIPHPLL_PHI1 clock */ {CLOCK_IP_PERIPHPLL_INSTANCE, CLOCK_IP_PLL_OUT, 0U, 0U, 0U, CLOCK_IP_DIV_1_INDEX, 0U, 0U, 0U}, /* PERIPHPLL_PHI1 clock */ 707 /* PERIPHPLL_PHI2 clock */ {CLOCK_IP_PERIPHPLL_INSTANCE, CLOCK_IP_PLL_OUT, 0U, 0U, 0U, CLOCK_IP_DIV_2_INDEX, 0U, 0U, 0U}, /* PERIPHPLL_PHI2 clock */ 708 /* PERIPHPLL_PHI3 clock */ {CLOCK_IP_PERIPHPLL_INSTANCE, CLOCK_IP_PLL_OUT, 0U, 0U, 0U, CLOCK_IP_DIV_3_INDEX, 0U, 0U, 0U}, /* PERIPHPLL_PHI3 clock */ 709 /* PERIPHPLL_PHI4 clock */ {CLOCK_IP_PERIPHPLL_INSTANCE, CLOCK_IP_PLL_OUT, 0U, 0U, 0U, CLOCK_IP_DIV_4_INDEX, 0U, 0U, 0U}, /* PERIPHPLL_PHI4 clock */ 710 /* PERIPHPLL_PHI5 clock */ {CLOCK_IP_PERIPHPLL_INSTANCE, CLOCK_IP_PLL_OUT, 0U, 0U, 0U, CLOCK_IP_DIV_5_INDEX, 0U, 0U, 0U}, /* PERIPHPLL_PHI5 clock */ 711 /* PERIPHPLL_PHI6 clock */ {CLOCK_IP_PERIPHPLL_INSTANCE, CLOCK_IP_PLL_OUT, 0U, 0U, 0U, CLOCK_IP_DIV_6_INDEX, 0U, 0U, 0U}, /* PERIPHPLL_PHI6 clock */ 712 /* PERIPHPLL_DFS0 clock */ {CLOCK_IP_PERIPHDFS_INSTANCE, CLOCK_IP_DFS, 0U, 0U, 0U, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* PERIPHPLL_DFS0 clock */ 713 /* PERIPHPLL_DFS1 clock */ {CLOCK_IP_PERIPHDFS_INSTANCE, CLOCK_IP_DFS, 0U, 0U, 0U, CLOCK_IP_DIV_1_INDEX, 0U, 0U, 0U}, /* PERIPHPLL_DFS1 clock */ 714 /* PERIPHPLL_DFS2 clock */ {CLOCK_IP_PERIPHDFS_INSTANCE, CLOCK_IP_DFS, 0U, 0U, 0U, CLOCK_IP_DIV_2_INDEX, 0U, 0U, 0U}, /* PERIPHPLL_DFS2 clock */ 715 /* PERIPHPLL_DFS3 clock */ {CLOCK_IP_PERIPHDFS_INSTANCE, CLOCK_IP_DFS, 0U, 0U, 0U, CLOCK_IP_DIV_3_INDEX, 0U, 0U, 0U}, /* PERIPHPLL_DFS3 clock */ 716 /* PERIPHPLL_DFS4 clock */ {CLOCK_IP_PERIPHDFS_INSTANCE, CLOCK_IP_DFS, 0U, 0U, 0U, CLOCK_IP_DIV_4_INDEX, 0U, 0U, 0U}, /* PERIPHPLL_DFS4 clock */ 717 /* PERIPHPLL_DFS5 clock */ {CLOCK_IP_PERIPHDFS_INSTANCE, CLOCK_IP_DFS, 0U, 0U, 0U, CLOCK_IP_DIV_5_INDEX, 0U, 0U, 0U}, /* PERIPHPLL_DFS5 clock */ 718 /* DDRPLL_PHI0 clock */ {CLOCK_IP_DDRPLL_INSTANCE, CLOCK_IP_PCFS_PLL_OUT, 0U, 0U, 0U, CLOCK_IP_DIV_0_INDEX, 0U, CLOCK_IP_PCFS_39_INDEX, 0U}, /* DDRPLL_PHI0 clock */ 719 /* LFAST0_PLL_PH0_CLK clock */ {0U, CLOCK_IP_NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* LFAST0_PLL_PH0_CLK clock */ 720 /* LFAST0_PLL_PH0_CLK clock */ {0U, CLOCK_IP_NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* LFAST0_PLL_PH0_CLK clock */ 721 /* eth_rgmii_ref clock */ {0U, CLOCK_IP_NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* eth_rgmii_ref clock */ 722 /* tmr_1588_ref clock */ {0U, CLOCK_IP_NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* tmr_1588_ref clock */ 723 /* eth0_ext_rx clock */ {0U, CLOCK_IP_NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* eth0_ext_rx clock */ 724 /* eth0_ext_tx clock */ {0U, CLOCK_IP_NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* eth0_ext_tx clock */ 725 /* eth1_ext_rx clock */ {0U, CLOCK_IP_NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* eth1_ext_rx clock */ 726 /* eth1_ext_tx clock */ {0U, CLOCK_IP_NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* eth1_ext_tx clock */ 727 /* lfast0_ext_ref clock */ {0U, CLOCK_IP_NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* lfast0_ext_ref clock */ 728 /* lfast1_ext_ref clock */ {0U, CLOCK_IP_NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* lfast1_ext_ref clock */ 729 /* DDR_CLK clock */ {CLOCK_IP_CGM6_INSTANCE, CLOCK_IP_HWMUX_DIV_CMU, CLOCK_IP_DDR_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, CLOCK_IP_DIV_0_INDEX, CLOCK_IP_P6_GROUP_0_BIT0_INDEX, 0U, CLOCK_IP_CMU_FC_6_INSTANCE}, /* DDR_CLK clock */ 730 /* P0_SYS_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX, CLOCK_IP_P0_SYS_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, 0U, 0U, 0U, 0U}, /* P0_SYS_CLK clock */ 731 /* P1_SYS_CLK clock */ {CLOCK_IP_CGM1_INSTANCE, CLOCK_IP_HWMUX, CLOCK_IP_P1_SYS_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, 0U, 0U, 0U, 0U}, /* P1_SYS_CLK clock */ 732 /* P1_SYS_DIV2_CLK clock */ {CLOCK_IP_CGM1_INSTANCE, CLOCK_IP_NO_CALLBACK, CLOCK_IP_P1_SYS_DIV2_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, 0U, 0U, 0U, 0U}, /* P1_SYS_DIV2_CLK clock */ 733 /* P1_SYS_DIV4_CLK clock */ {CLOCK_IP_CGM1_INSTANCE, CLOCK_IP_NO_CALLBACK, CLOCK_IP_P1_SYS_DIV4_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, 0U, 0U, 0U, 0U}, /* P1_SYS_DIV4_CLK clock */ 734 /* P2_SYS_CLK clock */ {CLOCK_IP_CGM2_INSTANCE, CLOCK_IP_HWMUX_CMU, CLOCK_IP_P2_SYS_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, 0U, 0U, 0U, CLOCK_IP_SMU_CMU_FC_INSTANCE}, /* P2_SYS_CLK clock */ 735 /* CORE_M33_CLK clock */ {CLOCK_IP_CGM2_INSTANCE, CLOCK_IP_NO_CALLBACK, CLOCK_IP_CORE_M33_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, 0U, 0U, 0U, 0U}, /* CORE_M33_CLK clock */ 736 /* P2_SYS_DIV2_CLK clock */ {CLOCK_IP_CGM2_INSTANCE, CLOCK_IP_NO_CALLBACK, CLOCK_IP_P2_SYS_DIV2_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, 0U, 0U, 0U, 0U}, /* P2_SYS_DIV2_CLK clock */ 737 /* P2_SYS_DIV4_CLK clock */ {CLOCK_IP_CGM2_INSTANCE, CLOCK_IP_NO_CALLBACK, CLOCK_IP_P2_SYS_DIV4_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, 0U, 0U, 0U, 0U}, /* P2_SYS_DIV4_CLK clock */ 738 /* P3_SYS_CLK clock */ {CLOCK_IP_CGM3_INSTANCE, CLOCK_IP_HWMUX, CLOCK_IP_P3_SYS_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, 0U, 0U, 0U, 0U}, /* P3_SYS_CLK clock */ 739 /* CE_SYS_DIV2_CLK clock */ {CLOCK_IP_CGM3_INSTANCE, CLOCK_IP_CMU, CLOCK_IP_CE_SYS_DIV2_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, 0U, 0U, 0U, CLOCK_IP_CE_CMU_FC_2_INSTANCE}, /* CE_SYS_DIV2_CLK clock */ 740 /* CE_SYS_DIV4_CLK clock */ {CLOCK_IP_CGM3_INSTANCE, CLOCK_IP_NO_CALLBACK, CLOCK_IP_CE_SYS_DIV4_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, 0U, 0U, 0U, 0U}, /* CE_SYS_DIV4_CLK clock */ 741 /* P3_SYS_DIV2_NOC_CLK clock */ {CLOCK_IP_CGM3_INSTANCE, CLOCK_IP_NO_CALLBACK, CLOCK_IP_P3_SYS_DIV2_NOC_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, 0U, 0U, 0U, 0U}, /* P3_SYS_DIV2_NOC_CLK clock */ 742 /* P3_SYS_DIV4_CLK clock */ {CLOCK_IP_CGM3_INSTANCE, CLOCK_IP_NO_CALLBACK, CLOCK_IP_P3_SYS_DIV4_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, 0U, 0U, 0U, 0U}, /* P3_SYS_DIV4_CLK clock */ 743 /* P4_SYS_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX, CLOCK_IP_P4_SYS_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, 0U, 0U, 0U, 0U}, /* P4_SYS_CLK clock */ 744 /* P4_SYS_DIV2_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_NO_CALLBACK, CLOCK_IP_P4_SYS_DIV2_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, 0U, 0U, 0U, 0U}, /* P4_SYS_DIV2_CLK clock */ 745 /* HSE_SYS_DIV2_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_NO_CALLBACK, CLOCK_IP_HSE_SYS_DIV2_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, 0U, 0U, 0U, 0U}, /* HSE_SYS_DIV2_CLK clock */ 746 /* P5_SYS_CLK clock */ {CLOCK_IP_CGM5_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P5_SYS_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, 0U, 0U, 0U, 0U}, /* P5_SYS_CLK clock */ 747 /* P5_SYS_DIV2_CLK clock */ {CLOCK_IP_CGM5_INSTANCE, CLOCK_IP_NO_CALLBACK, CLOCK_IP_P5_SYS_DIV2_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, 0U, 0U, 0U, 0U}, /* P5_SYS_DIV2_CLK clock */ 748 /* P5_SYS_DIV4_CLK clock */ {CLOCK_IP_CGM5_INSTANCE, CLOCK_IP_NO_CALLBACK, CLOCK_IP_P5_SYS_DIV4_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, 0U, 0U, 0U, 0U}, /* P5_SYS_DIV4_CLK clock */ 749 /* P2_MATH_CLK clock */ {CLOCK_IP_CGM2_INSTANCE, CLOCK_IP_HWMUX_CMU, CLOCK_IP_P2_MATH_EXTENSION, 0U, CLOCK_IP_SEL_3_INDEX, 0U, 0U, 0U, CLOCK_IP_CMU_FC_2C_INSTANCE}, /* P2_MATH_CLK clock */ 750 /* P2_MATH_DIV3_CLK clock */ {CLOCK_IP_CGM2_INSTANCE, CLOCK_IP_NO_CALLBACK, CLOCK_IP_P2_MATH_DIV3_EXTENSION, 0U, CLOCK_IP_SEL_3_INDEX, 0U, 0U, 0U, 0U}, /* P2_MATH_DIV3_CLK clock */ 751 /* GLB_LBIST_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_GLB_LBIST_EXTENSION, 0U, CLOCK_IP_SEL_8_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* GLB_LBIST_CLK clock */ 752 /* RTU0_CORE_CLK clock */ {CLOCK_IP_CGM7_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_RTU0_CORE_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* RTU0_CORE_CLK clock */ 753 /* RTU0_CORE_DIV2_CLK clock */ {CLOCK_IP_CGM7_INSTANCE, CLOCK_IP_NO_CALLBACK, CLOCK_IP_RTU0_CORE_DIV2_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, 0U, 0U, 0U, 0U}, /* RTU0_CORE_DIV2_CLK clock */ 754 /* RTU1_CORE_CLK clock */ {CLOCK_IP_CGM8_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_RTU1_CORE_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* RTU1_CORE_CLK clock */ 755 /* RTU1_CORE_DIV2_CLK clock */ {CLOCK_IP_CGM8_INSTANCE, CLOCK_IP_NO_CALLBACK, CLOCK_IP_RTU1_CORE_DIV2_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, 0U, 0U, 0U, 0U}, /* RTU1_CORE_DIV2_CLK clock */ 756 /* P0_PSI5_S_UTIL_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P0_PSI5_S_UTIL_EXTENSION, 0U, CLOCK_IP_SEL_2_INDEX, CLOCK_IP_DIV_3_INDEX, 0U, 0U, 0U}, /* P0_PSI5_S_UTIL_CLK clock */ 757 /* P4_PSI5_S_UTIL_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P4_PSI5_S_UTIL_EXTENSION, 0U, CLOCK_IP_SEL_2_INDEX, CLOCK_IP_DIV_3_INDEX, 0U, 0U, 0U}, /* P4_PSI5_S_UTIL_CLK clock */ 758 #if defined(CLOCK_IP_HAS_SYSTEM_DRUN_CLK) 759 /* SYSTEM_DRUN_CLK clock */ {CLOCK_IP_CGM_AE_INSTANCE, CLOCK_IP_HWMUX_AE, 0U, CLOCK_IP_DRUN_POWER_MODE,0U, 0U, 0U, 0U, 0U}, /* SYSTEM_DRUN_CLK clock */ 760 #endif 761 #if defined(CLOCK_IP_HAS_SYSTEM_RUN0_CLK) 762 /* SYSTEM_RUN0_CLK clock */ {CLOCK_IP_CGM_AE_INSTANCE, CLOCK_IP_HWMUX_AE, 0U, CLOCK_IP_RUN0_POWER_MODE,0U, 0U, 0U, 0U, 0U}, /* SYSTEM_RUN0_CLK clock */ 763 #endif 764 #if defined(CLOCK_IP_HAS_SYSTEM_SAFE_CLK) 765 /* SYSTEM_SAFE_CLK clock */ {CLOCK_IP_CGM_AE_INSTANCE, CLOCK_IP_HWMUX_AE, 0U, CLOCK_IP_SAFE_POWER_MODE,0U, 0U, 0U, 0U, 0U}, /* SYSTEM_SAFE_CLK clock */ 766 #endif 767 #if defined(CLOCK_IP_HAS_SYSTEM_CLK) 768 /* SYSTEM_CLK clock */ {CLOCK_IP_CGM_AE_INSTANCE, CLOCK_IP_NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* SYSTEM_CLK clock */ 769 #endif 770 #if defined(CLOCK_IP_HAS_SYSTEM_DIV2_CLK) 771 /* SYSTEM_DIV2_CLK clock */ {CLOCK_IP_CGM_AE_INSTANCE, CLOCK_IP_CMU, 0U, 0U, 0U, 0U, 0U, 0U, CLOCK_IP_CMU_FC_AE_1_INSTANCE}, /* SYSTEM_DIV2_CLK clock */ 772 #endif 773 #if defined(CLOCK_IP_HAS_SYSTEM_DIV4_MON1_CLK) 774 /* SYSTEM_DIV4_MON1_CLK clock */ {CLOCK_IP_CGM_AE_INSTANCE, CLOCK_IP_CMU, 0U, 0U, 0U, 0U, 0U, 0U, CLOCK_IP_CMU_FC_AE_2_INSTANCE}, /* SYSTEM_DIV4_MON1_CLK clock */ 775 #endif 776 #if defined(CLOCK_IP_HAS_SYSTEM_DIV4_MON2_CLK) 777 /* SYSTEM_DIV4_MON2_CLK clock */ {CLOCK_IP_CGM_AE_INSTANCE, CLOCK_IP_CMU, 0U, 0U, 0U, 0U, 0U, 0U, CLOCK_IP_CMU_FC_AE_3_INSTANCE}, /* SYSTEM_DIV4_MON2_CLK clock */ 778 #endif 779 /* THE_LAST_PRODUCER_CLK */ {0U, CLOCK_IP_NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* THE_LAST_PRODUCER_CLK */ 780 /* ADC0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P0_GROUP_13_BIT0_INDEX, 0U, 0U}, /* ADC0_CLK clock */ 781 /* ADC1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P0_GROUP_12_BIT0_INDEX, 0U, 0U}, /* ADC1_CLK clock */ 782 /* CE_EDMA_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_1_BIT0_INDEX, 0U, 0U}, /* CE_EDMA_CLK clock */ 783 /* CE_PIT0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_27_BIT0_INDEX, 0U, 0U}, /* CE_PIT0_CLK clock */ 784 /* CE_PIT1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_28_BIT0_INDEX, 0U, 0U}, /* CE_PIT1_CLK clock */ 785 /* CE_PIT2_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_29_BIT0_INDEX, 0U, 0U}, /* CE_PIT2_CLK clock */ 786 /* CE_PIT3_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_30_BIT0_INDEX, 0U, 0U}, /* CE_PIT3_CLK clock */ 787 /* CE_PIT4_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_31_BIT0_INDEX, 0U, 0U}, /* CE_PIT4_CLK clock */ 788 /* CE_PIT5_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_32_BIT0_INDEX, 0U, 0U}, /* CE_PIT5_CLK clock */ 789 /* CLKOUT0_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_SWMUX_DIV, CLOCK_IP_CLKOUT0_EXTENSION, 0U, CLOCK_IP_SEL_10_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* CLKOUT0_CLK clock */ 790 /* CLKOUT1_CLK clock */ {CLOCK_IP_CGM1_INSTANCE, CLOCK_IP_SWMUX_DIV, CLOCK_IP_CLKOUT1_EXTENSION, 0U, CLOCK_IP_SEL_10_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* CLKOUT1_CLK clock */ 791 /* CLKOUT2_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_SWMUX_DIV, CLOCK_IP_CLKOUT2_EXTENSION, 0U, CLOCK_IP_SEL_6_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* CLKOUT2_CLK clock */ 792 /* CLKOUT3_CLK clock */ {CLOCK_IP_CGM5_INSTANCE, CLOCK_IP_SWMUX_DIV, CLOCK_IP_CLKOUT3_EXTENSION, 0U, CLOCK_IP_SEL_4_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* CLKOUT3_CLK clock */ 793 /* CLKOUT4_CLK clock */ {CLOCK_IP_CGM3_INSTANCE, CLOCK_IP_SWMUX_DIV, CLOCK_IP_CLKOUT4_EXTENSION, 0U, CLOCK_IP_SEL_4_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* CLKOUT4_CLK clock */ 794 /* CTU_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P0_GROUP_20_BIT0_INDEX, 0U, 0U}, /* CTU_CLK clock */ 795 /* DMACRC0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P0_GROUP_5_BIT1_INDEX, 0U, 0U}, /* DMACRC0_CLK clock */ 796 /* DMACRC1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P1_GROUP_1_BIT1_INDEX, 0U, 0U}, /* DMACRC1_CLK clock */ 797 /* DMACRC4_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P4_GROUP_2_BIT1_INDEX, 0U, 0U}, /* DMACRC4_CLK clock */ 798 /* DMACRC5_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P5_GROUP_0_BIT1_INDEX, 0U, 0U}, /* DMACRC5_CLK clock */ 799 /* DMAMUX0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P0_GROUP_5_BIT2_INDEX, 0U, 0U}, /* DMAMUX0_CLK clock */ 800 /* DMAMUX1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P1_GROUP_1_BIT2_INDEX, 0U, 0U}, /* DMAMUX1_CLK clock */ 801 /* DMAMUX4_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P4_GROUP_2_BIT2_INDEX, 0U, 0U}, /* DMAMUX4_CLK clock */ 802 /* DMAMUX5_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P5_GROUP_0_BIT2_INDEX, 0U, 0U}, /* DMAMUX5_CLK clock */ 803 /* EDMA0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P0_GROUP_5_BIT0_INDEX, 0U, 0U}, /* EDMA0_CLK clock */ 804 /* EDMA1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P1_GROUP_1_BIT0_INDEX, 0U, 0U}, /* EDMA1_CLK clock */ 805 /* EDMA3_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_0_BIT0_INDEX, 0U, 0U}, /* EDMA3_CLK clock */ 806 /* EDMA4_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P4_GROUP_2_BIT0_INDEX, 0U, 0U}, /* EDMA4_CLK clock */ 807 /* EDMA5_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P5_GROUP_0_BIT0_INDEX, 0U, 0U}, /* EDMA5_CLK clock */ 808 /* ETH0_TX_MII_CLK clock */ {CLOCK_IP_CGM1_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_ETH0_TX_MII_EXTENSION, 0U, CLOCK_IP_SEL_6_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* ETH0_TX_MII_CLK clock */ 809 /* ENET0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P1_GROUP_12_BIT0_INDEX, 0U, 0U}, /* ENET0_CLK clock */ 810 /* P3_CAN_PE_CLK clock */ {CLOCK_IP_CGM3_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P3_CAN_PE_EXTENSION, 0U, CLOCK_IP_SEL_3_INDEX, 0U, 0U, 0U, 0U}, /* P3_CAN_PE_CLK clock */ 811 /* FLEXCAN0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_3_BIT0_INDEX, 0U, 0U}, /* FLEXCAN0_CLK clock */ 812 /* FLEXCAN1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_4_BIT0_INDEX, 0U, 0U}, /* FLEXCAN1_CLK clock */ 813 /* FLEXCAN2_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_5_BIT0_INDEX, 0U, 0U}, /* FLEXCAN2_CLK clock */ 814 /* FLEXCAN3_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_6_BIT0_INDEX, 0U, 0U}, /* FLEXCAN3_CLK clock */ 815 /* FLEXCAN4_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_7_BIT0_INDEX, 0U, 0U}, /* FLEXCAN4_CLK clock */ 816 /* FLEXCAN5_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_8_BIT0_INDEX, 0U, 0U}, /* FLEXCAN5_CLK clock */ 817 /* FLEXCAN6_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_9_BIT0_INDEX, 0U, 0U}, /* FLEXCAN6_CLK clock */ 818 /* FLEXCAN7_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_10_BIT0_INDEX, 0U, 0U}, /* FLEXCAN7_CLK clock */ 819 /* FLEXCAN8_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_11_BIT0_INDEX, 0U, 0U}, /* FLEXCAN8_CLK clock */ 820 /* FLEXCAN9_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_12_BIT0_INDEX, 0U, 0U}, /* FLEXCAN9_CLK clock */ 821 /* FLEXCAN10_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_13_BIT0_INDEX, 0U, 0U}, /* FLEXCAN10_CLK clock */ 822 /* FLEXCAN11_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_14_BIT0_INDEX, 0U, 0U}, /* FLEXCAN11_CLK clock */ 823 /* FLEXCAN12_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_15_BIT0_INDEX, 0U, 0U}, /* FLEXCAN12_CLK clock */ 824 /* FLEXCAN13_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_16_BIT0_INDEX, 0U, 0U}, /* FLEXCAN13_CLK clock */ 825 /* FLEXCAN14_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_17_BIT0_INDEX, 0U, 0U}, /* FLEXCAN14_CLK clock */ 826 /* FLEXCAN15_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_18_BIT0_INDEX, 0U, 0U}, /* FLEXCAN15_CLK clock */ 827 /* FLEXCAN16_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_19_BIT0_INDEX, 0U, 0U}, /* FLEXCAN16_CLK clock */ 828 /* FLEXCAN17_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_20_BIT0_INDEX, 0U, 0U}, /* FLEXCAN17_CLK clock */ 829 /* FLEXCAN18_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_21_BIT0_INDEX, 0U, 0U}, /* FLEXCAN18_CLK clock */ 830 /* FLEXCAN19_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_22_BIT0_INDEX, 0U, 0U}, /* FLEXCAN19_CLK clock */ 831 /* FLEXCAN20_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_23_BIT0_INDEX, 0U, 0U}, /* FLEXCAN20_CLK clock */ 832 /* FLEXCAN21_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_24_BIT0_INDEX, 0U, 0U}, /* FLEXCAN21_CLK clock */ 833 /* FLEXCAN22_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_25_BIT0_INDEX, 0U, 0U}, /* FLEXCAN22_CLK clock */ 834 /* FLEXCAN23_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_26_BIT0_INDEX, 0U, 0U}, /* FLEXCAN23_CLK clock */ 835 /* P0_FR_PE_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P0_FR_PE_EXTENSION, 0U, CLOCK_IP_SEL_6_INDEX, 0U, 0U, 0U, 0U}, /* P0_FR_PE_CLK clock */ 836 /* FRAY0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P0_GROUP_2_BIT0_INDEX, 0U, 0U}, /* FRAY0_CLK clock */ 837 /* FRAY1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P0_GROUP_3_BIT0_INDEX, 0U, 0U}, /* FRAY1_CLK clock */ 838 /* GTM_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P0_GROUP_22_BIT0_INDEX, 0U, 0U}, /* GTM_CLK clock */ 839 /* IIIC0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P0_GROUP_4_BIT0_INDEX, 0U, 0U}, /* IIIC0_CLK clock */ 840 /* IIIC1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P1_GROUP_0_BIT0_INDEX, 0U, 0U}, /* IIIC1_CLK clock */ 841 /* IIIC2_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P4_GROUP_11_BIT0_INDEX, 0U, 0U}, /* IIIC2_CLK clock */ 842 /* P0_LIN_BAUD_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P0_LIN_BAUD_EXTENSION, 0U, CLOCK_IP_SEL_4_INDEX, 0U, 0U, 0U, 0U}, /* P0_LIN_BAUD_CLK clock */ 843 /* LIN0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P0_GROUP_8_BIT0_INDEX, 0U, 0U}, /* LIN0_CLK clock */ 844 /* LIN1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P0_GROUP_9_BIT0_INDEX, 0U, 0U}, /* LIN1_CLK clock */ 845 /* LIN2_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P0_GROUP_10_BIT0_INDEX, 0U, 0U}, /* LIN2_CLK clock */ 846 /* P1_LIN_BAUD_CLK clock */ {CLOCK_IP_CGM1_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P1_LIN_BAUD_EXTENSION, 0U, CLOCK_IP_SEL_4_INDEX, 0U, 0U, 0U, 0U}, /* P1_LIN_BAUD_CLK clock */ 847 /* LIN3_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P1_GROUP_5_BIT0_INDEX, 0U, 0U}, /* LIN3_CLK clock */ 848 /* LIN4_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P1_GROUP_6_BIT0_INDEX, 0U, 0U}, /* LIN4_CLK clock */ 849 /* LIN5_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P1_GROUP_7_BIT0_INDEX, 0U, 0U}, /* LIN5_CLK clock */ 850 /* P4_LIN_BAUD_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P4_LIN_BAUD_EXTENSION, 0U, CLOCK_IP_SEL_8_INDEX, 0U, 0U, 0U, 0U}, /* P4_LIN_BAUD_CLK clock */ 851 /* LIN6_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P4_GROUP_6_BIT0_INDEX, 0U, 0U}, /* LIN6_CLK clock */ 852 /* LIN7_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P4_GROUP_7_BIT0_INDEX, 0U, 0U}, /* LIN7_CLK clock */ 853 /* LIN8_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P4_GROUP_8_BIT0_INDEX, 0U, 0U}, /* LIN8_CLK clock */ 854 /* P5_LIN_BAUD_CLK clock */ {CLOCK_IP_CGM5_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P5_LIN_BAUD_EXTENSION, 0U, CLOCK_IP_SEL_2_INDEX, 0U, 0U, 0U, 0U}, /* P5_LIN_BAUD_CLK clock */ 855 /* LIN9_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P5_GROUP_3_BIT0_INDEX, 0U, 0U}, /* LIN9_CLK clock */ 856 /* LIN10_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P5_GROUP_4_BIT0_INDEX, 0U, 0U}, /* LIN10_CLK clock */ 857 /* LIN11_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P5_GROUP_5_BIT0_INDEX, 0U, 0U}, /* LIN11_CLK clock */ 858 /* MSCDSPI_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P0_GROUP_6_BIT0_INDEX, 0U, 0U}, /* MSCDSPI_CLK clock */ 859 /* MSCLIN_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P0_GROUP_11_BIT0_INDEX, 0U, 0U}, /* MSCLIN_CLK clock */ 860 /* NANO_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P0_GROUP_22_BIT1_INDEX, 0U, 0U}, /* NANO_CLK clock */ 861 /* P0_CLKOUT_SRC_CLK clock */ {CLOCK_IP_GPR0_INSTANCE, CLOCK_IP_CLKOUT_CMU, CLOCK_IP_P0_CLKOUT_SRC_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, 0U, 0U, 0U, CLOCK_IP_CMU_FC_DEBUG_1_INSTANCE}, /* P0_CLKOUT_SRC_CLK clock */ 862 /* P0_CTU_PER_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P0_CTU_PER_EXTENSION, 0U, CLOCK_IP_SEL_9_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* P0_CTU_PER_CLK clock */ 863 /* P0_DSPI_MSC_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX_DIV_TRIGGER, CLOCK_IP_P0_DSPI_MSC_EXTENSION, 0U, CLOCK_IP_SEL_7_INDEX, CLOCK_IP_DIV_1_INDEX, 0U, 0U, 0U}, /* P0_DSPI_MSC_CLK clock */ 864 /* P0_EMIOS_LCU_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX, CLOCK_IP_P0_EMIOS_LCU_EXTENSION, 0U, CLOCK_IP_SEL_9_INDEX, 0U, 0U, 0U, 0U}, /* P0_EMIOS_LCU_CLK clock */ 865 /* P0_GTM_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX_DIV_TRIGGER, CLOCK_IP_P0_GTM_EXTENSION, 0U, CLOCK_IP_SEL_7_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* P0_GTM_CLK clock */ 866 /* P0_GTM_NOC_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P0_GTM_NOC_EXTENSION, 0U, CLOCK_IP_SEL_7_INDEX, 0U, 0U, 0U, 0U}, /* P0_GTM_NOC_CLK clock */ 867 /* P0_GTM_TS_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P0_GTM_TS_EXTENSION, 0U, CLOCK_IP_SEL_7_INDEX, 0U, 0U, 0U, 0U}, /* P0_GTM_TS_CLK clock */ 868 /* P0_LIN_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P0_LIN_EXTENSION, 0U, CLOCK_IP_SEL_4_INDEX, 0U, 0U, 0U, 0U}, /* P0_LIN_CLK clock */ 869 /* P0_NANO_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX, CLOCK_IP_P0_NANO_EXTENSION, 0U, CLOCK_IP_SEL_7_INDEX, 0U, 0U, 0U, 0U}, /* P0_NANO_CLK clock */ 870 /* P0_PSI5_125K_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P0_PSI5_125K_EXTENSION, 0U, CLOCK_IP_SEL_2_INDEX, CLOCK_IP_DIV_1_INDEX, 0U, 0U, 0U}, /* P0_PSI5_125K_CLK clock */ 871 /* P0_PSI5_189K_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX_MUL_DIV, CLOCK_IP_P0_PSI5_189K_EXTENSION, 0U, CLOCK_IP_SEL_2_INDEX, CLOCK_IP_DIV_2_INDEX, 0U, 0U, 0U}, /* P0_PSI5_189K_CLK clock */ 872 /* P0_PSI5_S_BAUD_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P0_PSI5_S_BAUD_EXTENSION, 0U, CLOCK_IP_SEL_2_INDEX, CLOCK_IP_DIV_5_INDEX, 0U, 0U, 0U}, /* P0_PSI5_S_BAUD_CLK clock */ 873 /* P0_PSI5_S_CORE_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P0_PSI5_S_CORE_EXTENSION, 0U, CLOCK_IP_SEL_2_INDEX, 0U, 0U, 0U, 0U}, /* P0_PSI5_S_CORE_CLK clock */ 874 /* P0_PSI5_S_TRIG0_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P0_PSI5_S_TRIG0_EXTENSION, 0U, CLOCK_IP_SEL_3_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* P0_PSI5_S_TRIG0_CLK clock */ 875 /* P0_PSI5_S_TRIG1_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P0_PSI5_S_TRIG1_EXTENSION, 0U, CLOCK_IP_SEL_3_INDEX, CLOCK_IP_DIV_1_INDEX, 0U, 0U, 0U}, /* P0_PSI5_S_TRIG1_CLK clock */ 876 /* P0_PSI5_S_TRIG2_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P0_PSI5_S_TRIG2_EXTENSION, 0U, CLOCK_IP_SEL_3_INDEX, CLOCK_IP_DIV_2_INDEX, 0U, 0U, 0U}, /* P0_PSI5_S_TRIG2_CLK clock */ 877 /* P0_PSI5_S_TRIG3_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P0_PSI5_S_TRIG3_EXTENSION, 0U, CLOCK_IP_SEL_3_INDEX, CLOCK_IP_DIV_3_INDEX, 0U, 0U, 0U}, /* P0_PSI5_S_TRIG3_CLK clock */ 878 /* P0_PSI5_S_UART_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P0_PSI5_S_UART_EXTENSION, 0U, CLOCK_IP_SEL_2_INDEX, CLOCK_IP_DIV_4_INDEX, 0U, 0U, 0U}, /* P0_PSI5_S_UART_CLK clock */ 879 /* P0_PSI5_S_WDOG0_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P0_PSI5_S_WDOG0_EXTENSION, 0U, CLOCK_IP_SEL_3_INDEX, CLOCK_IP_DIV_4_INDEX, 0U, 0U, 0U}, /* P0_PSI5_S_WDOG0_CLK clock */ 880 /* P0_PSI5_S_WDOG1_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P0_PSI5_S_WDOG1_EXTENSION, 0U, CLOCK_IP_SEL_3_INDEX, CLOCK_IP_DIV_5_INDEX, 0U, 0U, 0U}, /* P0_PSI5_S_WDOG1_CLK clock */ 881 /* P0_PSI5_S_WDOG2_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P0_PSI5_S_WDOG2_EXTENSION, 0U, CLOCK_IP_SEL_3_INDEX, CLOCK_IP_DIV_6_INDEX, 0U, 0U, 0U}, /* P0_PSI5_S_WDOG2_CLK clock */ 882 /* P0_PSI5_S_WDOG3_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P0_PSI5_S_WDOG3_EXTENSION, 0U, CLOCK_IP_SEL_3_INDEX, CLOCK_IP_DIV_7_INDEX, 0U, 0U, 0U}, /* P0_PSI5_S_WDOG3_CLK clock */ 883 /* P0_REG_INTF_2X_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P0_REG_INTF_2X_EXTENSION, 0U, CLOCK_IP_SEL_1_INDEX, CLOCK_IP_DIV_1_INDEX, 0U, 0U, 0U}, /* P0_REG_INTF_2X_CLK clock */ 884 /* P0_REG_INTF_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX_DIV_CMU, CLOCK_IP_P0_REG_INTF_EXTENSION, 0U, CLOCK_IP_SEL_1_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, CLOCK_IP_CMU_FC_0_INSTANCE}, /* P0_REG_INTF_CLK clock */ 885 /* P1_CLKOUT_SRC_CLK clock */ {CLOCK_IP_GPR1_INSTANCE, CLOCK_IP_CLKOUT_CMU, CLOCK_IP_P1_CLKOUT_SRC_EXTENSION, 0U, CLOCK_IP_SEL_1_INDEX, 0U, 0U, 0U, CLOCK_IP_CMU_FC_DEBUG_2_INSTANCE}, /* P1_CLKOUT_SRC_CLK clock */ 886 /* P1_DSPI60_CLK clock */ {CLOCK_IP_CGM1_INSTANCE, CLOCK_IP_HWMUX, CLOCK_IP_P1_DSPI60_EXTENSION, 0U, CLOCK_IP_SEL_3_INDEX, 0U, 0U, 0U, 0U}, /* P1_DSPI60_CLK clock */ 887 /* ETH_TS_CLK clock */ {CLOCK_IP_CGM1_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_ETH_TS_EXTENSION, 0U, CLOCK_IP_SEL_5_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* ETH_TS_CLK clock */ 888 /* ETH_TS_DIV4_CLK clock */ {CLOCK_IP_CGM1_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_ETH_TS_DIV4_EXTENSION, 0U, CLOCK_IP_SEL_5_INDEX, 0U, 0U, 0U, 0U}, /* ETH_TS_DIV4_CLK clock */ 889 /* ETH0_REF_RMII_CLK clock */ {CLOCK_IP_CGM1_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_ETH0_REF_RMII_EXTENSION, 0U, CLOCK_IP_SEL_7_INDEX, CLOCK_IP_DIV_2_INDEX, 0U, 0U, 0U}, /* ETH0_REF_RMII_CLK clock */ 890 /* ETH0_RX_MII_CLK clock */ {CLOCK_IP_CGM1_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_ETH0_RX_MII_EXTENSION, 0U, CLOCK_IP_SEL_7_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* ETH0_RX_MII_CLK clock */ 891 /* ETH0_RX_RGMII_CLK clock */ {CLOCK_IP_CGM1_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_ETH0_RX_RGMII_EXTENSION, 0U, CLOCK_IP_SEL_7_INDEX, CLOCK_IP_DIV_1_INDEX, 0U, 0U, 0U}, /* ETH0_RX_RGMII_CLK clock */ 892 /* ETH0_TX_RGMII_CLK clock */ {CLOCK_IP_CGM1_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_ETH0_TX_RGMII_EXTENSION, 0U, CLOCK_IP_SEL_6_INDEX, CLOCK_IP_DIV_1_INDEX, 0U, 0U, 0U}, /* ETH0_TX_RGMII_CLK clock */ 893 /* ETH0_PS_TX_CLK */ {CLOCK_IP_CGM1_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_ETH0_TX_RGMII_LPBK_EXTENSION, 0U, CLOCK_IP_SEL_6_INDEX, CLOCK_IP_DIV_1_INDEX, 0U, 0U, 0U}, /* ETH0_PS_TX_CLK */ 894 /* ETH1_REF_RMII_CLK clock */ {CLOCK_IP_CGM1_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_ETH1_REF_RMII_EXTENSION, 0U, CLOCK_IP_SEL_9_INDEX, CLOCK_IP_DIV_2_INDEX, 0U, 0U, 0U}, /* ETH1_REF_RMII_CLK clock */ 895 /* ETH1_RX_MII_CLK clock */ {CLOCK_IP_CGM1_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_ETH1_RX_MII_EXTENSION, 0U, CLOCK_IP_SEL_9_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* ETH1_RX_MII_CLK clock */ 896 /* ETH1_RX_RGMII_CLK clock */ {CLOCK_IP_CGM1_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_ETH1_RX_RGMII_EXTENSION, 0U, CLOCK_IP_SEL_9_INDEX, CLOCK_IP_DIV_1_INDEX, 0U, 0U, 0U}, /* ETH1_RX_RGMII_CLK clock */ 897 /* ETH1_TX_MII_CLK clock */ {CLOCK_IP_CGM1_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_ETH1_TX_MII_EXTENSION, 0U, CLOCK_IP_SEL_8_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* ETH1_TX_MII_CLK clock */ 898 /* ETH1_TX_RGMII_CLK clock */ {CLOCK_IP_CGM1_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_ETH1_TX_RGMII_EXTENSION, 0U, CLOCK_IP_SEL_8_INDEX, CLOCK_IP_DIV_1_INDEX, 0U, 0U, 0U}, /* ETH1_TX_RGMII_CLK clock */ 899 /* ETH1_PS_TX_CLK */ {CLOCK_IP_CGM1_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_ETH1_TX_RGMII_LPBK_EXTENSION, 0U, CLOCK_IP_SEL_8_INDEX, CLOCK_IP_DIV_1_INDEX, 0U, 0U, 0U}, /* ETH1_PS_TX_CLK */ 900 /* P1_LFAST0_REF_CLK clock */ {CLOCK_IP_CGM1_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P1_LFAST0_REF_EXTENSION, 0U, CLOCK_IP_SEL_11_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* P1_LFAST0_REF_CLK clock */ 901 /* P1_LFAST1_REF_CLK clock */ {CLOCK_IP_CGM1_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P1_LFAST1_REF_EXTENSION, 0U, CLOCK_IP_SEL_12_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* P1_LFAST1_REF_CLK clock */ 902 /* P1_NETC_AXI_CLK clock */ {CLOCK_IP_CGM1_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P1_NETC_AXI_EXTENSION, 0U, CLOCK_IP_SEL_14_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* P1_NETC_AXI_CLK clock */ 903 /* P1_LIN_CLK clock */ {CLOCK_IP_CGM1_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P1_LIN_EXTENSION, 0U, CLOCK_IP_SEL_4_INDEX, 0U, 0U, 0U, 0U}, /* P1_LIN_CLK clock */ 904 /* P1_REG_INTF_CLK clock */ {CLOCK_IP_CGM1_INSTANCE, CLOCK_IP_HWMUX_DIV_CMU, CLOCK_IP_P1_REG_INTF_EXTENSION, 0U, CLOCK_IP_SEL_1_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, CLOCK_IP_CMU_FC_1_INSTANCE}, /* P1_REG_INTF_CLK clock */ 905 /* P2_DBG_ATB_CLK clock */ {CLOCK_IP_CGM2_INSTANCE, CLOCK_IP_HWMUX, CLOCK_IP_P2_DBG_ATB_EXTENSION, 0U, CLOCK_IP_SEL_2_INDEX, 0U, 0U, 0U, 0U}, /* P2_DBG_ATB_CLK clock */ 906 /* P2_REG_INTF_CLK clock */ {CLOCK_IP_CGM2_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P2_REG_INTF_EXTENSION, 0U, CLOCK_IP_SEL_1_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* P2_REG_INTF_CLK clock */ 907 /* P3_AES_CLK clock */ {CLOCK_IP_CGM3_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P3_AES_EXTENSION, 0U, CLOCK_IP_SEL_2_INDEX, CLOCK_IP_DIV_1_INDEX, 0U, 0U, 0U}, /* P3_AES_CLK clock */ 908 /* P3_CLKOUT_SRC_CLK clock */ {CLOCK_IP_GPR3_INSTANCE, CLOCK_IP_CLKOUT, CLOCK_IP_P3_CLKOUT_SRC_EXTENSION, 0U, CLOCK_IP_SEL_4_INDEX, 0U, 0U, 0U, 0U}, /* P3_CLKOUT_SRC_CLK clock */ 909 /* P3_DBG_TS_CLK clock */ {CLOCK_IP_CGM3_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P3_DBG_TS_EXTENSION, 0U, CLOCK_IP_SEL_2_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* P3_DBG_TS_CLK clock */ 910 /* P3_REG_INTF_CLK clock */ {CLOCK_IP_CGM3_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P3_REG_INTF_EXTENSION, 0U, CLOCK_IP_SEL_1_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* P3_REG_INTF_CLK clock */ 911 /* P3_SYS_MON1_CLK clock */ {0U, CLOCK_IP_CMU, 0U, 0U, 0U, 0U, 0U, 0U, CLOCK_IP_CMU_FC_3_INSTANCE}, /* P3_SYS_MON1_CLK clock */ 912 /* P3_SYS_MON2_CLK clock */ {0U, CLOCK_IP_CMU, 0U, 0U, 0U, 0U, 0U, 0U, CLOCK_IP_CE_CMU_FC_0_INSTANCE}, /* P3_SYS_MON2_CLK clock */ 913 /* P3_SYS_MON3_CLK clock */ {0U, CLOCK_IP_CMU, 0U, 0U, 0U, 0U, 0U, 0U, CLOCK_IP_CE_CMU_FC_1_INSTANCE}, /* P3_SYS_MON3_CLK clock */ 914 /* P4_CLKOUT_SRC_CLK clock */ {CLOCK_IP_GPR4_INSTANCE, CLOCK_IP_CLKOUT, CLOCK_IP_P4_CLKOUT_SRC_EXTENSION, 0U, CLOCK_IP_SEL_2_INDEX, 0U, 0U, 0U, 0U}, /* P4_CLKOUT_SRC_CLK clock */ 915 /* P4_DSPI60_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX, CLOCK_IP_P4_DSPI60_EXTENSION, 0U, CLOCK_IP_SEL_5_INDEX, 0U, 0U, 0U, 0U}, /* P4_DSPI60_CLK clock */ 916 /* P4_EMIOS_LCU_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX, CLOCK_IP_P4_EMIOS_LCU_EXTENSION, 0U, CLOCK_IP_SEL_11_INDEX, 0U, 0U, 0U, 0U}, /* P4_EMIOS_LCU_CLK clock */ 917 /* P4_LIN_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P4_LIN_EXTENSION, 0U, CLOCK_IP_SEL_8_INDEX, 0U, 0U, 0U, 0U}, /* P4_LIN_CLK clock */ 918 /* P4_PSI5_125K_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P4_PSI5_125K_EXTENSION, 0U, CLOCK_IP_SEL_2_INDEX, CLOCK_IP_DIV_1_INDEX, 0U, 0U, 0U}, /* P4_PSI5_125K_CLK clock */ 919 /* P4_PSI5_189K_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX_MUL_DIV, CLOCK_IP_P4_PSI5_189K_EXTENSION, 0U, CLOCK_IP_SEL_2_INDEX, CLOCK_IP_DIV_2_INDEX, 0U, 0U, 0U}, /* P4_PSI5_189K_CLK clock */ 920 /* P4_PSI5_S_BAUD_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P4_PSI5_S_BAUD_EXTENSION, 0U, CLOCK_IP_SEL_2_INDEX, CLOCK_IP_DIV_5_INDEX, 0U, 0U, 0U}, /* P4_PSI5_S_BAUD_CLK clock */ 921 /* P4_PSI5_S_CORE_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P4_PSI5_S_CORE_EXTENSION, 0U, CLOCK_IP_SEL_2_INDEX, 0U, 0U, 0U, 0U}, /* P4_PSI5_S_CORE_CLK clock */ 922 /* P4_PSI5_S_TRIG0_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P4_PSI5_S_TRIG0_EXTENSION, 0U, CLOCK_IP_SEL_3_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* P4_PSI5_S_TRIG0_CLK clock */ 923 /* P4_PSI5_S_TRIG1_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P4_PSI5_S_TRIG1_EXTENSION, 0U, CLOCK_IP_SEL_3_INDEX, CLOCK_IP_DIV_1_INDEX, 0U, 0U, 0U}, /* P4_PSI5_S_TRIG1_CLK clock */ 924 /* P4_PSI5_S_TRIG2_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P4_PSI5_S_TRIG2_EXTENSION, 0U, CLOCK_IP_SEL_3_INDEX, CLOCK_IP_DIV_2_INDEX, 0U, 0U, 0U}, /* P4_PSI5_S_TRIG2_CLK clock */ 925 /* P4_PSI5_S_TRIG3_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P4_PSI5_S_TRIG3_EXTENSION, 0U, CLOCK_IP_SEL_3_INDEX, CLOCK_IP_DIV_3_INDEX, 0U, 0U, 0U}, /* P4_PSI5_S_TRIG3_CLK clock */ 926 /* P4_PSI5_S_UART_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P4_PSI5_S_UART_EXTENSION, 0U, CLOCK_IP_SEL_2_INDEX, CLOCK_IP_DIV_4_INDEX, 0U, 0U, 0U}, /* P4_PSI5_S_UART_CLK clock */ 927 /* P4_PSI5_S_WDOG0_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P4_PSI5_S_WDOG0_EXTENSION, 0U, CLOCK_IP_SEL_3_INDEX, CLOCK_IP_DIV_4_INDEX, 0U, 0U, 0U}, /* P4_PSI5_S_WDOG0_CLK clock */ 928 /* P4_PSI5_S_WDOG1_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P4_PSI5_S_WDOG1_EXTENSION, 0U, CLOCK_IP_SEL_3_INDEX, CLOCK_IP_DIV_5_INDEX, 0U, 0U, 0U}, /* P4_PSI5_S_WDOG1_CLK clock */ 929 /* P4_PSI5_S_WDOG2_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P4_PSI5_S_WDOG2_EXTENSION, 0U, CLOCK_IP_SEL_3_INDEX, CLOCK_IP_DIV_6_INDEX, 0U, 0U, 0U}, /* P4_PSI5_S_WDOG2_CLK clock */ 930 /* P4_PSI5_S_WDOG3_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P4_PSI5_S_WDOG3_EXTENSION, 0U, CLOCK_IP_SEL_3_INDEX, CLOCK_IP_DIV_7_INDEX, 0U, 0U, 0U}, /* P4_PSI5_S_WDOG3_CLK clock */ 931 /* P4_QSPI0_2X_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P4_QSPI0_2X_EXTENSION, 0U, CLOCK_IP_SEL_7_INDEX, 0U, 0U, 0U, 0U}, /* P4_QSPI0_2X_CLK clock */ 932 /* P4_QSPI0_1X_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P4_QSPI0_1X_EXTENSION, 0U, CLOCK_IP_SEL_7_INDEX, 0U, 0U, 0U, 0U}, /* P4_QSPI0_1X_CLK clock */ 933 /* P4_QSPI1_2X_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P4_QSPI1_2X_EXTENSION, 0U, CLOCK_IP_SEL_9_INDEX, CLOCK_IP_DIV_1_INDEX, 0U, 0U, 0U}, /* P4_QSPI1_2X_CLK clock */ 934 /* P4_QSPI1_1X_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P4_QSPI1_1X_EXTENSION, 0U, CLOCK_IP_SEL_9_INDEX, CLOCK_IP_DIV_1_INDEX, 0U, 0U, 0U}, /* P4_QSPI1_1X_CLK clock */ 935 /* P4_REG_INTF_2X_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P4_REG_INTF_2X_EXTENSION, 0U, CLOCK_IP_SEL_1_INDEX, CLOCK_IP_DIV_1_INDEX, 0U, 0U, 0U}, /* P4_REG_INTF_2X_CLK clock */ 936 /* P4_REG_INTF_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX_DIV_CMU, CLOCK_IP_P4_REG_INTF_EXTENSION, 0U, CLOCK_IP_SEL_1_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, CLOCK_IP_CMU_FC_4_INSTANCE}, /* P4_REG_INTF_CLK clock */ 937 /* P4_SDHC_IP_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX, CLOCK_IP_P4_SDHC_IP_EXTENSION, 0U, CLOCK_IP_SEL_10_INDEX, 0U, 0U, 0U, 0U}, /* P4_SDHC_IP_CLK clock */ 938 /* P4_SDHC_IP_DIV2_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX, CLOCK_IP_P4_SDHC_IP_DIV2_EXTENSION, 0U, CLOCK_IP_SEL_10_INDEX, 0U, 0U, 0U, 0U}, /* P4_SDHC_IP_DIV2_CLK clock */ 939 /* P5_DIPORT_CLK clock */ {CLOCK_IP_CGM5_INSTANCE, CLOCK_IP_HWMUX, CLOCK_IP_P5_AE_EXTENSION, 0U, CLOCK_IP_SEL_5_INDEX, 0U, 0U, 0U, 0U}, /* P5_DIPORT_CLK clock */ 940 /* P5_AE_CLK clock */ {CLOCK_IP_CGM5_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P5_AE_EXTENSION, 0U, CLOCK_IP_SEL_5_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, CLOCK_IP_PCFS_2_INDEX, 0U}, /* P5_AE_CLK clock */ 941 /* P5_CANXL_PE_CLK clock */ {CLOCK_IP_CGM5_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P5_CANXL_PE_EXTENSION, 0U, CLOCK_IP_SEL_5_INDEX, CLOCK_IP_DIV_1_INDEX, 0U, 0U, 0U}, /* P5_CANXL_PE_CLK clock */ 942 /* P5_CANXL_CHI_CLK clock */ {CLOCK_IP_CGM5_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P5_CANXL_CHI_EXTENSION, 0U, CLOCK_IP_SEL_5_INDEX, CLOCK_IP_DIV_2_INDEX, 0U, 0U, 0U}, /* P5_CANXL_CHI_CLK clock */ 943 /* P5_CLKOUT_SRC_CLK clock */ {CLOCK_IP_GPR5_INSTANCE, CLOCK_IP_CLKOUT, CLOCK_IP_P5_CLKOUT_SRC_EXTENSION, 0U, CLOCK_IP_SEL_3_INDEX, 0U, 0U, 0U, 0U}, /* P5_CLKOUT_SRC_CLK clock */ 944 /* P5_LIN_CLK clock */ {CLOCK_IP_CGM5_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P5_LIN_EXTENSION, 0U, CLOCK_IP_SEL_2_INDEX, 0U, 0U, 0U, 0U}, /* P5_LIN_CLK clock */ 945 /* P5_REG_INTF_CLK clock */ {CLOCK_IP_CGM5_INSTANCE, CLOCK_IP_HWMUX_DIV_CMU, CLOCK_IP_P5_REG_INTF_EXTENSION, 0U, CLOCK_IP_SEL_1_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, CLOCK_IP_CMU_FC_5_INSTANCE}, /* P5_REG_INTF_CLK clock */ 946 /* P6_REG_INTF_CLK clock */ {CLOCK_IP_CGM6_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P6_REG_INTF_EXTENSION, 0U, CLOCK_IP_SEL_1_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* P6_REG_INTF_CLK clock */ 947 /* PIT0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P0_GROUP_5_BIT3_INDEX, 0U, 0U}, /* PIT0_CLK clock */ 948 /* PIT1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P1_GROUP_1_BIT3_INDEX, 0U, 0U}, /* PIT1_CLK clock */ 949 /* PIT4_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P4_GROUP_2_BIT3_INDEX, 0U, 0U}, /* PIT4_CLK clock */ 950 /* PIT5_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P5_GROUP_0_BIT3_INDEX, 0U, 0U}, /* PIT5_CLK clock */ 951 /* P0_PSI5_1US_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P0_PSI5_1US_EXTENSION, 0U, CLOCK_IP_SEL_2_INDEX, 0U, 0U, 0U, 0U}, /* P0_PSI5_1US_CLK clock */ 952 /* PSI5_0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P0_GROUP_19_BIT0_INDEX, 0U, 0U}, /* PSI5_0_CLK clock */ 953 /* P4_PSI5_1US_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P4_PSI5_1US_EXTENSION, 0U, CLOCK_IP_SEL_2_INDEX, 0U, 0U, 0U, 0U}, /* P4_PSI5_1US_CLK clock */ 954 /* PSI5_1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P4_GROUP_12_BIT0_INDEX, 0U, 0U}, /* PSI5_1_CLK clock */ 955 /* PSI5S_0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P0_GROUP_23_BIT0_INDEX, 0U, 0U}, /* PSI5S_0_CLK clock */ 956 /* PSI5S_1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P4_GROUP_14_BIT0_INDEX, 0U, 0U}, /* PSI5S_1_CLK clock */ 957 /* QSPI0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P4_GROUP_0_BIT0_INDEX, 0U, 0U}, /* QSPI0_CLK clock */ 958 /* QSPI1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P4_GROUP_1_BIT0_INDEX, 0U, 0U}, /* QSPI1_CLK clock */ 959 /* RTU0_CORE_MON1_CLK */ {0U, CLOCK_IP_CMU, 0U, 0U, 0U, 0U, 0U, 0U, CLOCK_IP_RTU0_CMU_FC_0_INSTANCE}, /* RTU0_CORE_MON1_CLK */ 960 /* RTU0_CORE_MON2_CLK */ {0U, CLOCK_IP_CMU, 0U, 0U, 0U, 0U, 0U, 0U, CLOCK_IP_RTU0_CMU_FC_3_INSTANCE}, /* RTU0_CORE_MON2_CLK */ 961 /* RTU0_CORE_DIV2_MON1_CLK */ {0U, CLOCK_IP_CMU, 0U, 0U, 0U, 0U, 0U, 0U, CLOCK_IP_RTU0_CMU_FC_1_INSTANCE}, /* RTU0_CORE_DIV2_MON1_CLK */ 962 /* RTU0_CORE_DIV2_MON2_CLK */ {0U, CLOCK_IP_CMU, 0U, 0U, 0U, 0U, 0U, 0U, CLOCK_IP_RTU0_CMU_FC_2_INSTANCE}, /* RTU0_CORE_DIV2_MON2_CLK */ 963 /* RTU0_CORE_DIV2_MON3_CLK */ {0U, CLOCK_IP_CMU, 0U, 0U, 0U, 0U, 0U, 0U, CLOCK_IP_RTU0_CMU_FC_4_INSTANCE}, /* RTU0_CORE_DIV2_MON3_CLK */ 964 /* RTU0_REG_INTF_CLK clock */ {CLOCK_IP_CGM7_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_RTU0_REG_INTF_EXTENSION, 0U, CLOCK_IP_SEL_1_INDEX, 0U, 0U, 0U, 0U}, /* RTU0_REG_INTF_CLK clock */ 965 /* RTU1_CORE_MON1_CLK */ {0U, CLOCK_IP_CMU, 0U, 0U, 0U, 0U, 0U, 0U, CLOCK_IP_RTU1_CMU_FC_0_INSTANCE}, /* RTU1_CORE_MON1_CLK */ 966 /* RTU1_CORE_MON2_CLK */ {0U, CLOCK_IP_CMU, 0U, 0U, 0U, 0U, 0U, 0U, CLOCK_IP_RTU1_CMU_FC_3_INSTANCE}, /* RTU1_CORE_MON2_CLK */ 967 /* RTU1_CORE_DIV2_MON1_CLK */ {0U, CLOCK_IP_CMU, 0U, 0U, 0U, 0U, 0U, 0U, CLOCK_IP_RTU1_CMU_FC_1_INSTANCE}, /* RTU1_CORE_DIV2_MON1_CLK */ 968 /* RTU1_CORE_DIV2_MON2_CLK */ {0U, CLOCK_IP_CMU, 0U, 0U, 0U, 0U, 0U, 0U, CLOCK_IP_RTU1_CMU_FC_2_INSTANCE}, /* RTU1_CORE_DIV2_MON2_CLK */ 969 /* RTU1_CORE_DIV2_MON3_CLK */ {0U, CLOCK_IP_CMU, 0U, 0U, 0U, 0U, 0U, 0U, CLOCK_IP_RTU1_CMU_FC_4_INSTANCE}, /* RTU1_CORE_DIV2_MON3_CLK */ 970 /* RTU1_REG_INTF_CLK clock */ {CLOCK_IP_CGM8_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_RTU1_REG_INTF_EXTENSION, 0U, CLOCK_IP_SEL_1_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* RTU1_REG_INTF_CLK clock */ 971 /* P4_SDHC_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P4_SDHC_EXTENSION, 0U, CLOCK_IP_SEL_9_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* P4_SDHC_CLK clock */ 972 /* RXLUT_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_33_BIT0_INDEX, 0U, 0U}, /* RXLUT_CLK clock */ 973 /* SDHC0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P4_GROUP_9_BIT0_INDEX, 0U, 0U}, /* SDHC0_CLK clock */ 974 /* SINC_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P0_GROUP_24_BIT0_INDEX, 0U, 0U}, /* SINC_CLK clock */ 975 /* SIPI0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P1_GROUP_8_BIT0_INDEX, 0U, 0U}, /* SIPI0_CLK clock */ 976 /* SIPI1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P1_GROUP_9_BIT0_INDEX, 0U, 0U}, /* SIPI1_CLK clock */ 977 /* SIUL2_0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P0_GROUP_21_BIT0_INDEX, 0U, 0U}, /* SIUL2_0_CLK clock */ 978 /* SIUL2_1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P1_GROUP_14_BIT0_INDEX, 0U, 0U}, /* SIUL2_1_CLK clock */ 979 /* SIUL2_4_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P4_GROUP_13_BIT0_INDEX, 0U, 0U}, /* SIUL2_4_CLK clock */ 980 /* SIUL2_5_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P5_GROUP_6_BIT0_INDEX, 0U, 0U}, /* SIUL2_5_CLK clock */ 981 /* P0_DSPI_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX, CLOCK_IP_P0_DSPI_EXTENSION, 0U, CLOCK_IP_SEL_5_INDEX, 0U, 0U, 0U, 0U}, /* P0_DSPI_CLK clock */ 982 /* SPI0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P0_GROUP_1_BIT0_INDEX, 0U, 0U}, /* SPI0_CLK clock */ 983 /* SPI1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P0_GROUP_7_BIT0_INDEX, 0U, 0U}, /* SPI1_CLK clock */ 984 /* P1_DSPI_CLK clock */ {CLOCK_IP_CGM1_INSTANCE, CLOCK_IP_HWMUX, CLOCK_IP_P1_DSPI_EXTENSION, 0U, CLOCK_IP_SEL_2_INDEX, 0U, 0U, 0U, 0U}, /* P1_DSPI_CLK clock */ 985 /* SPI2_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P1_GROUP_2_BIT0_INDEX, 0U, 0U}, /* SPI2_CLK clock */ 986 /* SPI3_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P1_GROUP_3_BIT0_INDEX, 0U, 0U}, /* SPI3_CLK clock */ 987 /* SPI4_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P1_GROUP_4_BIT0_INDEX, 0U, 0U}, /* SPI4_CLK clock */ 988 /* P4_DSPI_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX, CLOCK_IP_P4_DSPI_EXTENSION, 0U, CLOCK_IP_SEL_4_INDEX, 0U, 0U, 0U, 0U}, /* P4_DSPI_CLK clock */ 989 /* SPI5_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P4_GROUP_3_BIT0_INDEX, 0U, 0U}, /* SPI5_CLK clock */ 990 /* SPI6_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P4_GROUP_4_BIT0_INDEX, 0U, 0U}, /* SPI6_CLK clock */ 991 /* SPI7_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P4_GROUP_5_BIT0_INDEX, 0U, 0U}, /* SPI7_CLK clock */ 992 /* P5_DSPI_CLK clock */ {CLOCK_IP_CGM5_INSTANCE, CLOCK_IP_HWMUX, CLOCK_IP_P5_DSPI_EXTENSION, 0U, CLOCK_IP_SEL_3_INDEX, 0U, 0U, 0U, 0U}, /* P5_DSPI_CLK clock */ 993 /* SPI8_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P5_GROUP_1_BIT0_INDEX, 0U, 0U}, /* SPI8_CLK clock */ 994 /* SPI9_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P5_GROUP_2_BIT0_INDEX, 0U, 0U}, /* SPI9_CLK clock */ 995 /* SRX0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P1_GROUP_10_BIT0_INDEX, 0U, 0U}, /* SRX0_CLK clock */ 996 /* SRX1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P4_GROUP_10_BIT0_INDEX, 0U, 0U}, /* SRX1_CLK clock */ 997 /* CORE_PLL_REFCLKOUT clock */ {0U, CLOCK_IP_NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* CORE_PLL_REFCLKOUT clock */ 998 /* CORE_PLL_FBCLKOUT clock */ {0U, CLOCK_IP_NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* CORE_PLL_FBCLKOUT clock */ 999 /* PERIPH_PLL_REFCLKOUT clock */ {0U, CLOCK_IP_NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* PERIPH_PLL_REFCLKOUT clock */ 1000 /* PERIPH_PLL_FBCLKOUT clock */ {0U, CLOCK_IP_NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* PERIPH_PLL_FBCLKOUT clock */ 1001 }; 1002 1003 1004 /*! 1005 * @brief Converts a clock name to a selector entry clkout hardware value 1006 */ 1007 const uint8 Clock_Ip_au8SoftwareMuxResetValue[CLOCK_IP_NAMES_NO] = { 1008 0U, /*!< CLOCK_IS_OFF */ 1009 0U, /*!< FIRC_CLK */ 1010 0U, /*!< FXOSC_CLK */ 1011 0U, /*!< SIRC_CLK */ 1012 #if defined(CLOCK_IP_HAS_FIRC_AE_CLK) 1013 0U, /*!< FIRC_AE_CLK */ 1014 #endif 1015 0U, /*!< COREPLL_CLK */ 1016 0U, /*!< PERIPHPLL_CLK */ 1017 0U, /*!< DDRPLL_CLK */ 1018 0U, /*!< LFAST0_PLL_CLK */ 1019 0U, /*!< LFAST1_PLL_CLK */ 1020 0U, /*!< COREPLL_PHI0_CLK */ 1021 0U, /*!< COREPLL_DFS0_CLK */ 1022 0U, /*!< COREPLL_DFS1_CLK */ 1023 0U, /*!< COREPLL_DFS2_CLK */ 1024 0U, /*!< COREPLL_DFS3_CLK */ 1025 0U, /*!< COREPLL_DFS4_CLK */ 1026 0U, /*!< COREPLL_DFS5_CLK */ 1027 0U, /*!< PERIPHPLL_PHI0_CLK */ 1028 0U, /*!< PERIPHPLL_PHI1_CLK */ 1029 0U, /*!< PERIPHPLL_PHI2_CLK */ 1030 0U, /*!< PERIPHPLL_PHI3_CLK */ 1031 0U, /*!< PERIPHPLL_PHI4_CLK */ 1032 0U, /*!< PERIPHPLL_PHI5_CLK */ 1033 0U, /*!< PERIPHPLL_PHI6_CLK */ 1034 0U, /*!< PERIPHPLL_DFS0_CLK */ 1035 0U, /*!< PERIPHPLL_DFS1_CLK */ 1036 0U, /*!< PERIPHPLL_DFS2_CLK */ 1037 0U, /*!< PERIPHPLL_DFS3_CLK */ 1038 0U, /*!< PERIPHPLL_DFS4_CLK */ 1039 0U, /*!< PERIPHPLL_DFS5_CLK */ 1040 0U, /*!< DDRPLL_PHI0_CLK */ 1041 0U, /*!< LFAST0_PLL_PH0_CLK */ 1042 0U, /*!< LFAST1_PLL_PH0_CLK */ 1043 0U, /*!< ETH_RGMII_REF_CLK */ 1044 0U, /*!< TMR_1588_CLK */ 1045 0U, /*!< ETH0_EXT_RX_CLK */ 1046 0U, /*!< ETH0_EXT_TX_CLK */ 1047 0U, /*!< ETH1_EXT_RX_CLK */ 1048 0U, /*!< ETH1_EXT_TX_CLK */ 1049 0U, /*!< LFAST0_EXT_REF_CLK */ 1050 0U, /*!< LFAST1_EXT_REF_CLK */ 1051 0U, /*!< DDR_CLK */ 1052 0U, /*!< P0_SYS_CLK */ 1053 0U, /*!< P1_SYS_CLK */ 1054 0U, /*!< P1_SYS_DIV2_CLK */ 1055 0U, /*!< P1_SYS_DIV4_CLK */ 1056 0U, /*!< P2_SYS_CLK */ 1057 0U, /*!< CORE_M33_CLK */ 1058 0U, /*!< P2_SYS_DIV2_CLK */ 1059 0U, /*!< P2_SYS_DIV4_CLK */ 1060 0U, /*!< P3_SYS_CLK */ 1061 0U, /*!< CE_SYS_DIV2_CLK */ 1062 0U, /*!< CE_SYS_DIV4_CLK */ 1063 0U, /*!< P3_SYS_DIV2_NOC_CLK */ 1064 0U, /*!< P3_SYS_DIV4_CLK */ 1065 0U, /*!< P4_SYS_CLK */ 1066 0U, /*!< P4_SYS_DIV2_CLK */ 1067 0U, /*!< HSE_SYS_DIV2_CLK */ 1068 0U, /*!< P5_SYS_CLK */ 1069 0U, /*!< P5_SYS_DIV2_CLK */ 1070 0U, /*!< P5_SYS_DIV4_CLK */ 1071 0U, /*!< P2_MATH_CLK */ 1072 0U, /*!< P2_MATH_DIV3_CLK */ 1073 0U, /*!< GLB_LBIST_CLK */ 1074 0U, /*!< RTU0_CORE_CLK */ 1075 0U, /*!< RTU0_CORE_DIV2_CLK */ 1076 0U, /*!< RTU1_CORE_CLK */ 1077 0U, /*!< RTU1_CORE_DIV2_CLK */ 1078 0U, /*!< P0_PSI5_S_UTIL_CLK */ 1079 0U, /*!< P4_PSI5_S_UTIL_CLK */ 1080 #if defined(CLOCK_IP_HAS_SYSTEM_DRUN_CLK) 1081 0U, /*!< SYSTEM_DRUN_CLK */ 1082 #endif 1083 #if defined(CLOCK_IP_HAS_SYSTEM_CLK) 1084 0U, /*!< SYSTEM_CLK */ 1085 #endif 1086 #if defined(CLOCK_IP_HAS_SYSTEM_DIV2_CLK) 1087 0U, /*!< SYSTEM_DIV2_CLK */ 1088 #endif 1089 #if defined(CLOCK_IP_HAS_SYSTEM_DIV4_MON1_CLK) 1090 0U, /*!< SYSTEM_DIV4_MON1_CLK */ 1091 #endif 1092 #if defined(CLOCK_IP_HAS_SYSTEM_DIV4_MON2_CLK) 1093 0U, /*!< SYSTEM_DIV4_MON2_CLK */ 1094 #endif 1095 0U, /*!< THE_LAST_PRODUCER_CLK */ 1096 0U, /*!< ADC0_CLK */ 1097 0U, /*!< ADC1_CLK */ 1098 0U, /*!< CE_EDMA_CLK */ 1099 0U, /*!< CE_PIT0_CLK */ 1100 0U, /*!< CE_PIT1_CLK */ 1101 0U, /*!< CE_PIT2_CLK */ 1102 0U, /*!< CE_PIT3_CLK */ 1103 0U, /*!< CE_PIT4_CLK */ 1104 0U, /*!< CE_PIT5_CLK */ 1105 0U, /*!< CLKOUT0_CLK */ 1106 0U, /*!< CLKOUT1_CLK */ 1107 0U, /*!< CLKOUT2_CLK */ 1108 0U, /*!< CLKOUT3_CLK */ 1109 0U, /*!< CLKOUT4_CLK */ 1110 0U, /*!< CTU_CLK */ 1111 0U, /*!< DMACRC0_CLK */ 1112 0U, /*!< DMACRC1_CLK */ 1113 0U, /*!< DMACRC4_CLK */ 1114 0U, /*!< DMACRC5_CLK */ 1115 0U, /*!< DMAMUX0_CLK */ 1116 0U, /*!< DMAMUX1_CLK */ 1117 0U, /*!< DMAMUX4_CLK */ 1118 0U, /*!< DMAMUX5_CLK */ 1119 0U, /*!< EDMA0_CLK */ 1120 0U, /*!< EDMA1_CLK */ 1121 0U, /*!< EDMA3_CLK */ 1122 0U, /*!< EDMA4_CLK */ 1123 0U, /*!< EDMA5_CLK */ 1124 0U, /*!< ETH0_TX_MII_CLK */ 1125 0U, /*!< ENET0_CLK */ 1126 0U, /*!< P3_CAN_PE_CLK */ 1127 0U, /*!< FLEXCAN0_CLK */ 1128 0U, /*!< FLEXCAN1_CLK */ 1129 0U, /*!< FLEXCAN2_CLK */ 1130 0U, /*!< FLEXCAN3_CLK */ 1131 0U, /*!< FLEXCAN4_CLK */ 1132 0U, /*!< FLEXCAN5_CLK */ 1133 0U, /*!< FLEXCAN6_CLK */ 1134 0U, /*!< FLEXCAN7_CLK */ 1135 0U, /*!< FLEXCAN8_CLK */ 1136 0U, /*!< FLEXCAN9_CLK */ 1137 0U, /*!< FLEXCAN10_CLK */ 1138 0U, /*!< FLEXCAN11_CLK */ 1139 0U, /*!< FLEXCAN12_CLK */ 1140 0U, /*!< FLEXCAN13_CLK */ 1141 0U, /*!< FLEXCAN14_CLK */ 1142 0U, /*!< FLEXCAN15_CLK */ 1143 0U, /*!< FLEXCAN16_CLK */ 1144 0U, /*!< FLEXCAN17_CLK */ 1145 0U, /*!< FLEXCAN18_CLK */ 1146 0U, /*!< FLEXCAN19_CLK */ 1147 0U, /*!< FLEXCAN20_CLK */ 1148 0U, /*!< FLEXCAN21_CLK */ 1149 0U, /*!< FLEXCAN22_CLK */ 1150 0U, /*!< FLEXCAN23_CLK */ 1151 0U, /*!< P0_FR_PE_CLK */ 1152 0U, /*!< FRAY0_CLK */ 1153 0U, /*!< FRAY1_CLK */ 1154 0U, /*!< GTM_CLK */ 1155 0U, /*!< IIIC0_CLK */ 1156 0U, /*!< IIIC1_CLK */ 1157 0U, /*!< IIIC2_CLK */ 1158 0U, /*!< P0_LIN_BAUD_CLK */ 1159 0U, /*!< LIN0_CLK */ 1160 0U, /*!< LIN1_CLK */ 1161 0U, /*!< LIN2_CLK */ 1162 0U, /*!< P1_LIN_BAUD_CLK */ 1163 0U, /*!< LIN3_CLK */ 1164 0U, /*!< LIN4_CLK */ 1165 0U, /*!< LIN5_CLK */ 1166 0U, /*!< P4_LIN_BAUD_CLK */ 1167 0U, /*!< LIN6_CLK */ 1168 0U, /*!< LIN7_CLK */ 1169 0U, /*!< LIN8_CLK */ 1170 0U, /*!< P5_LIN_BAUD_CLK */ 1171 0U, /*!< LIN9_CLK */ 1172 0U, /*!< LIN10_CLK */ 1173 0U, /*!< LIN11_CLK */ 1174 0U, /*!< MSCDSPI_CLK */ 1175 0U, /*!< MSCLIN_CLK */ 1176 0U, /*!< NANO_CLK */ 1177 0U, /*!< P0_CLKOUT_SRC_CLK */ 1178 0U, /*!< P0_CTU_PER_CLK */ 1179 0U, /*!< P0_DSPI_MSC_CLK */ 1180 0U, /*!< P0_EMIOS_LCU_CLK */ 1181 0U, /*!< P0_GTM_CLK */ 1182 0U, /*!< P0_GTM_NOC_CLK */ 1183 0U, /*!< P0_GTM_TS_CLK */ 1184 0U, /*!< P0_LIN_CLK */ 1185 0U, /*!< P0_NANO_CLK */ 1186 0U, /*!< P0_PSI5_125K_CLK */ 1187 0U, /*!< P0_PSI5_189K_CLK */ 1188 0U, /*!< P0_PSI5_S_BAUD_CLK */ 1189 0U, /*!< P0_PSI5_S_CORE_CLK */ 1190 0U, /*!< P0_PSI5_S_TRIG0_CLK */ 1191 0U, /*!< P0_PSI5_S_TRIG1_CLK */ 1192 0U, /*!< P0_PSI5_S_TRIG2_CLK */ 1193 0U, /*!< P0_PSI5_S_TRIG3_CLK */ 1194 0U, /*!< P0_PSI5_S_UART_CLK */ 1195 0U, /*!< P0_PSI5_S_WDOG0_CLK */ 1196 0U, /*!< P0_PSI5_S_WDOG1_CLK */ 1197 0U, /*!< P0_PSI5_S_WDOG2_CLK */ 1198 0U, /*!< P0_PSI5_S_WDOG3_CLK */ 1199 0U, /*!< P0_REG_INTF_2X_CLK */ 1200 0U, /*!< P0_REG_INTF_CLK */ 1201 0U, /*!< P1_CLKOUT_SRC_CLK */ 1202 0U, /*!< P1_DSPI60_CLK */ 1203 0U, /*!< ETH_TS_CLK */ 1204 0U, /*!< ETH_TS_DIV4_CLK */ 1205 0U, /*!< ETH0_REF_RMII_CLK */ 1206 0U, /*!< ETH0_RX_MII_CLK */ 1207 0U, /*!< ETH0_RX_RGMII_CLK */ 1208 0U, /*!< ETH0_TX_RGMII_CLK */ 1209 0U, /*!< ETH0_PS_TX_CLK */ 1210 0U, /*!< ETH1_REF_RMII_CLK */ 1211 0U, /*!< ETH1_RX_MII_CLK */ 1212 0U, /*!< ETH1_RX_RGMII_CLK */ 1213 0U, /*!< ETH1_TX_MII_CLK */ 1214 0U, /*!< ETH1_TX_RGMII_CLK */ 1215 0U, /*!< ETH1_PS_TX_CLK */ 1216 0U, /*!< P1_LFAST0_REF_CLK */ 1217 0U, /*!< P1_LFAST1_REF_CLK */ 1218 0U, /*!< P1_NETC_AXI_CLK */ 1219 0U, /*!< P1_LIN_CLK */ 1220 0U, /*!< P1_REG_INTF_CLK */ 1221 0U, /*!< P2_DBG_ATB_CLK */ 1222 0U, /*!< P2_REG_INTF_CLK */ 1223 0U, /*!< P3_AES_CLK */ 1224 0U, /*!< P3_CLKOUT_SRC_CLK */ 1225 0U, /*!< P3_DBG_TS_CLK */ 1226 0U, /*!< P3_REG_INTF_CLK */ 1227 0U, /*!< P3_SYS_MON1_CLK */ 1228 0U, /*!< P3_SYS_MON2_CLK */ 1229 0U, /*!< P3_SYS_MON3_CLK */ 1230 0U, /*!< P4_CLKOUT_SRC_CLK */ 1231 0U, /*!< P4_DSPI60_CLK */ 1232 0U, /*!< P4_EMIOS_LCU_CLK */ 1233 0U, /*!< P4_LIN_CLK */ 1234 0U, /*!< P4_PSI5_125K_CLK */ 1235 0U, /*!< P4_PSI5_189K_CLK */ 1236 0U, /*!< P4_PSI5_S_BAUD_CLK */ 1237 0U, /*!< P4_PSI5_S_CORE_CLK */ 1238 0U, /*!< P4_PSI5_S_TRIG0_CLK */ 1239 0U, /*!< P4_PSI5_S_TRIG1_CLK */ 1240 0U, /*!< P4_PSI5_S_TRIG2_CLK */ 1241 0U, /*!< P4_PSI5_S_TRIG3_CLK */ 1242 0U, /*!< P4_PSI5_S_UART_CLK */ 1243 0U, /*!< P4_PSI5_S_WDOG0_CLK */ 1244 0U, /*!< P4_PSI5_S_WDOG1_CLK */ 1245 0U, /*!< P4_PSI5_S_WDOG2_CLK */ 1246 0U, /*!< P4_PSI5_S_WDOG3_CLK */ 1247 0U, /*!< P4_QSPI0_2X_CLK */ 1248 0U, /*!< P4_QSPI0_1X_CLK */ 1249 0U, /*!< P4_QSPI1_2X_CLK */ 1250 0U, /*!< P4_QSPI1_1X_CLK */ 1251 0U, /*!< P4_REG_INTF_2X_CLK */ 1252 0U, /*!< P4_REG_INTF_CLK */ 1253 0U, /*!< P4_SDHC_IP_CLK */ 1254 0U, /*!< P4_SDHC_IP_DIV2_CLK */ 1255 0U, /*!< P5_DIPORT_CLK */ 1256 0U, /*!< P5_AE_CLK */ 1257 0U, /*!< P5_CANXL_PE_CLK */ 1258 0U, /*!< P5_CANXL_CHI_CLK */ 1259 0U, /*!< P5_CLKOUT_SRC_CLK */ 1260 0U, /*!< P5_LIN_CLK */ 1261 0U, /*!< P5_REG_INTF_CLK */ 1262 0U, /*!< P6_REG_INTF_CLK */ 1263 0U, /*!< PIT0_CLK */ 1264 0U, /*!< PIT1_CLK */ 1265 0U, /*!< PIT4_CLK */ 1266 0U, /*!< PIT5_CLK */ 1267 0U, /*!< P0_PSI5_1US_CLK */ 1268 0U, /*!< PSI5_0_CLK */ 1269 0U, /*!< P4_PSI5_1US_CLK */ 1270 0U, /*!< PSI5_1_CLK */ 1271 0U, /*!< PSI5S_0_CLK */ 1272 0U, /*!< PSI5S_1_CLK */ 1273 0U, /*!< QSPI0_CLK */ 1274 0U, /*!< QSPI1_CLK */ 1275 0U, /*!< RTU0_CORE_MON1_CLK */ 1276 0U, /*!< RTU0_CORE_MON2_CLK */ 1277 0U, /*!< RTU0_CORE_DIV2_MON1_CLK */ 1278 0U, /*!< RTU0_CORE_DIV2_MON2_CLK */ 1279 0U, /*!< RTU0_CORE_DIV2_MON3_CLK */ 1280 0U, /*!< RTU0_REG_INTF_CLK */ 1281 0U, /*!< RTU1_CORE_MON1_CLK */ 1282 0U, /*!< RTU1_CORE_MON2_CLK */ 1283 0U, /*!< RTU1_CORE_DIV2_MON1_CLK */ 1284 0U, /*!< RTU1_CORE_DIV2_MON2_CLK */ 1285 0U, /*!< RTU1_CORE_DIV2_MON3_CLK */ 1286 0U, /*!< RTU1_REG_INTF_CLK */ 1287 0U, /*!< P4_SDHC_CLK */ 1288 0U, /*!< RXLUT_CLK */ 1289 0U, /*!< SDHC0_CLK */ 1290 0U, /*!< SINC_CLK */ 1291 0U, /*!< SIPI0_CLK */ 1292 0U, /*!< SIPI1_CLK */ 1293 0U, /*!< SIUL2_0_CLK */ 1294 0U, /*!< SIUL2_1_CLK */ 1295 0U, /*!< SIUL2_4_CLK */ 1296 0U, /*!< SIUL2_5_CLK */ 1297 0U, /*!< P0_DSPI_CLK */ 1298 0U, /*!< SPI0_CLK */ 1299 0U, /*!< SPI1_CLK */ 1300 0U, /*!< P1_DSPI_CLK */ 1301 0U, /*!< SPI2_CLK */ 1302 0U, /*!< SPI3_CLK */ 1303 0U, /*!< SPI4_CLK */ 1304 0U, /*!< P4_DSPI_CLK */ 1305 0U, /*!< SPI5_CLK */ 1306 0U, /*!< SPI6_CLK */ 1307 0U, /*!< SPI7_CLK */ 1308 0U, /*!< P5_DSPI_CLK */ 1309 0U, /*!< SPI8_CLK */ 1310 0U, /*!< SPI9_CLK */ 1311 0U, /*!< SRX0_CLK */ 1312 0U, /*!< SRX1_CLK */ 1313 0U, /*!< CORE_PLL_REFCLKOUT clock */ 1314 0U, /*!< CORE_PLL_FBCLKOUT clock */ 1315 0U, /*!< PERIPH_PLL_REFCLKOUT clock */ 1316 0U, /*!< PERIPH_PLL_FBCLKOUT clock */ 1317 }; 1318 1319 1320 /* Clock stop constant section data */ 1321 #define MCU_STOP_SEC_CONST_8 1322 #include "Mcu_MemMap.h" 1323 1324 1325 1326 1327 /* Clock start constant section data */ 1328 #define MCU_START_SEC_CONST_16 1329 #include "Mcu_MemMap.h" 1330 /*! 1331 * @brief Converts a clock name to a selector entry hardware value 1332 */ 1333 const uint16 Clock_Ip_au16SelectorEntryHardwareValue[CLOCK_IP_NAMES_NO] = { 1334 0U, /*!< CLOCK_IS_OFF */ 1335 0U, /*!< FIRC_CLK */ 1336 2U, /*!< FXOSC_CLK */ 1337 1U, /*!< SIRC_CLK */ 1338 #if defined(CLOCK_IP_HAS_FIRC_AE_CLK) 1339 0U, /*!< FIRC_AE_CLK */ 1340 #endif 1341 0U, /*!< COREPLL_CLK */ 1342 0U, /*!< PERIPHPLL_CLK */ 1343 0U, /*!< DDRPLL_CLK */ 1344 0U, /*!< LFAST0_PLL_CLK */ 1345 0U, /*!< LFAST1_PLL_CLK */ 1346 10U, /*!< CORE_PLL_PHI0_CLK */ 1347 11U, /*!< CORE_PLL_DFS0_CLK */ 1348 12U, /*!< CORE_PLL_DFS1_CLK */ 1349 13U, /*!< CORE_PLL_DFS2_CLK */ 1350 14U, /*!< CORE_PLL_DFS3_CLK */ 1351 15U, /*!< CORE_PLL_DFS4_CLK */ 1352 16U, /*!< CORE_PLL_DFS5_CLK */ 1353 20U, /*!< PERIPH_PLL_PHI0_CLK */ 1354 21U, /*!< PERIPH_PLL_PHI1_CLK */ 1355 22U, /*!< PERIPH_PLL_PHI2_CLK */ 1356 23U, /*!< PERIPH_PLL_PHI3_CLK */ 1357 24U, /*!< PERIPH_PLL_PHI4_CLK */ 1358 25U, /*!< PERIPH_PLL_PHI5_CLK */ 1359 26U, /*!< PERIPH_PLL_PHI6_CLK */ 1360 30U, /*!< PERIPH_PLL_DFS0_CLK */ 1361 31U, /*!< PERIPH_PLL_DFS1_CLK */ 1362 32U, /*!< PERIPH_PLL_DFS2_CLK */ 1363 33U, /*!< PERIPH_PLL_DFS3_CLK */ 1364 34U, /*!< PERIPH_PLL_DFS4_CLK */ 1365 35U, /*!< PERIPH_PLL_DFS5_CLK */ 1366 40U, /*!< DDR_PLL_PHI0_CLK */ 1367 0U, /*!< LFAST0_PLL_PH0_CLK */ 1368 0U, /*!< LFAST1_PLL_PH0_CLK */ 1369 47U, /*!< ENET_EXT_REF_CLK */ 1370 48U, /*!< ENET_EXT_TS_CLK */ 1371 49U, /*!< ENET0_EXT_RX_CLK */ 1372 50U, /*!< ENET0_EXT_TX_CLK */ 1373 51U, /*!< ENET1_EXT_RX_CLK */ 1374 52U, /*!< ENET1_EXT_TX_CLK */ 1375 59U, /*!< LFAST0_EXT_TX_CLK */ 1376 60U, /*!< LFAST1_EXT_TX_CLK */ 1377 0U, /*!< DDR_CLK */ 1378 0U, /*!< P0_SYS_CLK */ 1379 0U, /*!< P1_SYS_CLK */ 1380 0U, /*!< P1_SYS_DIV2_CLK */ 1381 0U, /*!< P1_SYS_DIV4_CLK */ 1382 0U, /*!< P2_SYS_CLK */ 1383 0U, /*!< CORE_M33_CLK */ 1384 0U, /*!< P2_SYS_DIV2_CLK */ 1385 0U, /*!< P2_SYS_DIV4_CLK */ 1386 0U, /*!< P3_SYS_CLK */ 1387 0U, /*!< CE_SYS_DIV2_CLK */ 1388 0U, /*!< CE_SYS_DIV4_CLK */ 1389 0U, /*!< P3_SYS_DIV2_NOC_CLK */ 1390 0U, /*!< P3_SYS_DIV4_CLK */ 1391 0U, /*!< P4_SYS_CLK */ 1392 0U, /*!< P4_SYS_DIV2_CLK */ 1393 0U, /*!< HSE_SYS_DIV2_CLK */ 1394 0U, /*!< P5_SYS_CLK */ 1395 0U, /*!< P5_SYS_DIV2_CLK */ 1396 0U, /*!< P5_SYS_DIV4_CLK */ 1397 0U, /*!< P2_MATH_CLK */ 1398 0U, /*!< P2_MATH_DIV3_CLK */ 1399 0U, /*!< GLB_LBIST_CLK */ 1400 0U, /*!< RTU0_CORE_CLK */ 1401 0U, /*!< RTU0_CORE_DIV2_CLK */ 1402 0U, /*!< RTU1_CORE_CLK */ 1403 0U, /*!< RTU1_CORE_DIV2_CLK */ 1404 62U, /*!< P0_PSI5_S_UTIL_CLK */ 1405 62U, /*!< P4_PSI5_S_UTIL_CLK */ 1406 #if defined(CLOCK_IP_HAS_SYSTEM_DRUN_CLK) 1407 0U, /*!< SYSTEM_DRUN_CLK */ 1408 #endif 1409 #if defined(CLOCK_IP_HAS_SYSTEM_RUN0_CLK) 1410 0U, /*!< SYSTEM_RUN0_CLK */ 1411 #endif 1412 #if defined(CLOCK_IP_HAS_SYSTEM_SAFE_CLK) 1413 0U, /*!< SYSTEM_SAFE_CLK */ 1414 #endif 1415 #if defined(CLOCK_IP_HAS_SYSTEM_CLK) 1416 0U, /*!< SYSTEM_CLK */ 1417 #endif 1418 #if defined(CLOCK_IP_HAS_SYSTEM_DIV2_CLK) 1419 0U, /*!< SYSTEM_DIV2_CL */ 1420 #endif 1421 #if defined(CLOCK_IP_HAS_SYSTEM_DIV4_MON1_CLK) 1422 0U, /*!< SYSTEM_DIV4_MON1_CLK */ 1423 #endif 1424 #if defined(CLOCK_IP_HAS_SYSTEM_DIV4_MON2_CLK) 1425 0U, /*!< SYSTEM_DIV4_MON2_CLK */ 1426 #endif 1427 0U, /*!< THE_LAST_PRODUCER_CLK */ 1428 0U, /*!< ADC0_CLK clock */ 1429 0U, /*!< ADC1_CLK clock */ 1430 0U, /*!< CE_EDMA_CLK clock */ 1431 0U, /*!< CE_PIT0_CLK clock */ 1432 0U, /*!< CE_PIT1_CLK clock */ 1433 0U, /*!< CE_PIT2_CLK clock */ 1434 0U, /*!< CE_PIT3_CLK clock */ 1435 0U, /*!< CE_PIT4_CLK clock */ 1436 0U, /*!< CE_PIT5_CLK clock */ 1437 0U, /*!< CLKOUT0_CLK clock */ 1438 0U, /*!< CLKOUT1_CLK clock */ 1439 0U, /*!< CLKOUT2_CLK clock */ 1440 0U, /*!< CLKOUT3_CLK clock */ 1441 0U, /*!< CLKOUT4_CLK clock */ 1442 0U, /*!< CTU_CLK clock */ 1443 0U, /*!< DMACRC0_CLK clock */ 1444 0U, /*!< DMACRC1_CLK clock */ 1445 0U, /*!< DMACRC4_CLK clock */ 1446 0U, /*!< DMACRC5_CLK clock */ 1447 0U, /*!< DMAMUX0_CLK clock */ 1448 0U, /*!< DMAMUX1_CLK clock */ 1449 0U, /*!< DMAMUX4_CLK clock */ 1450 0U, /*!< DMAMUX5_CLK clock */ 1451 0U, /*!< EDMA0_CLK clock */ 1452 0U, /*!< EDMA1_CLK clock */ 1453 0U, /*!< EDMA3_CLK clock */ 1454 0U, /*!< EDMA4_CLK clock */ 1455 0U, /*!< EDMA5_CLK clock */ 1456 0U, /*!< ETH0_TX_MII_CLK clock */ 1457 0U, /*!< ENET0_CLK clock */ 1458 0U, /*!< P3_CAN_PE_CLK clock */ 1459 0U, /*!< FLEXCAN0_CLK clock */ 1460 0U, /*!< FLEXCAN1_CLK clock */ 1461 0U, /*!< FLEXCAN2_CLK clock */ 1462 0U, /*!< FLEXCAN3_CLK clock */ 1463 0U, /*!< FLEXCAN4_CLK clock */ 1464 0U, /*!< FLEXCAN5_CLK clock */ 1465 0U, /*!< FLEXCAN6_CLK clock */ 1466 0U, /*!< FLEXCAN7_CLK clock */ 1467 0U, /*!< FLEXCAN8_CLK clock */ 1468 0U, /*!< FLEXCAN9_CLK clock */ 1469 0U, /*!< FLEXCAN10_CLK clock */ 1470 0U, /*!< FLEXCAN11_CLK clock */ 1471 0U, /*!< FLEXCAN12_CLK clock */ 1472 0U, /*!< FLEXCAN13_CLK clock */ 1473 0U, /*!< FLEXCAN14_CLK clock */ 1474 0U, /*!< FLEXCAN15_CLK clock */ 1475 0U, /*!< FLEXCAN16_CLK clock */ 1476 0U, /*!< FLEXCAN17_CLK clock */ 1477 0U, /*!< FLEXCAN18_CLK clock */ 1478 0U, /*!< FLEXCAN19_CLK clock */ 1479 0U, /*!< FLEXCAN20_CLK clock */ 1480 0U, /*!< FLEXCAN21_CLK clock */ 1481 0U, /*!< FLEXCAN22_CLK clock */ 1482 0U, /*!< FLEXCAN23_CLK clock */ 1483 0U, /*!< P0_FR_PE_CLK clock */ 1484 0U, /*!< FRAY0_CLK clock */ 1485 0U, /*!< FRAY1_CLK clock */ 1486 0U, /*!< GTM_CLK clock */ 1487 0U, /*!< IIIC0_CLK clock */ 1488 0U, /*!< IIIC1_CLK clock */ 1489 0U, /*!< IIIC2_CLK clock */ 1490 0U, /*!< P0_LIN_BAUD_CLK clock */ 1491 0U, /*!< LIN0_CLK clock */ 1492 0U, /*!< LIN1_CLK clock */ 1493 0U, /*!< LIN2_CLK clock */ 1494 0U, /*!< P1_LIN_BAUD_CLK clock */ 1495 0U, /*!< LIN3_CLK clock */ 1496 0U, /*!< LIN4_CLK clock */ 1497 0U, /*!< LIN5_CLK clock */ 1498 0U, /*!< P4_LIN_BAUD_CLK clock */ 1499 0U, /*!< LIN6_CLK clock */ 1500 0U, /*!< LIN7_CLK clock */ 1501 0U, /*!< LIN8_CLK clock */ 1502 0U, /*!< P5_LIN_BAUD_CLK clock */ 1503 0U, /*!< LIN9_CLK clock */ 1504 0U, /*!< LIN10_CLK clock */ 1505 0U, /*!< LIN11_CLK clock */ 1506 0U, /*!< MSCDSPI_CLK clock */ 1507 0U, /*!< MSCLIN_CLK clock */ 1508 0U, /*!< NANO_CLK clock */ 1509 61U, /*!< P0_CLKOUT_SRC_CLK clock */ 1510 0U, /*!< P0_CTU_PER_CLK clock */ 1511 0U, /*!< P0_DSPI_MSC_CLK clock */ 1512 0U, /*!< P0_EMIOS_LCU_CLK clock */ 1513 0U, /*!< P0_GTM_CLK clock */ 1514 0U, /*!< P0_GTM_NOC_CLK clock */ 1515 0U, /*!< P0_GTM_TS_CLK clock */ 1516 0U, /*!< P0_LIN_CLK clock */ 1517 0U, /*!< P0_NANO_CLK clock */ 1518 0U, /*!< P0_PSI5_125K_CLK clock */ 1519 0U, /*!< P0_PSI5_189K_CLK clock */ 1520 0U, /*!< P0_PSI5_S_BAUD_CLK clock */ 1521 0U, /*!< P0_PSI5_S_CORE_CLK clock */ 1522 0U, /*!< P0_PSI5_S_TRIG0_CLK clock */ 1523 0U, /*!< P0_PSI5_S_TRIG1_CLK clock */ 1524 0U, /*!< P0_PSI5_S_TRIG2_CLK clock */ 1525 0U, /*!< P0_PSI5_S_TRIG3_CLK clock */ 1526 0U, /*!< P0_PSI5_S_UART_CLK clock */ 1527 0U, /*!< P0_PSI5_S_WDOG0_CLK clock */ 1528 0U, /*!< P0_PSI5_S_WDOG1_CLK clock */ 1529 0U, /*!< P0_PSI5_S_WDOG2_CLK clock */ 1530 0U, /*!< P0_PSI5_S_WDOG3_CLK clock */ 1531 0U, /*!< P0_REG_INTF_2X_CLK clock */ 1532 0U, /*!< P0_REG_INTF_CLK clock */ 1533 61U, /*!< P1_CLKOUT_SRC_CLK clock */ 1534 0U, /*!< P1_DSPI60_CLK clock */ 1535 0U, /*!< ETH_TS_CLK clock */ 1536 0U, /*!< ETH_TS_DIV4_CLK clock */ 1537 0U, /*!< ETH0_REF_RMII_CLK clock */ 1538 0U, /*!< ETH0_RX_MII_CLK clock */ 1539 0U, /*!< ETH0_RX_RGMII_CLK clock */ 1540 0U, /*!< ETH0_TX_RGMII_CLK clock */ 1541 0U, /*!< ETH0_PS_TX_CLK */ 1542 0U, /*!< ETH1_REF_RMII_CLK clock */ 1543 0U, /*!< ETH1_RX_MII_CLK clock */ 1544 0U, /*!< ETH1_RX_RGMII_CLK clock */ 1545 0U, /*!< ETH1_TX_MII_CLK clock */ 1546 0U, /*!< ETH1_TX_RGMII_CLK clock */ 1547 0U, /*!< ETH1_PS_TX_CLK */ 1548 0U, /*!< P1_LFAST0_REF_CLK clock */ 1549 0U, /*!< P1_LFAST1_REF_CLK clock */ 1550 0U, /*!< P1_NETC_AXI_CLK clock */ 1551 0U, /*!< P1_LIN_CLK clock */ 1552 0U, /*!< P1_REG_INTF_CLK clock */ 1553 0U, /*!< P2_DBG_ATB_CLK clock */ 1554 0U, /*!< P2_REG_INTF_CLK clock */ 1555 0U, /*!< P3_AES_CLK clock */ 1556 61U, /*!< P3_CLKOUT_SRC_CLK clock */ 1557 0U, /*!< P3_DBG_TS_CLK clock */ 1558 0U, /*!< P3_REG_INTF_CLK clock */ 1559 0U, /*!< P3_SYS_MON1_CLK clock */ 1560 0U, /*!< P3_SYS_MON2_CLK clock */ 1561 0U, /*!< P3_SYS_MON3_CLK clock */ 1562 61U, /*!< P4_CLKOUT_SRC_CLK clock */ 1563 0U, /*!< P4_DSPI60_CLK clock */ 1564 0U, /*!< P4_EMIOS_LCU_CLK clock */ 1565 0U, /*!< P4_LIN_CLK clock */ 1566 0U, /*!< P4_PSI5_125K_CLK clock */ 1567 0U, /*!< P4_PSI5_189K_CLK clock */ 1568 0U, /*!< P4_PSI5_S_BAUD_CLK clock */ 1569 0U, /*!< P4_PSI5_S_CORE_CLK clock */ 1570 0U, /*!< P4_PSI5_S_TRIG0_CLK clock */ 1571 0U, /*!< P4_PSI5_S_TRIG1_CLK clock */ 1572 0U, /*!< P4_PSI5_S_TRIG2_CLK clock */ 1573 0U, /*!< P4_PSI5_S_TRIG3_CLK clock */ 1574 0U, /*!< P4_PSI5_S_UART_CLK clock */ 1575 0U, /*!< P4_PSI5_S_WDOG0_CLK clock */ 1576 0U, /*!< P4_PSI5_S_WDOG1_CLK clock */ 1577 0U, /*!< P4_PSI5_S_WDOG2_CLK clock */ 1578 0U, /*!< P4_PSI5_S_WDOG3_CLK clock */ 1579 0U, /*!< P4_QSPI0_2X_CLK clock */ 1580 0U, /*!< P4_QSPI0_1X_CLK clock */ 1581 0U, /*!< P4_QSPI1_2X_CLK clock */ 1582 0U, /*!< P4_QSPI1_1X_CLK clock */ 1583 0U, /*!< P4_REG_INTF_2X_CLK clock */ 1584 0U, /*!< P4_REG_INTF_CLK clock */ 1585 0U, /*!< P4_SDHC_IP_CLK clock */ 1586 0U, /*!< P4_SDHC_IP_DIV2_CLK clock */ 1587 0U, /*!< P5_DIPORT_CLK clock */ 1588 0U, /*!< P5_AE_CLK clock */ 1589 0U, /*!< P5_CANXL_PE_CLK clock */ 1590 0U, /*!< P5_CANXL_CHI_CLK clock */ 1591 61U, /*!< P5_CLKOUT_SRC_CLK clock */ 1592 0U, /*!< P5_LIN_CLK clock */ 1593 0U, /*!< P5_REG_INTF_CLK clock */ 1594 0U, /*!< P6_REG_INTF_CLK clock */ 1595 0U, /*!< PIT0_CLK clock */ 1596 0U, /*!< PIT1_CLK clock */ 1597 0U, /*!< PIT4_CLK clock */ 1598 0U, /*!< PIT5_CLK clock */ 1599 0U, /*!< P0_PSI5_1US_CLK clock */ 1600 0U, /*!< PSI5_0_CLK clock */ 1601 0U, /*!< P4_PSI5_1US_CLK clock */ 1602 0U, /*!< PSI5_1_CLK clock */ 1603 0U, /*!< PSI5S_0_CLK clock */ 1604 0U, /*!< PSI5S_1_CLK clock */ 1605 0U, /*!< QSPI0_CLK clock */ 1606 0U, /*!< QSPI1_CLK clock */ 1607 0U, /*!< RTU0_CORE_MON1_CLK */ 1608 0U, /*!< RTU0_CORE_MON2_CLK */ 1609 0U, /*!< RTU0_CORE_DIV2_MON1_CLK */ 1610 0U, /*!< RTU0_CORE_DIV2_MON2_CLK */ 1611 0U, /*!< RTU0_CORE_DIV2_MON3_CLK */ 1612 0U, /*!< RTU0_CORE_DIV2_MON4_CLK */ 1613 0U, /*!< RTU0_REG_INTF_CLK clock */ 1614 0U, /*!< RTU1_CORE_DIV2_MON1_CLK */ 1615 0U, /*!< RTU1_CORE_DIV2_MON2_CLK */ 1616 0U, /*!< RTU1_CORE_DIV2_MON3_CLK */ 1617 0U, /*!< RTU1_CORE_DIV2_MON4_CLK */ 1618 0U, /*!< RTU1_REG_INTF_CLK clock */ 1619 0U, /*!< P4_SDHC_CLK clock */ 1620 0U, /*!< RXLUT_CLK clock */ 1621 0U, /*!< SDHC0_CLK clock */ 1622 0U, /*!< SINC_CLK clock */ 1623 0U, /*!< SIPI0_CLK clock */ 1624 0U, /*!< SIPI1_CLK clock */ 1625 0U, /*!< SIUL2_0_CLK clock */ 1626 0U, /*!< SIUL2_1_CLK clock */ 1627 0U, /*!< SIUL2_4_CLK clock */ 1628 0U, /*!< SIUL2_5_CLK clock */ 1629 0U, /*!< P0_DSPI_CLK clock */ 1630 0U, /*!< SPI0_CLK clock */ 1631 0U, /*!< SPI1_CLK clock */ 1632 0U, /*!< P1_DSPI_CLK clock */ 1633 0U, /*!< SPI2_CLK clock */ 1634 0U, /*!< SPI3_CLK clock */ 1635 0U, /*!< SPI4_CLK clock */ 1636 0U, /*!< P4_DSPI_CLK clock */ 1637 0U, /*!< SPI5_CLK clock */ 1638 0U, /*!< SPI6_CLK clock */ 1639 0U, /*!< SPI7_CLK clock */ 1640 0U, /*!< P5_DSPI_CLK clock */ 1641 0U, /*!< SPI8_CLK clock */ 1642 0U, /*!< SPI9_CLK clock */ 1643 0U, /*!< SRX0_CLK clock */ 1644 0U, /*!< SRX1_CLK clock */ 1645 0U, /*!< CORE_PLL_REFCLKOUT clock */ 1646 0U, /*!< CORE_PLL_FBCLKOUT clock */ 1647 0U, /*!< PERIPH_PLL_REFCLKOUT clock */ 1648 0U, /*!< PERIPH_PLL_FBCLKOUT clock */ 1649 }; 1650 1651 /*! 1652 * @brief Converts a clock name to a selector entry clkout hardware value 1653 */ 1654 const uint16 Clock_Ip_au16SelectorEntryClkoutHardwareValue[CLOCK_IP_NAMES_NO] = { 1655 0U, /*!< CLOCK_IS_OFF */ 1656 1U, /*!< FIRC_CLK */ 1657 2U, /*!< FXOSC_CLK */ 1658 0U, /*!< SIRC_CLK */ 1659 #if defined(CLOCK_IP_HAS_FIRC_AE_CLK) 1660 0U, /*!< FIRC_AE_CLK */ 1661 #endif 1662 0U, /*!< COREPLL_CLK */ 1663 0U, /*!< PERIPHPLL_CLK */ 1664 0U, /*!< DDRPLL_CLK */ 1665 0U, /*!< LFAST0_PLL_CLK */ 1666 0U, /*!< LFAST1_PLL_CLK */ 1667 3U, /*!< COREPLL_PHI0_CLK */ 1668 4U, /*!< COREPLL_DFS0_CLK */ 1669 5U, /*!< COREPLL_DFS1_CLK */ 1670 6U, /*!< COREPLL_DFS2_CLK */ 1671 7U, /*!< COREPLL_DFS3_CLK */ 1672 8U, /*!< COREPLL_DFS4_CLK */ 1673 9U, /*!< COREPLL_DFS5_CLK */ 1674 10U, /*!< PERIPHPLL_PHI0_CLK */ 1675 11U, /*!< PERIPHPLL_PHI1_CLK */ 1676 12U, /*!< PERIPHPLL_PHI2_CLK */ 1677 13U, /*!< PERIPHPLL_PHI3_CLK */ 1678 14U, /*!< PERIPHPLL_PHI4_CLK */ 1679 15U, /*!< PERIPHPLL_PHI5_CLK */ 1680 16U, /*!< PERIPHPLL_PHI6_CLK */ 1681 17U, /*!< PERIPHPLL_DFS0_CLK */ 1682 18U, /*!< PERIPHPLL_DFS1_CLK */ 1683 19U, /*!< PERIPHPLL_DFS2_CLK */ 1684 20U, /*!< PERIPHPLL_DFS3_CLK */ 1685 21U, /*!< PERIPHPLL_DFS4_CLK */ 1686 22U, /*!< PERIPHPLL_DFS5_CLK */ 1687 23U, /*!< DDRPLL_PHI0_CLK */ 1688 0U, /*!< LFAST0_PLL_PH0_CLK */ 1689 1U, /*!< LFAST1_PLL_PH0_CLK */ 1690 0U, /*!< ETH_RGMII_REF_CLK */ 1691 0U, /*!< TMR_1588_CLK */ 1692 0U, /*!< ETH0_EXT_RX_CLK */ 1693 0U, /*!< ETH0_EXT_TX_CLK */ 1694 0U, /*!< ETH1_EXT_RX_CLK */ 1695 0U, /*!< ETH1_EXT_TX_CLK */ 1696 0U, /*!< LFAST0_EXT_REF_CLK */ 1697 0U, /*!< LFAST1_EXT_REF_CLK */ 1698 9U, /*!< DDR_CLK */ 1699 24U, /*!< P0_SYS_CLK */ 1700 2U, /*!< P1_SYS_CLK */ 1701 3U, /*!< P1_SYS_DIV2_CLK */ 1702 4U, /*!< P1_SYS_DIV4_CLK */ 1703 6U, /*!< P2_SYS_CLK */ 1704 0U, /*!< CORE_M33_CLK */ 1705 0U, /*!< P2_SYS_DIV2_CLK */ 1706 0U, /*!< P2_SYS_DIV4_CLK */ 1707 0U, /*!< P3_SYS_CLK */ 1708 1U, /*!< CE_SYS_DIV2_CLK */ 1709 2U, /*!< CE_SYS_DIV4_CLK */ 1710 10U, /*!< P3_SYS_DIV2_NOC_CLK */ 1711 0U, /*!< P3_SYS_DIV4_CLK */ 1712 0U, /*!< P4_SYS_CLK */ 1713 1U, /*!< P4_SYS_DIV2_CLK */ 1714 2U, /*!< HSE_SYS_DIV2_CLK */ 1715 0U, /*!< P5_SYS_CLK */ 1716 1U, /*!< P5_SYS_DIV2_CLK */ 1717 2U, /*!< P5_SYS_DIV4_CLK */ 1718 0U, /*!< P2_MATH_CLK */ 1719 0U, /*!< P2_MATH_DIV3_CLK */ 1720 0U, /*!< GLB_LBIST_CLK */ 1721 0U, /*!< RTU0_CORE_CLK */ 1722 7U, /*!< RTU0_CORE_DIV2_CLK */ 1723 0U, /*!< RTU1_CORE_CLK */ 1724 8U, /*!< RTU1_CORE_DIV2_CLK */ 1725 30U, /*!< P0_PSI5_S_UTIL_CLK */ 1726 8U, /*!< P4_PSI5_S_UTIL_CLK */ 1727 #if defined(CLOCK_IP_HAS_SYSTEM_DRUN_CLK) 1728 0U, /*!< SYSTEM_DRUN_CLK */ 1729 #endif 1730 #if defined(CLOCK_IP_HAS_SYSTEM_CLK) 1731 0U, /*!< SYSTEM_CLK */ 1732 #endif 1733 #if defined(CLOCK_IP_HAS_SYSTEM_DIV2_CLK) 1734 0U, /*!< SYSTEM_DIV2_CLK */ 1735 #endif 1736 #if defined(CLOCK_IP_HAS_SYSTEM_DIV4_MON1_CLK) 1737 0U, /*!< SYSTEM_DIV4_MON1_CLK */ 1738 #endif 1739 #if defined(CLOCK_IP_HAS_SYSTEM_DIV4_MON2_CLK) 1740 0U, /*!< SYSTEM_DIV4_MON2_CLK */ 1741 #endif 1742 0U, /*!< THE_LAST_PRODUCER_CLK */ 1743 0U, /*!< ADC0_CLK */ 1744 0U, /*!< ADC1_CLK */ 1745 0U, /*!< CE_EDMA_CLK */ 1746 0U, /*!< CE_PIT0_CLK */ 1747 0U, /*!< CE_PIT1_CLK */ 1748 0U, /*!< CE_PIT2_CLK */ 1749 0U, /*!< CE_PIT3_CLK */ 1750 0U, /*!< CE_PIT4_CLK */ 1751 0U, /*!< CE_PIT5_CLK */ 1752 0U, /*!< CLKOUT0_CLK */ 1753 0U, /*!< CLKOUT1_CLK */ 1754 0U, /*!< CLKOUT2_CLK */ 1755 0U, /*!< CLKOUT3_CLK */ 1756 0U, /*!< CLKOUT4_CLK */ 1757 0U, /*!< CTU_CLK */ 1758 0U, /*!< DMACRC0_CLK */ 1759 0U, /*!< DMACRC1_CLK */ 1760 0U, /*!< DMACRC4_CLK */ 1761 0U, /*!< DMACRC5_CLK */ 1762 0U, /*!< DMAMUX0_CLK */ 1763 0U, /*!< DMAMUX1_CLK */ 1764 0U, /*!< DMAMUX4_CLK */ 1765 0U, /*!< DMAMUX5_CLK */ 1766 0U, /*!< EDMA0_CLK */ 1767 0U, /*!< EDMA1_CLK */ 1768 0U, /*!< EDMA3_CLK */ 1769 0U, /*!< EDMA4_CLK */ 1770 0U, /*!< EDMA5_CLK */ 1771 12U, /*!< ETH0_TX_MII_CLK */ 1772 0U, /*!< ENET0_CLK */ 1773 5U, /*!< P3_CAN_PE_CLK */ 1774 0U, /*!< FLEXCAN0_CLK */ 1775 0U, /*!< FLEXCAN1_CLK */ 1776 0U, /*!< FLEXCAN2_CLK */ 1777 0U, /*!< FLEXCAN3_CLK */ 1778 0U, /*!< FLEXCAN4_CLK */ 1779 0U, /*!< FLEXCAN5_CLK */ 1780 0U, /*!< FLEXCAN6_CLK */ 1781 0U, /*!< FLEXCAN7_CLK */ 1782 0U, /*!< FLEXCAN8_CLK */ 1783 0U, /*!< FLEXCAN9_CLK */ 1784 0U, /*!< FLEXCAN10_CLK */ 1785 0U, /*!< FLEXCAN11_CLK */ 1786 0U, /*!< FLEXCAN12_CLK */ 1787 0U, /*!< FLEXCAN13_CLK */ 1788 0U, /*!< FLEXCAN14_CLK */ 1789 0U, /*!< FLEXCAN15_CLK */ 1790 0U, /*!< FLEXCAN16_CLK */ 1791 0U, /*!< FLEXCAN17_CLK */ 1792 0U, /*!< FLEXCAN18_CLK */ 1793 0U, /*!< FLEXCAN19_CLK */ 1794 0U, /*!< FLEXCAN20_CLK */ 1795 0U, /*!< FLEXCAN21_CLK */ 1796 0U, /*!< FLEXCAN22_CLK */ 1797 0U, /*!< FLEXCAN23_CLK */ 1798 37U, /*!< P0_FR_PE_CLK */ 1799 0U, /*!< FRAY0_CLK */ 1800 0U, /*!< FRAY1_CLK */ 1801 0U, /*!< GTM_CLK */ 1802 0U, /*!< IIIC0_CLK */ 1803 0U, /*!< IIIC1_CLK */ 1804 0U, /*!< IIIC2_CLK */ 1805 34U, /*!< P0_LIN_BAUD_CLK */ 1806 0U, /*!< LIN0_CLK */ 1807 0U, /*!< LIN1_CLK */ 1808 0U, /*!< LIN2_CLK */ 1809 8U, /*!< P1_LIN_BAUD_CLK */ 1810 0U, /*!< LIN3_CLK */ 1811 0U, /*!< LIN4_CLK */ 1812 0U, /*!< LIN5_CLK */ 1813 16U, /*!< P4_LIN_BAUD_CLK */ 1814 0U, /*!< LIN6_CLK */ 1815 0U, /*!< LIN7_CLK */ 1816 0U, /*!< LIN8_CLK */ 1817 4U, /*!< P5_LIN_BAUD_CLK */ 1818 0U, /*!< LIN9_CLK */ 1819 0U, /*!< LIN10_CLK */ 1820 0U, /*!< LIN11_CLK */ 1821 0U, /*!< MSCDSPI_CLK */ 1822 0U, /*!< MSCLIN_CLK */ 1823 0U, /*!< NANO_CLK */ 1824 0U, /*!< P0_CLKOUT_SRC_CLK */ 1825 43U, /*!< P0_CTU_PER_CLK */ 1826 42U, /*!< P0_DSPI_MSC_CLK */ 1827 44U, /*!< P0_EMIOS_LCU_CLK */ 1828 39U, /*!< P0_GTM_CLK */ 1829 40U, /*!< P0_GTM_NOC_CLK */ 1830 41U, /*!< P0_GTM_TS_CLK */ 1831 35U, /*!< P0_LIN_CLK */ 1832 38U, /*!< P0_NANO_CLK */ 1833 28U, /*!< P0_PSI5_125K_CLK */ 1834 29U, /*!< P0_PSI5_189K_CLK */ 1835 32U, /*!< P0_PSI5_S_BAUD_CLK */ 1836 33U, /*!< P0_PSI5_S_CORE_CLK */ 1837 0U, /*!< P0_PSI5_S_TRIG0_CLK */ 1838 0U, /*!< P0_PSI5_S_TRIG1_CLK */ 1839 0U, /*!< P0_PSI5_S_TRIG2_CLK */ 1840 0U, /*!< P0_PSI5_S_TRIG3_CLK */ 1841 31U, /*!< P0_PSI5_S_UART_CLK */ 1842 0U, /*!< P0_PSI5_S_WDOG0_CLK */ 1843 0U, /*!< P0_PSI5_S_WDOG1_CLK */ 1844 0U, /*!< P0_PSI5_S_WDOG2_CLK */ 1845 0U, /*!< P0_PSI5_S_WDOG3_CLK */ 1846 26U, /*!< P0_REG_INTF_2X_CLK */ 1847 25U, /*!< P0_REG_INTF_CLK */ 1848 0U, /*!< P1_CLKOUT_SRC_CLK */ 1849 7U, /*!< P1_DSPI60_CLK */ 1850 10U, /*!< ETH_TS_CLK */ 1851 11U, /*!< ETH_TS_DIV4_CLK */ 1852 16U, /*!< ETH0_REF_RMII_CLK */ 1853 14U, /*!< ETH0_RX_MII_CLK */ 1854 15U, /*!< ETH0_RX_RGMII_CLK */ 1855 13U, /*!< ETH0_TX_RGMII_CLK */ 1856 0U, /*!< ETH0_PS_TX_CLK */ 1857 21U, /*!< ETH1_REF_RMII_CLK */ 1858 19U, /*!< ETH1_RX_MII_CLK */ 1859 20U, /*!< ETH1_RX_RGMII_CLK */ 1860 17U, /*!< ETH1_TX_MII_CLK */ 1861 18U, /*!< ETH1_TX_RGMII_CLK */ 1862 0U, /*!< ETH1_PS_TX_CLK */ 1863 0U, /*!< P1_LFAST0_REF_CLK */ 1864 0U, /*!< P1_LFAST1_REF_CLK */ 1865 0U, /*!< P1_NETC_AXI_CLK */ 1866 9U, /*!< P1_LIN_CLK */ 1867 5U, /*!< P1_REG_INTF_CLK */ 1868 0U, /*!< P2_DBG_ATB_CLK */ 1869 0U, /*!< P2_REG_INTF_CLK */ 1870 5U, /*!< P3_AES_CLK */ 1871 0U, /*!< P3_CLKOUT_SRC_CLK */ 1872 4U, /*!< P3_DBG_TS_CLK */ 1873 3U, /*!< P3_REG_INTF_CLK */ 1874 0U, /*!< P3_SYS_MON1_CLK */ 1875 0U, /*!< P3_SYS_MON2_CLK */ 1876 0U, /*!< P3_SYS_MON3_CLK */ 1877 0U, /*!< P4_CLKOUT_SRC_CLK */ 1878 13U, /*!< P4_DSPI60_CLK */ 1879 23U, /*!< P4_EMIOS_LCU_CLK */ 1880 17U, /*!< P4_LIN_CLK */ 1881 6U, /*!< P4_PSI5_125K_CLK */ 1882 7U, /*!< P4_PSI5_189K_CLK */ 1883 10U, /*!< P4_PSI5_S_BAUD_CLK */ 1884 11U, /*!< P4_PSI5_S_CORE_CLK */ 1885 0U, /*!< P4_PSI5_S_TRIG0_CLK */ 1886 0U, /*!< P4_PSI5_S_TRIG1_CLK */ 1887 0U, /*!< P4_PSI5_S_TRIG2_CLK */ 1888 0U, /*!< P4_PSI5_S_TRIG3_CLK */ 1889 9U, /*!< P4_PSI5_S_UART_CLK */ 1890 0U, /*!< P4_PSI5_S_WDOG0_CLK */ 1891 0U, /*!< P4_PSI5_S_WDOG1_CLK */ 1892 0U, /*!< P4_PSI5_S_WDOG2_CLK */ 1893 0U, /*!< P4_PSI5_S_WDOG3_CLK */ 1894 14U, /*!< P4_QSPI0_2X_CLK */ 1895 15U, /*!< P4_QSPI0_1X_CLK */ 1896 19U, /*!< P4_QSPI1_2X_CLK */ 1897 20U, /*!< P4_QSPI1_1X_CLK */ 1898 4U, /*!< P4_REG_INTF_2X_CLK */ 1899 3U, /*!< P4_REG_INTF_CLK */ 1900 21U, /*!< P4_SDHC_IP_CLK */ 1901 22U, /*!< P4_SDHC_IP_DIV2_CLK */ 1902 7U, /*!< P5_DIPORT_CLK */ 1903 8U, /*!< P5_AE_CLK */ 1904 9U, /*!< P5_CANXL_PE_CLK */ 1905 10U, /*!< P5_CANXL_CHI_CLK */ 1906 0U, /*!< P5_CLKOUT_SRC_CLK */ 1907 5U, /*!< P5_LIN_CLK */ 1908 3U, /*!< P5_REG_INTF_CLK */ 1909 0U, /*!< P6_REG_INTF_CLK */ 1910 0U, /*!< PIT0_CLK */ 1911 0U, /*!< PIT1_CLK */ 1912 0U, /*!< PIT4_CLK */ 1913 0U, /*!< PIT5_CLK */ 1914 27U, /*!< P0_PSI5_1US_CLK */ 1915 0U, /*!< PSI5_0_CLK */ 1916 5U, /*!< P4_PSI5_1US_CLK */ 1917 0U, /*!< PSI5_1_CLK */ 1918 0U, /*!< PSI5S_0_CLK */ 1919 0U, /*!< PSI5S_1_CLK */ 1920 0U, /*!< QSPI0_CLK */ 1921 0U, /*!< QSPI1_CLK */ 1922 0U, /*!< RTU0_CORE_MON1_CLK */ 1923 0U, /*!< RTU0_CORE_MON2_CLK */ 1924 0U, /*!< RTU0_CORE_DIV2_MON1_CLK */ 1925 0U, /*!< RTU0_CORE_DIV2_MON2_CLK */ 1926 0U, /*!< RTU0_CORE_DIV2_MON3_CLK */ 1927 0U, /*!< RTU0_REG_INTF_CLK */ 1928 0U, /*!< RTU1_CORE_MON1_CLK */ 1929 0U, /*!< RTU1_CORE_MON2_CLK */ 1930 0U, /*!< RTU1_CORE_DIV2_MON1_CLK */ 1931 0U, /*!< RTU1_CORE_DIV2_MON2_CLK */ 1932 0U, /*!< RTU1_CORE_DIV2_MON3_CLK */ 1933 0U, /*!< RTU1_REG_INTF_CLK */ 1934 18U, /*!< P4_SDHC_CLK */ 1935 0U, /*!< RXLUT_CLK */ 1936 0U, /*!< SDHC0_CLK */ 1937 0U, /*!< SINC_CLK */ 1938 0U, /*!< SIPI0_CLK */ 1939 0U, /*!< SIPI1_CLK */ 1940 0U, /*!< SIUL2_0_CLK */ 1941 0U, /*!< SIUL2_1_CLK */ 1942 0U, /*!< SIUL2_4_CLK */ 1943 0U, /*!< SIUL2_5_CLK */ 1944 36U, /*!< P0_DSPI_CLK */ 1945 0U, /*!< SPI0_CLK */ 1946 0U, /*!< SPI1_CLK */ 1947 6U, /*!< P1_DSPI_CLK */ 1948 0U, /*!< SPI2_CLK */ 1949 0U, /*!< SPI3_CLK */ 1950 0U, /*!< SPI4_CLK */ 1951 12U, /*!< P4_DSPI_CLK */ 1952 0U, /*!< SPI5_CLK */ 1953 0U, /*!< SPI6_CLK */ 1954 0U, /*!< SPI7_CLK */ 1955 6U, /*!< P5_DSPI_CLK */ 1956 0U, /*!< SPI8_CLK */ 1957 0U, /*!< SPI9_CLK */ 1958 0U, /*!< SRX0_CLK */ 1959 0U, /*!< SRX1_CLK */ 1960 45U, /*!< CORE_PLL_REFCLKOUT clock */ 1961 46U, /*!< CORE_PLL_FBCLKOUT clock */ 1962 47U, /*!< PERIPH_PLL_REFCLKOUT clock */ 1963 48U, /*!< PERIPH_PLL_FBCLKOUT clock */ 1964 }; 1965 1966 1967 #ifdef CLOCK_IP_MC_ME_AE_GS_S_SYSCLK 1968 /*! 1969 * @brief Converts a clock name to a AE selector entry hardware value 1970 */ 1971 const uint16 Clock_Ip_au16SelectorEntryAeHardwareValue[CLOCK_IP_FEATURE_NAMES_NO] = { 1972 0U, /*!< CLOCK_IS_OFF */ 1973 0U, /*!< FIRC_CLK */ 1974 0U, /*!< FXOSC_CLK */ 1975 0U, /*!< SIRC_CLK */ 1976 #if defined(CLOCK_IP_HAS_FIRC_AE_CLK) 1977 0U, /*!< FIRC_AE_CLK */ 1978 #endif 1979 0U, /*!< COREPLL_CLK */ 1980 0U, /*!< PERIPHPLL_CLK */ 1981 0U, /*!< DDRPLL_CLK */ 1982 0U, /*!< LFAST0_PLL_CLK */ 1983 0U, /*!< LFAST1_PLL_CLK */ 1984 0U, /*!< CORE_PLL_PHI0_CLK */ 1985 0U, /*!< CORE_PLL_DFS0_CLK */ 1986 0U, /*!< CORE_PLL_DFS1_CLK */ 1987 0U, /*!< CORE_PLL_DFS2_CLK */ 1988 0U, /*!< CORE_PLL_DFS3_CLK */ 1989 0U, /*!< CORE_PLL_DFS4_CLK */ 1990 0U, /*!< CORE_PLL_DFS5_CLK */ 1991 0U, /*!< PERIPH_PLL_PHI0_CLK */ 1992 0U, /*!< PERIPH_PLL_PHI1_CLK */ 1993 0U, /*!< PERIPH_PLL_PHI2_CLK */ 1994 0U, /*!< PERIPH_PLL_PHI3_CLK */ 1995 0U, /*!< PERIPH_PLL_PHI4_CLK */ 1996 0U, /*!< PERIPH_PLL_PHI5_CLK */ 1997 0U, /*!< PERIPH_PLL_PHI6_CLK */ 1998 0U, /*!< PERIPH_PLL_DFS0_CLK */ 1999 0U, /*!< PERIPH_PLL_DFS1_CLK */ 2000 0U, /*!< PERIPH_PLL_DFS2_CLK */ 2001 0U, /*!< PERIPH_PLL_DFS3_CLK */ 2002 0U, /*!< PERIPH_PLL_DFS4_CLK */ 2003 0U, /*!< PERIPH_PLL_DFS5_CLK */ 2004 0U, /*!< DDR_PLL_PHI0_CLK */ 2005 0U, /*!< LFAST0_PLL_PH0_CLK */ 2006 0U, /*!< LFAST1_PLL_PH0_CLK */ 2007 0U, /*!< ENET_EXT_REF_CLK */ 2008 0U, /*!< ENET_EXT_TS_CLK */ 2009 0U, /*!< ENET0_EXT_RX_CLK */ 2010 0U, /*!< ENET0_EXT_TX_CLK */ 2011 0U, /*!< ENET1_EXT_RX_CLK */ 2012 0U, /*!< ENET1_EXT_TX_CLK */ 2013 0U, /*!< LFAST0_EXT_TX_CLK */ 2014 0U, /*!< LFAST1_EXT_TX_CLK */ 2015 0U, /*!< DDR_CLK */ 2016 0U, /*!< P0_SYS_CLK */ 2017 0U, /*!< P1_SYS_CLK */ 2018 0U, /*!< P1_SYS_DIV2_CLK */ 2019 0U, /*!< P1_SYS_DIV4_CLK */ 2020 0U, /*!< P2_SYS_CLK */ 2021 0U, /*!< CORE_M33_CLK */ 2022 0U, /*!< P2_SYS_DIV2_CLK */ 2023 0U, /*!< P2_SYS_DIV4_CLK */ 2024 0U, /*!< P3_SYS_CLK */ 2025 0U, /*!< CE_SYS_DIV2_CLK */ 2026 0U, /*!< CE_SYS_DIV4_CLK */ 2027 0U, /*!< P3_SYS_DIV2_NOC_CLK */ 2028 0U, /*!< P3_SYS_DIV4_CLK */ 2029 0U, /*!< P4_SYS_CLK */ 2030 0U, /*!< P4_SYS_DIV2_CLK */ 2031 0U, /*!< HSE_SYS_DIV2_CLK */ 2032 0U, /*!< P5_SYS_CLK */ 2033 0U, /*!< P5_SYS_DIV2_CLK */ 2034 0U, /*!< P5_SYS_DIV4_CLK */ 2035 0U, /*!< P2_MATH_CLK */ 2036 0U, /*!< P2_MATH_DIV3_CLK */ 2037 0U, /*!< GLB_LBIST_CLK */ 2038 0U, /*!< RTU0_CORE_CLK */ 2039 0U, /*!< RTU0_CORE_DIV2_CLK */ 2040 0U, /*!< RTU1_CORE_CLK */ 2041 0U, /*!< RTU1_CORE_DIV2_CLK */ 2042 0U, /*!< P0_PSI5_S_UTIL_CLK */ 2043 0U, /*!< P4_PSI5_S_UTIL_CLK */ 2044 #if defined(CLOCK_IP_HAS_SYSTEM_DRUN_CLK) 2045 0U, /*!< SYSTEM_DRUN_CLK */ 2046 #endif 2047 #if defined(CLOCK_IP_HAS_SYSTEM_RUN0_CLK) 2048 0U, /*!< SYSTEM_RUN0_CLK */ 2049 #endif 2050 #if defined(CLOCK_IP_HAS_SYSTEM_SAFE_CLK) 2051 0U, /*!< SYSTEM_SAFE_CLK */ 2052 #endif 2053 #if defined(CLOCK_IP_HAS_SYSTEM_CLK) 2054 0U, /*!< SYSTEM_CLK */ 2055 #endif 2056 #if defined(CLOCK_IP_HAS_SYSTEM_DIV2_CLK) 2057 0U, /*!< SYSTEM_DIV2_CL */ 2058 #endif 2059 #if defined(CLOCK_IP_HAS_SYSTEM_DIV4_MON1_CLK) 2060 0U, /*!< SYSTEM_DIV4_MON1_CLK */ 2061 #endif 2062 #if defined(CLOCK_IP_HAS_SYSTEM_DIV4_MON2_CLK) 2063 0U, /*!< SYSTEM_DIV4_MON2_CLK */ 2064 #endif 2065 0U, /*!< THE_LAST_PRODUCER_CLK */ 2066 0U, /*!< ADC0_CLK clock */ 2067 0U, /*!< ADC1_CLK clock */ 2068 0U, /*!< CE_EDMA_CLK clock */ 2069 0U, /*!< CE_PIT0_CLK clock */ 2070 0U, /*!< CE_PIT1_CLK clock */ 2071 0U, /*!< CE_PIT2_CLK clock */ 2072 0U, /*!< CE_PIT3_CLK clock */ 2073 0U, /*!< CE_PIT4_CLK clock */ 2074 0U, /*!< CE_PIT5_CLK clock */ 2075 0U, /*!< CLKOUT0_CLK clock */ 2076 0U, /*!< CLKOUT1_CLK clock */ 2077 0U, /*!< CLKOUT2_CLK clock */ 2078 0U, /*!< CLKOUT3_CLK clock */ 2079 0U, /*!< CLKOUT4_CLK clock */ 2080 0U, /*!< CTU_CLK clock */ 2081 0U, /*!< DMACRC0_CLK clock */ 2082 0U, /*!< DMACRC1_CLK clock */ 2083 0U, /*!< DMACRC4_CLK clock */ 2084 0U, /*!< DMACRC5_CLK clock */ 2085 0U, /*!< DMAMUX0_CLK clock */ 2086 0U, /*!< DMAMUX1_CLK clock */ 2087 0U, /*!< DMAMUX4_CLK clock */ 2088 0U, /*!< DMAMUX5_CLK clock */ 2089 0U, /*!< EDMA0_CLK clock */ 2090 0U, /*!< EDMA1_CLK clock */ 2091 0U, /*!< EDMA3_CLK clock */ 2092 0U, /*!< EDMA4_CLK clock */ 2093 0U, /*!< EDMA5_CLK clock */ 2094 0U, /*!< ETH0_TX_MII_CLK clock */ 2095 0U, /*!< ENET0_CLK clock */ 2096 0U, /*!< P3_CAN_PE_CLK clock */ 2097 0U, /*!< FLEXCAN0_CLK clock */ 2098 0U, /*!< FLEXCAN1_CLK clock */ 2099 0U, /*!< FLEXCAN2_CLK clock */ 2100 0U, /*!< FLEXCAN3_CLK clock */ 2101 0U, /*!< FLEXCAN4_CLK clock */ 2102 0U, /*!< FLEXCAN5_CLK clock */ 2103 0U, /*!< FLEXCAN6_CLK clock */ 2104 0U, /*!< FLEXCAN7_CLK clock */ 2105 0U, /*!< FLEXCAN8_CLK clock */ 2106 0U, /*!< FLEXCAN9_CLK clock */ 2107 0U, /*!< FLEXCAN10_CLK clock */ 2108 0U, /*!< FLEXCAN11_CLK clock */ 2109 0U, /*!< FLEXCAN12_CLK clock */ 2110 0U, /*!< FLEXCAN13_CLK clock */ 2111 0U, /*!< FLEXCAN14_CLK clock */ 2112 0U, /*!< FLEXCAN15_CLK clock */ 2113 0U, /*!< FLEXCAN16_CLK clock */ 2114 0U, /*!< FLEXCAN17_CLK clock */ 2115 0U, /*!< FLEXCAN18_CLK clock */ 2116 0U, /*!< FLEXCAN19_CLK clock */ 2117 0U, /*!< FLEXCAN20_CLK clock */ 2118 0U, /*!< FLEXCAN21_CLK clock */ 2119 0U, /*!< FLEXCAN22_CLK clock */ 2120 0U, /*!< FLEXCAN23_CLK clock */ 2121 0U, /*!< P0_FR_PE_CLK clock */ 2122 0U, /*!< FRAY0_CLK clock */ 2123 0U, /*!< FRAY1_CLK clock */ 2124 0U, /*!< GTM_CLK clock */ 2125 0U, /*!< IIIC0_CLK clock */ 2126 0U, /*!< IIIC1_CLK clock */ 2127 0U, /*!< IIIC2_CLK clock */ 2128 0U, /*!< P0_LIN_BAUD_CLK clock */ 2129 0U, /*!< LIN0_CLK clock */ 2130 0U, /*!< LIN1_CLK clock */ 2131 0U, /*!< LIN2_CLK clock */ 2132 0U, /*!< P1_LIN_BAUD_CLK clock */ 2133 0U, /*!< LIN3_CLK clock */ 2134 0U, /*!< LIN4_CLK clock */ 2135 0U, /*!< LIN5_CLK clock */ 2136 0U, /*!< P4_LIN_BAUD_CLK clock */ 2137 0U, /*!< LIN6_CLK clock */ 2138 0U, /*!< LIN7_CLK clock */ 2139 0U, /*!< LIN8_CLK clock */ 2140 0U, /*!< P5_LIN_BAUD_CLK clock */ 2141 0U, /*!< LIN9_CLK clock */ 2142 0U, /*!< LIN10_CLK clock */ 2143 0U, /*!< LIN11_CLK clock */ 2144 0U, /*!< MSCDSPI_CLK clock */ 2145 0U, /*!< MSCLIN_CLK clock */ 2146 0U, /*!< NANO_CLK clock */ 2147 0U, /*!< P0_CLKOUT_SRC_CLK clock */ 2148 0U, /*!< P0_CTU_PER_CLK clock */ 2149 0U, /*!< P0_DSPI_MSC_CLK clock */ 2150 0U, /*!< P0_EMIOS_LCU_CLK clock */ 2151 0U, /*!< P0_GTM_CLK clock */ 2152 0U, /*!< P0_GTM_NOC_CLK clock */ 2153 0U, /*!< P0_GTM_TS_CLK clock */ 2154 0U, /*!< P0_LIN_CLK clock */ 2155 0U, /*!< P0_NANO_CLK clock */ 2156 0U, /*!< P0_PSI5_125K_CLK clock */ 2157 0U, /*!< P0_PSI5_189K_CLK clock */ 2158 0U, /*!< P0_PSI5_S_BAUD_CLK clock */ 2159 0U, /*!< P0_PSI5_S_CORE_CLK clock */ 2160 0U, /*!< P0_PSI5_S_TRIG0_CLK clock */ 2161 0U, /*!< P0_PSI5_S_TRIG1_CLK clock */ 2162 0U, /*!< P0_PSI5_S_TRIG2_CLK clock */ 2163 0U, /*!< P0_PSI5_S_TRIG3_CLK clock */ 2164 0U, /*!< P0_PSI5_S_UART_CLK clock */ 2165 0U, /*!< P0_PSI5_S_WDOG0_CLK clock */ 2166 0U, /*!< P0_PSI5_S_WDOG1_CLK clock */ 2167 0U, /*!< P0_PSI5_S_WDOG2_CLK clock */ 2168 0U, /*!< P0_PSI5_S_WDOG3_CLK clock */ 2169 0U, /*!< P0_REG_INTF_2X_CLK clock */ 2170 0U, /*!< P0_REG_INTF_CLK clock */ 2171 0U, /*!< P1_CLKOUT_SRC_CLK clock */ 2172 0U, /*!< P1_DSPI60_CLK clock */ 2173 0U, /*!< ETH_TS_CLK clock */ 2174 0U, /*!< ETH_TS_DIV4_CLK clock */ 2175 0U, /*!< ETH0_REF_RMII_CLK clock */ 2176 0U, /*!< ETH0_RX_MII_CLK clock */ 2177 0U, /*!< ETH0_RX_RGMII_CLK clock */ 2178 0U, /*!< ETH0_TX_RGMII_CLK clock */ 2179 0U, /*!< ETH0_PS_TX_CLK */ 2180 0U, /*!< ETH1_REF_RMII_CLK clock */ 2181 0U, /*!< ETH1_RX_MII_CLK clock */ 2182 0U, /*!< ETH1_RX_RGMII_CLK clock */ 2183 0U, /*!< ETH1_TX_MII_CLK clock */ 2184 0U, /*!< ETH1_TX_RGMII_CLK clock */ 2185 0U, /*!< ETH1_PS_TX_CLK */ 2186 0U, /*!< P1_LFAST0_REF_CLK clock */ 2187 0U, /*!< P1_LFAST1_REF_CLK clock */ 2188 0U, /*!< P1_NETC_AXI_CLK clock */ 2189 0U, /*!< P1_LIN_CLK clock */ 2190 0U, /*!< P1_REG_INTF_CLK clock */ 2191 0U, /*!< P2_DBG_ATB_CLK clock */ 2192 0U, /*!< P2_REG_INTF_CLK clock */ 2193 0U, /*!< P3_AES_CLK clock */ 2194 0U, /*!< P3_CLKOUT_SRC_CLK clock */ 2195 0U, /*!< P3_DBG_TS_CLK clock */ 2196 0U, /*!< P3_REG_INTF_CLK clock */ 2197 0U, /*!< P3_SYS_MON1_CLK clock */ 2198 0U, /*!< P3_SYS_MON2_CLK clock */ 2199 0U, /*!< P3_SYS_MON3_CLK clock */ 2200 0U, /*!< P4_CLKOUT_SRC_CLK clock */ 2201 0U, /*!< P4_DSPI60_CLK clock */ 2202 0U, /*!< P4_EMIOS_LCU_CLK clock */ 2203 0U, /*!< P4_LIN_CLK clock */ 2204 0U, /*!< P4_PSI5_125K_CLK clock */ 2205 0U, /*!< P4_PSI5_189K_CLK clock */ 2206 0U, /*!< P4_PSI5_S_BAUD_CLK clock */ 2207 0U, /*!< P4_PSI5_S_CORE_CLK clock */ 2208 0U, /*!< P4_PSI5_S_TRIG0_CLK clock */ 2209 0U, /*!< P4_PSI5_S_TRIG1_CLK clock */ 2210 0U, /*!< P4_PSI5_S_TRIG2_CLK clock */ 2211 0U, /*!< P4_PSI5_S_TRIG3_CLK clock */ 2212 0U, /*!< P4_PSI5_S_UART_CLK clock */ 2213 0U, /*!< P4_PSI5_S_WDOG0_CLK clock */ 2214 0U, /*!< P4_PSI5_S_WDOG1_CLK clock */ 2215 0U, /*!< P4_PSI5_S_WDOG2_CLK clock */ 2216 0U, /*!< P4_PSI5_S_WDOG3_CLK clock */ 2217 0U, /*!< P4_QSPI0_2X_CLK clock */ 2218 0U, /*!< P4_QSPI0_1X_CLK clock */ 2219 0U, /*!< P4_QSPI1_2X_CLK clock */ 2220 0U, /*!< P4_QSPI1_1X_CLK clock */ 2221 0U, /*!< P4_REG_INTF_2X_CLK clock */ 2222 0U, /*!< P4_REG_INTF_CLK clock */ 2223 0U, /*!< P4_SDHC_IP_CLK clock */ 2224 0U, /*!< P4_SDHC_IP_DIV2_CLK clock */ 2225 0U, /*!< P5_DIPORT_CLK clock */ 2226 1U, /*!< P5_AE_CLK clock */ 2227 0U, /*!< P5_CANXL_PE_CLK clock */ 2228 0U, /*!< P5_CANXL_CHI_CLK clock */ 2229 0U, /*!< P5_CLKOUT_SRC_CLK clock */ 2230 0U, /*!< P5_LIN_CLK clock */ 2231 0U, /*!< P5_REG_INTF_CLK clock */ 2232 0U, /*!< P6_REG_INTF_CLK clock */ 2233 0U, /*!< PIT0_CLK clock */ 2234 0U, /*!< PIT1_CLK clock */ 2235 0U, /*!< PIT4_CLK clock */ 2236 0U, /*!< PIT5_CLK clock */ 2237 0U, /*!< P0_PSI5_1US_CLK clock */ 2238 0U, /*!< PSI5_0_CLK clock */ 2239 0U, /*!< P4_PSI5_1US_CLK clock */ 2240 0U, /*!< PSI5_1_CLK clock */ 2241 0U, /*!< PSI5S_0_CLK clock */ 2242 0U, /*!< PSI5S_1_CLK clock */ 2243 0U, /*!< QSPI0_CLK clock */ 2244 0U, /*!< QSPI1_CLK clock */ 2245 0U, /*!< RTU0_CORE_MON1_CLK */ 2246 0U, /*!< RTU0_CORE_MON2_CLK */ 2247 0U, /*!< RTU0_CORE_DIV2_MON1_CLK */ 2248 0U, /*!< RTU0_CORE_DIV2_MON2_CLK */ 2249 0U, /*!< RTU0_CORE_DIV2_MON3_CLK */ 2250 0U, /*!< RTU0_CORE_DIV2_MON4_CLK */ 2251 0U, /*!< RTU0_REG_INTF_CLK clock */ 2252 0U, /*!< RTU1_CORE_DIV2_MON1_CLK */ 2253 0U, /*!< RTU1_CORE_DIV2_MON2_CLK */ 2254 0U, /*!< RTU1_CORE_DIV2_MON3_CLK */ 2255 0U, /*!< RTU1_CORE_DIV2_MON4_CLK */ 2256 0U, /*!< RTU1_REG_INTF_CLK clock */ 2257 0U, /*!< P4_SDHC_CLK clock */ 2258 0U, /*!< RXLUT_CLK clock */ 2259 0U, /*!< SDHC0_CLK clock */ 2260 0U, /*!< SINC_CLK clock */ 2261 0U, /*!< SIPI0_CLK clock */ 2262 0U, /*!< SIPI1_CLK clock */ 2263 0U, /*!< SIUL2_0_CLK clock */ 2264 0U, /*!< SIUL2_1_CLK clock */ 2265 0U, /*!< SIUL2_4_CLK clock */ 2266 0U, /*!< SIUL2_5_CLK clock */ 2267 0U, /*!< P0_DSPI_CLK clock */ 2268 0U, /*!< SPI0_CLK clock */ 2269 0U, /*!< SPI1_CLK clock */ 2270 0U, /*!< P1_DSPI_CLK clock */ 2271 0U, /*!< SPI2_CLK clock */ 2272 0U, /*!< SPI3_CLK clock */ 2273 0U, /*!< SPI4_CLK clock */ 2274 0U, /*!< P4_DSPI_CLK clock */ 2275 0U, /*!< SPI5_CLK clock */ 2276 0U, /*!< SPI6_CLK clock */ 2277 0U, /*!< SPI7_CLK clock */ 2278 0U, /*!< P5_DSPI_CLK clock */ 2279 0U, /*!< SPI8_CLK clock */ 2280 0U, /*!< SPI9_CLK clock */ 2281 0U, /*!< SRX0_CLK clock */ 2282 0U, /*!< SRX1_CLK clock */ 2283 0U, /*!< CORE_PLL_REFCLKOUT clock */ 2284 0U, /*!< CORE_PLL_FBCLKOUT clock */ 2285 0U, /*!< PERIPH_PLL_REFCLKOUT clock */ 2286 0U, /*!< PERIPH_PLL_FBCLKOUT clock */ 2287 }; 2288 #endif 2289 2290 2291 /* Clock stop constant section data */ 2292 #define MCU_STOP_SEC_CONST_16 2293 #include "Mcu_MemMap.h" 2294 2295 2296 2297 2298 /* Clock start constant section data */ 2299 #define MCU_START_SEC_CONST_32 2300 #include "Mcu_MemMap.h" 2301 2302 #if (defined(CLOCK_IP_DEV_ERROR_DETECT)) 2303 #if (CLOCK_IP_DEV_ERROR_DETECT == STD_ON) 2304 /* Clock name types */ 2305 const uint32 Clock_Ip_au8ClockNameTypes[CLOCK_IP_NAMES_NO] = 2306 { 2307 /* CLOCK_IS_OFF clock */ 0U, /* CLOCK_IS_OFF */ 2308 /* FIRC_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FIRC_CLK clock */ 2309 /* FXOSC_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FXOSC_CLK clock */ 2310 /* SIRC_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SIRC_CLK clock */ 2311 #if defined(CLOCK_IP_HAS_FIRC_AE_CLK) 2312 /* FIRC_AE_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FIRC_AE_CLK clock */ 2313 #endif 2314 /* COREPLL_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* COREPLL_CLK clock */ 2315 /* PERIPHPLL_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* PERIPHPLL_CLK clock */ 2316 /* DDRPLL_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* DDRPLL_CLK clock */ 2317 /* LFAST0_PLL_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* LFAST0_PLL_CLK clock */ 2318 /* LFAST1_PLL_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* LFAST1_PLL_CLK clock */ 2319 /* COREPLL_PHI0 clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* COREPLL_PHI0 clock */ 2320 /* COREPLL_DFS0 clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* COREPLL_DFS0 clock */ 2321 /* COREPLL_DFS1 clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* COREPLL_DFS1 clock */ 2322 /* COREPLL_DFS2 clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* COREPLL_DFS2 clock */ 2323 /* COREPLL_DFS3 clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* COREPLL_DFS3 clock */ 2324 /* COREPLL_DFS4 clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* COREPLL_DFS4 clock */ 2325 /* COREPLL_DFS5 clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* COREPLL_DFS5 clock */ 2326 /* PERIPHPLL_PHI0 clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* PERIPHPLL_PHI0 clock */ 2327 /* PERIPHPLL_PHI1 clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* PERIPHPLL_PHI1 clock */ 2328 /* PERIPHPLL_PHI2 clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* PERIPHPLL_PHI2 clock */ 2329 /* PERIPHPLL_PHI3 clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* PERIPHPLL_PHI3 clock */ 2330 /* PERIPHPLL_PHI4 clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* PERIPHPLL_PHI4 clock */ 2331 /* PERIPHPLL_PHI5 clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* PERIPHPLL_PHI5 clock */ 2332 /* PERIPHPLL_PHI6 clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* PERIPHPLL_PHI6 clock */ 2333 /* PERIPHPLL_DFS0 clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* PERIPHPLL_DFS0 clock */ 2334 /* PERIPHPLL_DFS1 clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* PERIPHPLL_DFS1 clock */ 2335 /* PERIPHPLL_DFS2 clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* PERIPHPLL_DFS2 clock */ 2336 /* PERIPHPLL_DFS3 clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* PERIPHPLL_DFS3 clock */ 2337 /* PERIPHPLL_DFS4 clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* PERIPHPLL_DFS4 clock */ 2338 /* PERIPHPLL_DFS5 clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* PERIPHPLL_DFS5 clock */ 2339 /* DDRPLL_PHI0 clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* DDRPLL_PHI0 clock */ 2340 /* LFAST0_PLL_PH0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* LFAST0_PLL_PH0_CLK clock */ 2341 /* LFAST1_PLL_PH0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* LFAST0_PLL_PH0_CLK clock */ 2342 /* eth_rgmii_ref clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* eth_rgmii_ref clock */ 2343 /* tmr_1588_ref clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* tmr_1588_ref clock */ 2344 /* eth0_ext_rx clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* eth0_ext_rx clock */ 2345 /* eth0_ext_tx clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* eth0_ext_tx clock */ 2346 /* eth1_ext_rx clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* eth1_ext_rx clock */ 2347 /* eth1_ext_tx clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* eth1_ext_tx clock */ 2348 /* lfast0_ext_ref clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* lfast0_ext_ref clock */ 2349 /* lfast1_ext_ref clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* lfast1_ext_ref clock */ 2350 /* DDR_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* DDR_CLK clock */ 2351 /* P0_SYS_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_SYS_CLK clock */ 2352 /* P1_SYS_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P1_SYS_CLK clock */ 2353 /* P1_SYS_DIV2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P1_SYS_DIV2_CLK clock */ 2354 /* P1_SYS_DIV4_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P1_SYS_DIV4_CLK clock */ 2355 /* P2_SYS_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P2_SYS_CLK clock */ 2356 /* CORE_M33_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* CORE_M33_CLK clock */ 2357 /* P2_SYS_DIV2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P2_SYS_DIV2_CLK clock */ 2358 /* P2_SYS_DIV4_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P2_SYS_DIV4_CLK clock */ 2359 /* P3_SYS_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P3_SYS_CLK clock */ 2360 /* CE_SYS_DIV2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* CE_SYS_DIV2_CLK clock */ 2361 /* CE_SYS_DIV4_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* CE_SYS_DIV4_CLK clock */ 2362 /* P3_SYS_DIV2_NOC_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P3_SYS_DIV2_NOC_CLK clock */ 2363 /* P3_SYS_DIV4_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P3_SYS_DIV4_CLK clock */ 2364 /* P4_SYS_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_SYS_CLK clock */ 2365 /* P4_SYS_DIV2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_SYS_DIV2_CLK clock */ 2366 /* HSE_SYS_DIV2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* HSE_SYS_DIV2_CLK clock */ 2367 /* P5_SYS_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P5_SYS_CLK clock */ 2368 /* P5_SYS_DIV2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P5_SYS_DIV2_CLK clock */ 2369 /* P5_SYS_DIV4_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P5_SYS_DIV4_CLK clock */ 2370 /* P2_MATH_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P2_MATH_CLK clock */ 2371 /* P2_MATH_DIV3_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P2_MATH_DIV3_CLK clock */ 2372 /* GLB_LBIST_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* GLB_LBIST_CLK clock */ 2373 /* RTU0_CORE_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* RTU0_CORE_CLK clock */ 2374 /* RTU0_CORE_DIV2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* RTU0_CORE_DIV2_CLK clock */ 2375 /* RTU1_CORE_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* RTU1_CORE_CLK clock */ 2376 /* RTU1_CORE_DIV2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* RTU1_CORE_DIV2_CLK clock */ 2377 /* P0_PSI5_S_UTIL_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_PSI5_S_UTIL_CLK clock */ 2378 /* P4_PSI5_S_UTIL_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_PSI5_S_UTIL_CLK clock */ 2379 #if defined(CLOCK_IP_HAS_SYSTEM_DRUN_CLK) 2380 /* SYSTEM_DRUN_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SYSTEM_DRUN_CLK clock */ 2381 #endif 2382 #if defined(CLOCK_IP_HAS_SYSTEM_RUN0_CLK) 2383 /* SYSTEM_RUN0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SYSTEM_RUN0_CLK clock */ 2384 #endif 2385 #if defined(CLOCK_IP_HAS_SYSTEM_SAFE_CLK) 2386 /* SYSTEM_SAFE_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SYSTEM_SAFE_CLK clock */ 2387 #endif 2388 #if defined(CLOCK_IP_HAS_SYSTEM_CLK) 2389 /* SYSTEM_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SYSTEM_CLK clock */ 2390 #endif 2391 #if defined(CLOCK_IP_HAS_SYSTEM_DIV2_CLK) 2392 /* SYSTEM_DIV2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SYSTEM_DIV2_CLK clock */ 2393 #endif 2394 #if defined(CLOCK_IP_HAS_SYSTEM_DIV4_MON1_CLK) 2395 /* SYSTEM_DIV4_MON1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SYSTEM_DIV4_MON1_CLK clock */ 2396 #endif 2397 #if defined(CLOCK_IP_HAS_SYSTEM_DIV4_MON2_CLK) 2398 /* SYSTEM_DIV4_MON2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SYSTEM_DIV4_MON2_CLK clock */ 2399 #endif 2400 /* THE_LAST_PRODUCER_CLK */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* THE_LAST_PRODUCER_CLK */ 2401 /* ADC0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* ADC0_CLK clock */ 2402 /* ADC1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* ADC1_CLK clock */ 2403 /* CE_EDMA_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* CE_EDMA_CLK clock */ 2404 /* CE_PIT0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* CE_PIT0_CLK clock */ 2405 /* CE_PIT1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* CE_PIT1_CLK clock */ 2406 /* CE_PIT2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* CE_PIT2_CLK clock */ 2407 /* CE_PIT3_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* CE_PIT3_CLK clock */ 2408 /* CE_PIT4_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* CE_PIT4_CLK clock */ 2409 /* CE_PIT5_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* CE_PIT5_CLK clock */ 2410 /* CLKOUT0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* CLKOUT0_CLK clock */ 2411 /* CLKOUT1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* CLKOUT1_CLK clock */ 2412 /* CLKOUT3_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* CLKOUT3_CLK clock */ 2413 /* CLKOUT4_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* CLKOUT4_CLK clock */ 2414 /* CLKOUT5_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* CLKOUT5_CLK clock */ 2415 /* CTU_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* CTU_CLK clock */ 2416 /* DMACRC0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* DMACRC0_CLK clock */ 2417 /* DMACRC1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* DMACRC1_CLK clock */ 2418 /* DMACRC4_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* DMACRC4_CLK clock */ 2419 /* DMACRC5_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* DMACRC5_CLK clock */ 2420 /* DMAMUX0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* DMAMUX0_CLK clock */ 2421 /* DMAMUX1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* DMAMUX1_CLK clock */ 2422 /* DMAMUX4_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* DMAMUX4_CLK clock */ 2423 /* DMAMUX5_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* DMAMUX5_CLK clock */ 2424 /* EDMA0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* EDMA0_CLK clock */ 2425 /* EDMA1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* EDMA1_CLK clock */ 2426 /* EDMA3_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* EDMA3_CLK clock */ 2427 /* EDMA4_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* EDMA4_CLK clock */ 2428 /* EDMA5_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* EDMA5_CLK clock */ 2429 /* ETH0_TX_MII_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* ETH0_TX_MII_CLK clock */ 2430 /* ENET0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* ENET0_CLK clock */ 2431 /* P3_CAN_PE_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P3_CAN_PE_CLK clock */ 2432 /* FLEXCAN0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FLEXCAN0_CLK clock */ 2433 /* FLEXCAN1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FLEXCAN1_CLK clock */ 2434 /* FLEXCAN2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FLEXCAN2_CLK clock */ 2435 /* FLEXCAN3_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FLEXCAN3_CLK clock */ 2436 /* FLEXCAN4_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FLEXCAN4_CLK clock */ 2437 /* FLEXCAN5_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FLEXCAN5_CLK clock */ 2438 /* FLEXCAN6_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FLEXCAN6_CLK clock */ 2439 /* FLEXCAN7_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FLEXCAN7_CLK clock */ 2440 /* FLEXCAN8_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FLEXCAN8_CLK clock */ 2441 /* FLEXCAN9_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FLEXCAN9_CLK clock */ 2442 /* FLEXCAN10_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FLEXCAN10_CLK clock */ 2443 /* FLEXCAN11_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FLEXCAN11_CLK clock */ 2444 /* FLEXCAN12_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FLEXCAN12_CLK clock */ 2445 /* FLEXCAN13_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FLEXCAN13_CLK clock */ 2446 /* FLEXCAN14_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FLEXCAN14_CLK clock */ 2447 /* FLEXCAN15_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FLEXCAN15_CLK clock */ 2448 /* FLEXCAN16_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FLEXCAN16_CLK clock */ 2449 /* FLEXCAN17_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FLEXCAN17_CLK clock */ 2450 /* FLEXCAN18_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FLEXCAN18_CLK clock */ 2451 /* FLEXCAN19_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FLEXCAN19_CLK clock */ 2452 /* FLEXCAN20_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FLEXCAN20_CLK clock */ 2453 /* FLEXCAN21_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FLEXCAN21_CLK clock */ 2454 /* FLEXCAN22_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FLEXCAN22_CLK clock */ 2455 /* FLEXCAN23_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FLEXCAN23_CLK clock */ 2456 /* P0_FR_PE_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_FR_PE_CLK clock */ 2457 /* FRAY0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FRAY0_CLK clock */ 2458 /* FRAY1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FRAY1_CLK clock */ 2459 /* GTM_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* GTM_CLK clock */ 2460 /* IIIC0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* IIIC0_CLK clock */ 2461 /* IIIC1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* IIIC1_CLK clock */ 2462 /* IIIC2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* IIIC2_CLK clock */ 2463 /* P0_LIN_BAUD_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_LIN_BAUD_CLK clock */ 2464 /* LIN0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* LIN0_CLK clock */ 2465 /* LIN1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* LIN1_CLK clock */ 2466 /* LIN2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* LIN2_CLK clock */ 2467 /* P1_LIN_BAUD_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P1_LIN_BAUD_CLK clock */ 2468 /* LIN3_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* LIN3_CLK clock */ 2469 /* LIN4_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* LIN4_CLK clock */ 2470 /* LIN5_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* LIN5_CLK clock */ 2471 /* P4_LIN_BAUD_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_LIN_BAUD_CLK clock */ 2472 /* LIN6_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* LIN6_CLK clock */ 2473 /* LIN7_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* LIN7_CLK clock */ 2474 /* LIN8_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* LIN8_CLK clock */ 2475 /* P5_LIN_BAUD_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P5_LIN_BAUD_CLK clock */ 2476 /* LIN9_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* LIN9_CLK clock */ 2477 /* LIN10_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* LIN10_CLK clock */ 2478 /* LIN11_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* LIN11_CLK clock */ 2479 /* MSCDSPI_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* MSCDSPI_CLK clock */ 2480 /* MSCLIN_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* MSCLIN_CLK clock */ 2481 /* NANO_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* NANO_CLK clock */ 2482 /* P0_CLKOUT_SRC_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_CLKOUT_SRC_CLK clock */ 2483 /* P0_CTU_PER_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_CTU_PER_CLK clock */ 2484 /* P0_DSPI_MSC_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_DSPI_MSC_CLK clock */ 2485 /* P0_EMIOS_LCU_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_EMIOS_LCU_CLK clock */ 2486 /* P0_GTM_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_GTM_CLK clock */ 2487 /* P0_GTM_NOC_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_GTM_NOC_CLK clock */ 2488 /* P0_GTM_TS_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_GTM_TS_CLK clock */ 2489 /* P0_LIN_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_LIN_CLK clock */ 2490 /* P0_NANO_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_NANO_CLK clock */ 2491 /* P0_PSI5_125K_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_PSI5_125K_CLK clock */ 2492 /* P0_PSI5_189K_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_PSI5_189K_CLK clock */ 2493 /* P0_PSI5_S_BAUD_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_PSI5_S_BAUD_CLK clock */ 2494 /* P0_PSI5_S_CORE_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_PSI5_S_CORE_CLK clock */ 2495 /* P0_PSI5_S_TRIG0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_PSI5_S_TRIG0_CLK clock */ 2496 /* P0_PSI5_S_TRIG1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_PSI5_S_TRIG1_CLK clock */ 2497 /* P0_PSI5_S_TRIG2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_PSI5_S_TRIG2_CLK clock */ 2498 /* P0_PSI5_S_TRIG3_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_PSI5_S_TRIG3_CLK clock */ 2499 /* P0_PSI5_S_UART_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_PSI5_S_UART_CLK clock */ 2500 /* P0_PSI5_S_WDOG0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_PSI5_S_WDOG0_CLK clock */ 2501 /* P0_PSI5_S_WDOG1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_PSI5_S_WDOG1_CLK clock */ 2502 /* P0_PSI5_S_WDOG2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_PSI5_S_WDOG2_CLK clock */ 2503 /* P0_PSI5_S_WDOG3_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_PSI5_S_WDOG3_CLK clock */ 2504 /* P0_REG_INTF_2X_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_REG_INTF_2X_CLK clock */ 2505 /* P0_REG_INTF_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_REG_INTF_CLK clock */ 2506 /* P1_CLKOUT_SRC_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P1_CLKOUT_SRC_CLK clock */ 2507 /* P1_DSPI60_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P1_DSPI60_CLK clock */ 2508 /* ETH_TS_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* ETH_TS_CLK clock */ 2509 /* ETH_TS_DIV4_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* ETH_TS_DIV4_CLK clock */ 2510 /* ETH0_REF_RMII_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* ETH0_REF_RMII_CLK clock */ 2511 /* ETH0_RX_MII_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* ETH0_RX_MII_CLK clock */ 2512 /* ETH0_RX_RGMII_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* ETH0_RX_RGMII_CLK clock */ 2513 /* ETH0_TX_RGMII_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* ETH0_TX_RGMII_CLK clock */ 2514 /* ETH0_PS_TX_CLK */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* ETH0_PS_TX_CLK */ 2515 /* ETH1_REF_RMII_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* ETH1_REF_RMII_CLK clock */ 2516 /* ETH1_RX_MII_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* ETH1_RX_MII_CLK clock */ 2517 /* ETH1_RX_RGMII_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* ETH1_RX_RGMII_CLK clock */ 2518 /* ETH1_TX_MII_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* ETH1_TX_MII_CLK clock */ 2519 /* ETH1_TX_RGMII_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* ETH1_TX_RGMII_CLK clock */ 2520 /* ETH1_PS_TX_CLK */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* ETH1_PS_TX_CLK */ 2521 /* P1_LFAST0_REF_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P1_LFAST0_REF_CLK clock */ 2522 /* P1_LFAST1_REF_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P1_LFAST1_REF_CLK clock */ 2523 /* P1_NETC_AXI_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P1_NETC_AXI_CLK clock */ 2524 /* P1_LIN_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P1_LIN_CLK clock */ 2525 /* P1_REG_INTF_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P1_REG_INTF_CLK clock */ 2526 /* P2_DBG_ATB_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P2_DBG_ATB_CLK clock */ 2527 /* P2_REG_INTF_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P2_REG_INTF_CLK clock */ 2528 /* P3_AES_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P3_AES_CLK clock */ 2529 /* P3_CLKOUT_SRC_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P3_CLKOUT_SRC_CLK clock */ 2530 /* P3_DBG_TS_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P3_DBG_TS_CLK clock */ 2531 /* P3_REG_INTF_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P3_REG_INTF_CLK clock */ 2532 /* P3_SYS_MON1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P3_SYS_MON1_CLK clock */ 2533 /* P3_SYS_MON2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P3_SYS_MON2_CLK clock */ 2534 /* P3_SYS_MON3_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P3_SYS_MON3_CLK clock */ 2535 /* P4_CLKOUT_SRC_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_CLKOUT_SRC_CLK clock */ 2536 /* P4_DSPI60_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_DSPI60_CLK clock */ 2537 /* P4_EMIOS_LCU_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_EMIOS_LCU_CLK clock */ 2538 /* P4_LIN_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_LIN_CLK clock */ 2539 /* P4_PSI5_125K_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_PSI5_125K_CLK clock */ 2540 /* P4_PSI5_189K_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_PSI5_189K_CLK clock */ 2541 /* P4_PSI5_S_BAUD_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_PSI5_S_BAUD_CLK clock */ 2542 /* P4_PSI5_S_CORE_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_PSI5_S_CORE_CLK clock */ 2543 /* P4_PSI5_S_TRIG0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_PSI5_S_TRIG0_CLK clock */ 2544 /* P4_PSI5_S_TRIG1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_PSI5_S_TRIG1_CLK clock */ 2545 /* P4_PSI5_S_TRIG2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_PSI5_S_TRIG2_CLK clock */ 2546 /* P4_PSI5_S_TRIG3_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_PSI5_S_TRIG3_CLK clock */ 2547 /* P4_PSI5_S_UART_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_PSI5_S_UART_CLK clock */ 2548 /* P4_PSI5_S_WDOG0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_PSI5_S_WDOG0_CLK clock */ 2549 /* P4_PSI5_S_WDOG1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_PSI5_S_WDOG1_CLK clock */ 2550 /* P4_PSI5_S_WDOG2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_PSI5_S_WDOG2_CLK clock */ 2551 /* P4_PSI5_S_WDOG3_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_PSI5_S_WDOG3_CLK clock */ 2552 /* P4_QSPI0_2X_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_QSPI0_2X_CLK clock */ 2553 /* P4_QSPI0_1X_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_QSPI0_1X_CLK clock */ 2554 /* P4_QSPI1_2X_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_QSPI1_2X_CLK clock */ 2555 /* P4_QSPI1_1X_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_QSPI1_1X_CLK clock */ 2556 /* P4_REG_INTF_2X_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_REG_INTF_2X_CLK clock */ 2557 /* P4_REG_INTF_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_REG_INTF_CLK clock */ 2558 /* P4_SDHC_IP_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_SDHC_IP_CLK clock */ 2559 /* P4_SDHC_IP_DIV2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_SDHC_IP_DIV2_CLK clock */ 2560 /* P5_DIPORT_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P5_DIPORT_CLK clock */ 2561 /* P5_AE_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P5_AE_CLK clock */ 2562 /* P5_CANXL_PE_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P5_CANXL_PE_CLK clock */ 2563 /* P5_CANXL_CHI_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P5_CANXL_CHI_CLK clock */ 2564 /* P5_CLKOUT_SRC_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P5_CLKOUT_SRC_CLK clock */ 2565 /* P5_LIN_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P5_LIN_CLK clock */ 2566 /* P5_REG_INTF_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P5_REG_INTF_CLK clock */ 2567 /* P6_REG_INTF_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P6_REG_INTF_CLK clock */ 2568 /* PIT0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* PIT0_CLK clock */ 2569 /* PIT1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* PIT1_CLK clock */ 2570 /* PIT4_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* PIT4_CLK clock */ 2571 /* PIT5_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* PIT5_CLK clock */ 2572 /* P0_PSI5_1US_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_PSI5_1US_CLK clock */ 2573 /* PSI5_0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* PSI5_0_CLK clock */ 2574 /* P4_PSI5_1US_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_PSI5_1US_CLK clock */ 2575 /* PSI5_1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* PSI5_1_CLK clock */ 2576 /* PSI5S_0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* PSI5S_0_CLK clock */ 2577 /* PSI5S_1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* PSI5S_1_CLK clock */ 2578 /* QSPI0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* QSPI0_CLK clock */ 2579 /* QSPI1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* QSPI1_CLK clock */ 2580 /* RTU0_CORE_MON1_CLK */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* RTU0_CORE_MON1_CLK */ 2581 /* RTU0_CORE_MON2_CLK */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* RTU0_CORE_MON2_CLK */ 2582 /* RTU0_CORE_DIV2_MON1_CLK */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* RTU0_CORE_DIV2_MON1_CLK */ 2583 /* RTU0_CORE_DIV2_MON2_CLK */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* RTU0_CORE_DIV2_MON2_CLK */ 2584 /* RTU0_CORE_DIV2_MON3_CLK */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* RTU0_CORE_DIV2_MON3_CLK */ 2585 /* RTU0_REG_INTF_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* RTU0_REG_INTF_CLK clock */ 2586 /* RTU1_CORE_MON1_CLK */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* RTU1_CORE_MON1_CLK */ 2587 /* RTU1_CORE_MON2_CLK */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* RTU1_CORE_MON2_CLK */ 2588 /* RTU1_CORE_DIV2_MON1_CLK */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* RTU1_CORE_DIV2_MON1_CLK */ 2589 /* RTU1_CORE_DIV2_MON2_CLK */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* RTU1_CORE_DIV2_MON2_CLK */ 2590 /* RTU1_CORE_DIV2_MON3_CLK */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* RTU1_CORE_DIV2_MON3_CLK */ 2591 /* RTU1_REG_INTF_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* RTU1_REG_INTF_CLK clock */ 2592 /* P4_SDHC_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_SDHC_CLK clock */ 2593 /* RXLUT clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* RXLUT clock */ 2594 /* SDHC0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SDHC0_CLK clock */ 2595 /* SINC_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SINC_CLK clock */ 2596 /* SIPI0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SIPI0_CLK clock */ 2597 /* SIPI1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SIPI1_CLK clock */ 2598 /* SIUL2_0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SIUL2_0_CLK clock */ 2599 /* SIUL2_1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SIUL2_1_CLK clock */ 2600 /* SIUL2_4_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SIUL2_4_CLK clock */ 2601 /* SIUL2_5_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SIUL2_5_CLK clock */ 2602 /* P0_DSPI_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_DSPI_CLK clock */ 2603 /* SPI0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SPI0_CLK clock */ 2604 /* SPI1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SPI1_CLK clock */ 2605 /* P1_DSPI_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P1_DSPI_CLK clock */ 2606 /* SPI2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SPI2_CLK clock */ 2607 /* SPI3_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SPI3_CLK clock */ 2608 /* SPI4_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SPI4_CLK clock */ 2609 /* P4_DSPI_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_DSPI_CLK clock */ 2610 /* SPI5_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SPI5_CLK clock */ 2611 /* SPI6_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SPI6_CLK clock */ 2612 /* SPI7_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SPI7_CLK clock */ 2613 /* P5_DSPI_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P5_DSPI_CLK clock */ 2614 /* SPI8_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SPI8_CLK clock */ 2615 /* SPI9_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SPI9_CLK clock */ 2616 /* SRX0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SRX0_CLK clock */ 2617 /* SRX1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SRX1_CLK clock */ 2618 /* CORE_PLL_REFCLKOUT clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* CORE_PLL_REFCLKOUT clock */ 2619 /* CORE_PLL_FBCLKOUT clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* CORE_PLL_FBCLKOUT clock */ 2620 /* PERIPH_PLL_REFCLKOUT clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* PERIPH_PLL_REFCLKOUT clock */ 2621 /* PERIPH_PLL_FBCLKOUT clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* PERIPH_PLL_FBCLKOUT clock */ 2622 }; 2623 #endif /* CLOCK_IP_DEV_ERROR_DETECT == STD_ON */ 2624 #endif /* CLOCK_IP_DEV_ERROR_DETECT */ 2625 /* Clock stop constant section data */ 2626 #define MCU_STOP_SEC_CONST_32 2627 #include "Mcu_MemMap.h" 2628 2629 2630 /* Clock start constant section data */ 2631 #define MCU_START_SEC_CONST_UNSPECIFIED 2632 #include "Mcu_MemMap.h" 2633 2634 Clock_Ip_CgmMuxType* const Clock_Ip_apxCgm[CLOCK_IP_MC_CGM_INSTANCES_COUNT][CLOCK_IP_MC_CGM_MUXS_COUNT] = 2635 { 2636 { 2637 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_0->MUX_0_CSC), 2638 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_0->MUX_1_CSC), 2639 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_0->MUX_2_CSC), 2640 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_0->MUX_3_CSC), 2641 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_0->MUX_4_CSC), 2642 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_0->MUX_5_CSC), 2643 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_0->MUX_6_CSC), 2644 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_0->MUX_7_CSC), 2645 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_0->MUX_8_CSC), 2646 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_0->MUX_9_CSC), 2647 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_0->MUX_10_CSC), 2648 NULL_PTR, 2649 NULL_PTR, 2650 NULL_PTR, 2651 NULL_PTR, 2652 }, 2653 2654 2655 { 2656 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_1->MUX_0_CSC), 2657 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_1->MUX_1_CSC), 2658 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_1->MUX_2_CSC), 2659 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_1->MUX_3_CSC), 2660 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_1->MUX_4_CSC), 2661 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_1->MUX_5_CSC), 2662 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_1->MUX_6_CSC), 2663 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_1->MUX_7_CSC), 2664 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_1->MUX_8_CSC), 2665 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_1->MUX_9_CSC), 2666 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_1->MUX_10_CSC), 2667 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_1->MUX_11_CSC), 2668 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_1->MUX_12_CSC), 2669 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_1->MUX_13_CSC), 2670 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_1->MUX_14_CSC), 2671 }, 2672 2673 2674 { 2675 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_2->MUX_0_CSC), 2676 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_2->MUX_1_CSC), 2677 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_2->MUX_2_CSC), 2678 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_2->MUX_3_CSC), 2679 NULL_PTR, 2680 NULL_PTR, 2681 NULL_PTR, 2682 NULL_PTR, 2683 NULL_PTR, 2684 NULL_PTR, 2685 NULL_PTR, 2686 NULL_PTR, 2687 NULL_PTR, 2688 NULL_PTR, 2689 NULL_PTR, 2690 }, 2691 2692 2693 { 2694 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_3->MUX_0_CSC), 2695 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_3->MUX_1_CSC), 2696 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_3->MUX_2_CSC), 2697 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_3->MUX_3_CSC), 2698 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_3->MUX_4_CSC), 2699 NULL_PTR, 2700 NULL_PTR, 2701 NULL_PTR, 2702 NULL_PTR, 2703 NULL_PTR, 2704 NULL_PTR, 2705 NULL_PTR, 2706 NULL_PTR, 2707 NULL_PTR, 2708 NULL_PTR, 2709 }, 2710 2711 2712 { (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_4->MUX_0_CSC), 2713 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_4->MUX_1_CSC), 2714 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_4->MUX_2_CSC), 2715 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_4->MUX_3_CSC), 2716 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_4->MUX_4_CSC), 2717 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_4->MUX_5_CSC), 2718 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_4->MUX_6_CSC), 2719 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_4->MUX_7_CSC), 2720 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_4->MUX_8_CSC), 2721 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_4->MUX_9_CSC), 2722 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_4->MUX_10_CSC), 2723 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_4->MUX_11_CSC), 2724 NULL_PTR, 2725 NULL_PTR, 2726 NULL_PTR, 2727 }, 2728 2729 2730 { (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_5->MUX_0_CSC), 2731 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_5->MUX_1_CSC), 2732 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_5->MUX_2_CSC), 2733 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_5->MUX_3_CSC), 2734 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_5->MUX_4_CSC), 2735 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_5->MUX_5_CSC), 2736 NULL_PTR, 2737 NULL_PTR, 2738 NULL_PTR, 2739 NULL_PTR, 2740 NULL_PTR, 2741 NULL_PTR, 2742 NULL_PTR, 2743 NULL_PTR, 2744 NULL_PTR, 2745 }, 2746 2747 2748 { (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_6->MUX_0_CSC), 2749 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_6->MUX_1_CSC), 2750 NULL_PTR, 2751 NULL_PTR, 2752 NULL_PTR, 2753 NULL_PTR, 2754 NULL_PTR, 2755 NULL_PTR, 2756 NULL_PTR, 2757 NULL_PTR, 2758 NULL_PTR, 2759 NULL_PTR, 2760 NULL_PTR, 2761 NULL_PTR, 2762 NULL_PTR, 2763 }, 2764 2765 2766 { (Clock_Ip_CgmMuxType*)(&CLOCK_IP_RTU0__MC_CGM->MUX_0_CSC), 2767 (Clock_Ip_CgmMuxType*)(&CLOCK_IP_RTU0__MC_CGM->MUX_1_CSC), 2768 NULL_PTR, 2769 NULL_PTR, 2770 NULL_PTR, 2771 NULL_PTR, 2772 NULL_PTR, 2773 NULL_PTR, 2774 NULL_PTR, 2775 NULL_PTR, 2776 NULL_PTR, 2777 NULL_PTR, 2778 NULL_PTR, 2779 NULL_PTR, 2780 NULL_PTR, 2781 }, 2782 2783 2784 { (Clock_Ip_CgmMuxType*)(&CLOCK_IP_RTU1__MC_CGM->MUX_0_CSC), 2785 (Clock_Ip_CgmMuxType*)(&CLOCK_IP_RTU1__MC_CGM->MUX_1_CSC), 2786 NULL_PTR, 2787 NULL_PTR, 2788 NULL_PTR, 2789 NULL_PTR, 2790 NULL_PTR, 2791 NULL_PTR, 2792 NULL_PTR, 2793 NULL_PTR, 2794 NULL_PTR, 2795 NULL_PTR, 2796 NULL_PTR, 2797 NULL_PTR, 2798 NULL_PTR, 2799 }, 2800 2801 /* No mux is implemented in CGM_AE */ 2802 { NULL_PTR, 2803 NULL_PTR, 2804 NULL_PTR, 2805 NULL_PTR, 2806 NULL_PTR, 2807 NULL_PTR, 2808 NULL_PTR, 2809 NULL_PTR, 2810 NULL_PTR, 2811 NULL_PTR, 2812 NULL_PTR, 2813 NULL_PTR, 2814 NULL_PTR, 2815 NULL_PTR, 2816 NULL_PTR, 2817 }, 2818 2819 }; 2820 volatile Clock_Ip_CgmPcfsType* const Clock_Ip_apxCgmPcfs[CLOCK_IP_MC_CGM_INSTANCES_COUNT] = 2821 { 2822 (volatile Clock_Ip_CgmPcfsType*)(&(IP_MC_CGM_0->PCFS_SDUR)), 2823 (volatile Clock_Ip_CgmPcfsType*)(&(IP_MC_CGM_1->PCFS_SDUR)), 2824 (volatile Clock_Ip_CgmPcfsType*)(&(IP_MC_CGM_2->PCFS_SDUR)), 2825 (volatile Clock_Ip_CgmPcfsType*)(&(IP_MC_CGM_3->PCFS_SDUR)), 2826 (volatile Clock_Ip_CgmPcfsType*)(&(IP_MC_CGM_4->PCFS_SDUR)), 2827 (volatile Clock_Ip_CgmPcfsType*)(&(IP_MC_CGM_5->PCFS_SDUR)), 2828 (volatile Clock_Ip_CgmPcfsType*)(&(IP_MC_CGM_6->PCFS_SDUR)), 2829 (volatile Clock_Ip_CgmPcfsType*)(&(CLOCK_IP_RTU0__MC_CGM->PCFS_SDUR)), 2830 (volatile Clock_Ip_CgmPcfsType*)(&(CLOCK_IP_RTU1__MC_CGM->PCFS_SDUR)), 2831 #if defined(CLOCK_IP_HAS_SYSTEM_CLK) 2832 (volatile Clock_Ip_CgmPcfsType*)(&(IP_MC_CGM_AE->PCFS_SDUR)), 2833 #else 2834 NULL_PTR, 2835 #endif 2836 }; 2837 2838 volatile uint32* const Clock_Ip_apxGprClkout[CLOCK_IP_GPR_INSTANCES_COUNT][CLOCK_IP_CLKOUTS_COUNT] = 2839 { 2840 /* GPR0 instance */ 2841 { 2842 (volatile uint32*)(&IP_GPR0->CLKOUT0SEL), 2843 NULL_PTR, 2844 NULL_PTR, 2845 NULL_PTR, 2846 NULL_PTR, 2847 }, 2848 2849 /* GPR1 instance */ 2850 { 2851 NULL_PTR, 2852 (volatile uint32*)(&IP_GPR1->CLKOUT1SEL), 2853 NULL_PTR, 2854 NULL_PTR, 2855 NULL_PTR, 2856 }, 2857 2858 /* GPR2 instance */ 2859 { 2860 NULL_PTR, 2861 NULL_PTR, 2862 NULL_PTR, 2863 NULL_PTR, 2864 NULL_PTR, 2865 }, 2866 2867 /* GPR3 instance */ 2868 { 2869 NULL_PTR, 2870 NULL_PTR, 2871 NULL_PTR, 2872 NULL_PTR, 2873 (volatile uint32*)(&IP_GPR3->CLKOUT4SEL), 2874 }, 2875 2876 /* GPR4 instance */ 2877 { 2878 NULL_PTR, 2879 NULL_PTR, 2880 (volatile uint32*)(&IP_GPR4->CLKOUT2SEL), 2881 NULL_PTR, 2882 NULL_PTR, 2883 2884 }, 2885 2886 /* GPR5 instance */ 2887 { 2888 NULL_PTR, 2889 NULL_PTR, 2890 NULL_PTR, 2891 (volatile uint32*)(&IP_GPR5->CLKOUT3SEL), 2892 NULL_PTR, 2893 2894 }, 2895 }; 2896 2897 #if defined(CLOCK_IP_HAS_SYSTEM_CLK) 2898 Clock_Ip_SystemClockType* const Clock_Ip_apxSystemClock = (Clock_Ip_SystemClockType*)(&(IP_MC_ME_AE->SAFE_MC)); 2899 #endif 2900 2901 Clock_Ip_ExtOSCType* const Clock_Ip_apxXosc[CLOCK_IP_XOSC_INSTANCES_ARRAY_SIZE] = {(Clock_Ip_ExtOSCType*)IP_FXOSC}; 2902 Clock_Ip_PllType const Clock_Ip_apxPll[CLOCK_IP_PLL_INSTANCES_ARRAY_SIZE] = { 2903 { 2904 IP_CORE_PLL, 2905 CLOCK_IP_COREPLL_DIVIDER_COUNT, 2906 }, 2907 { 2908 IP_PERIPH_PLL, 2909 CLOCK_IP_PERIPHPLL_DIVIDER_COUNT, 2910 }, 2911 { 2912 IP_DDR_PLL, 2913 CLOCK_IP_DDRPLL_DIVIDER_COUNT, 2914 } 2915 }; 2916 2917 Clock_Ip_LfastPllType const Clock_Ip_apxLfastPll[CLOCK_IP_LFASTPLL_INSTANCES_ARRAY_SIZE] = 2918 { 2919 { 2920 IP_LFAST_0, 2921 }, 2922 { 2923 IP_LFAST_1, 2924 }, 2925 }; 2926 2927 DFS_Type* const Clock_Ip_apxDfs[CLOCK_IP_DFS_INSTANCES_ARRAY_SIZE] = { 2928 IP_CORE_DFS, 2929 IP_PERIPH_DFS, 2930 }; 2931 Clock_Ip_ClockMonitorType* const Clock_Ip_apxCmu[CLOCK_IP_CMU_INSTANCES_ARRAY_SIZE] = 2932 { 2933 (Clock_Ip_ClockMonitorType*)IP_SMU__CMU_FC_BASE, 2934 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_0_BASE, 2935 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_1_BASE, 2936 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_2A_BASE, 2937 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_2B_BASE, 2938 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_2C_BASE, 2939 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_3_BASE, 2940 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_4_BASE, 2941 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_5_BASE, 2942 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_6_BASE, 2943 (Clock_Ip_ClockMonitorType*)IP_CE_CMU_FC_0_BASE, 2944 (Clock_Ip_ClockMonitorType*)IP_CE_CMU_FC_1_BASE, 2945 (Clock_Ip_ClockMonitorType*)IP_CE_CMU_FC_2_BASE, 2946 (Clock_Ip_ClockMonitorType*)IP_RTU0__CMU_FC_0_BASE, 2947 (Clock_Ip_ClockMonitorType*)IP_RTU0__CMU_FC_1_BASE, 2948 (Clock_Ip_ClockMonitorType*)IP_RTU0__CMU_FC_2_BASE, 2949 (Clock_Ip_ClockMonitorType*)IP_RTU0__CMU_FC_3_BASE, 2950 (Clock_Ip_ClockMonitorType*)IP_RTU0__CMU_FC_4_BASE, 2951 (Clock_Ip_ClockMonitorType*)IP_RTU0__CMU_FC_0_BASE, 2952 (Clock_Ip_ClockMonitorType*)IP_RTU0__CMU_FC_1_BASE, 2953 (Clock_Ip_ClockMonitorType*)IP_RTU0__CMU_FC_2_BASE, 2954 (Clock_Ip_ClockMonitorType*)IP_RTU0__CMU_FC_3_BASE, 2955 (Clock_Ip_ClockMonitorType*)IP_RTU0__CMU_FC_4_BASE, 2956 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_DEBUG_1_BASE, 2957 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_DEBUG_2_BASE, 2958 #if defined(CLOCK_IP_HAS_SYSTEM_DIV2_CLK) 2959 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_AE_1_BASE, 2960 #endif 2961 #if defined(CLOCK_IP_HAS_SYSTEM_DIV4_MON1_CLK) 2962 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_AE_2_BASE, 2963 #endif 2964 #if defined(CLOCK_IP_HAS_SYSTEM_DIV4_MON2_CLK) 2965 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_AE_3_BASE, 2966 #endif 2967 }; 2968 Clock_Ip_NameType const Clock_Ip_aeCmuNames[CLOCK_IP_CMU_INSTANCES_ARRAY_SIZE] = 2969 { 2970 P2_SYS_CLK, 2971 P0_REG_INTF_CLK, 2972 P1_REG_INTF_CLK, 2973 FIRC_CLK, 2974 FXOSC_CLK, 2975 P2_MATH_CLK, 2976 P3_SYS_MON1_CLK, 2977 P4_REG_INTF_CLK, 2978 P5_REG_INTF_CLK, 2979 DDR_CLK, 2980 P3_SYS_MON2_CLK, 2981 P3_SYS_MON3_CLK, 2982 CE_SYS_DIV2_CLK, 2983 RTU0_CORE_MON1_CLK, 2984 RTU0_CORE_DIV2_MON1_CLK, 2985 RTU0_CORE_DIV2_MON2_CLK, 2986 RTU0_CORE_MON2_CLK, 2987 RTU0_CORE_DIV2_MON3_CLK, 2988 RTU1_CORE_MON1_CLK, 2989 RTU1_CORE_DIV2_MON1_CLK, 2990 RTU1_CORE_DIV2_MON2_CLK, 2991 RTU1_CORE_MON2_CLK, 2992 RTU1_CORE_DIV2_MON3_CLK, 2993 P0_CLKOUT_SRC_CLK, 2994 P1_CLKOUT_SRC_CLK, 2995 #if defined(CLOCK_IP_HAS_SYSTEM_DIV2_CLK) 2996 SYSTEM_DIV2_CLK, 2997 #endif 2998 #if defined(CLOCK_IP_HAS_SYSTEM_DIV4_MON1_CLK) 2999 SYSTEM_DIV4_MON1_CLK, 3000 #endif 3001 #if defined(CLOCK_IP_HAS_SYSTEM_DIV4_MON2_CLK) 3002 SYSTEM_DIV4_MON2_CLK, 3003 #endif 3004 }; 3005 3006 Clock_Ip_CmuInfoType const Clock_Ip_axCmuInfo[CLOCK_IP_CMU_INFO_SIZE] = { 3007 3008 /* CLOCK_IP_SMU_CMU_FC_INSTANCE */ 3009 { 3010 P2_SYS_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3011 FXOSC_CLK, /* Name of the reference clock */ 3012 P2_SYS_DIV4_CLK, /* Name of the bus clock */ 3013 (Clock_Ip_ClockMonitorType*)IP_SMU__CMU_FC, /* Cmu instance */ 3014 }, 3015 /* CLOCK_IP_CMU_FC_0_INSTANCE */ 3016 { 3017 P0_REG_INTF_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3018 FXOSC_CLK, /* Name of the reference clock */ 3019 P0_REG_INTF_CLK, /* Name of the bus clock */ 3020 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_0, /* Cmu instance */ 3021 }, 3022 /* CLOCK_IP_CMU_FC_1_INSTANCE */ 3023 { 3024 P1_REG_INTF_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3025 FXOSC_CLK, /* Name of the reference clock */ 3026 P1_REG_INTF_CLK, /* Name of the bus clock */ 3027 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_1, /* Cmu instance */ 3028 }, 3029 /* CLOCK_IP_CMU_FC_2A_INSTANCE */ 3030 { 3031 FIRC_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3032 FXOSC_CLK, /* Name of the reference clock */ 3033 P2_REG_INTF_CLK, /* Name of the bus clock */ 3034 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_2A, /* Cmu instance */ 3035 }, 3036 /* CLOCK_IP_CMU_FC_2B_INSTANCE */ 3037 { 3038 FXOSC_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3039 FIRC_CLK, /* Name of the reference clock */ 3040 P2_REG_INTF_CLK, /* Name of the bus clock */ 3041 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_2B, /* Cmu instance */ 3042 }, 3043 /* CLOCK_IP_CMU_FC_2C_INSTANCE */ 3044 { 3045 P2_MATH_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3046 FXOSC_CLK, /* Name of the reference clock */ 3047 P2_REG_INTF_CLK, /* Name of the bus clock */ 3048 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_2C, /* Cmu instance */ 3049 }, 3050 /* CLOCK_IP_CMU_FC_3_INSTANCE */ 3051 { 3052 P3_SYS_MON1_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3053 FXOSC_CLK, /* Name of the reference clock */ 3054 P3_REG_INTF_CLK, /* Name of the bus clock */ 3055 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_3, /* Cmu instance */ 3056 }, 3057 /* CLOCK_IP_CMU_FC_4_INSTANCE */ 3058 { 3059 P4_REG_INTF_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3060 FXOSC_CLK, /* Name of the reference clock */ 3061 P4_REG_INTF_CLK, /* Name of the bus clock */ 3062 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_4, /* Cmu instance */ 3063 }, 3064 /* CLOCK_IP_CMU_FC_5_INSTANCE */ 3065 { 3066 P5_REG_INTF_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3067 FXOSC_CLK, /* Name of the reference clock */ 3068 P5_REG_INTF_CLK, /* Name of the bus clock */ 3069 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_5, /* Cmu instance */ 3070 }, 3071 /* CLOCK_IP_CMU_FC_6_INSTANCE */ 3072 { 3073 DDR_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3074 FXOSC_CLK, /* Name of the reference clock */ 3075 P6_REG_INTF_CLK, /* Name of the bus clock */ 3076 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_6, /* Cmu instance */ 3077 }, 3078 /* CLOCK_IP_CE_CMU_FC_0_INSTANCE */ 3079 { 3080 P3_SYS_MON2_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3081 FXOSC_CLK, /* Name of the reference clock */ 3082 CE_SYS_DIV4_CLK, /* Name of the bus clock */ 3083 (Clock_Ip_ClockMonitorType*)IP_CE_CMU_FC_0, /* Cmu instance */ 3084 }, 3085 /* CLOCK_IP_CE_CMU_FC_1_INSTANCE */ 3086 { 3087 P3_SYS_MON3_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3088 FXOSC_CLK, /* Name of the reference clock */ 3089 CE_SYS_DIV4_CLK, /* Name of the bus clock */ 3090 (Clock_Ip_ClockMonitorType*)IP_CE_CMU_FC_1, /* Cmu instance */ 3091 }, 3092 /* CLOCK_IP_CE_CMU_FC_2_INSTANCE */ 3093 { 3094 CE_SYS_DIV2_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3095 FXOSC_CLK, /* Name of the reference clock */ 3096 CE_SYS_DIV4_CLK, /* Name of the bus clock */ 3097 (Clock_Ip_ClockMonitorType*)IP_CE_CMU_FC_2, /* Cmu instance */ 3098 }, 3099 /* CLOCK_IP_RTU0_CMU_FC_0_INSTANCE */ 3100 { 3101 RTU0_CORE_MON1_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3102 FXOSC_CLK, /* Name of the reference clock */ 3103 RTU0_REG_INTF_CLK, /* Name of the bus clock */ 3104 (Clock_Ip_ClockMonitorType*)IP_RTU0__CMU_FC_0, /* Cmu instance */ 3105 }, 3106 /* CLOCK_IP_RTU0_CMU_FC_1_INSTANCE */ 3107 { 3108 RTU0_CORE_DIV2_MON1_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3109 FXOSC_CLK, /* Name of the reference clock */ 3110 RTU0_REG_INTF_CLK, /* Name of the bus clock */ 3111 (Clock_Ip_ClockMonitorType*)IP_RTU0__CMU_FC_1, /* Cmu instance */ 3112 }, 3113 /* CLOCK_IP_RTU0_CMU_FC_2_INSTANCE */ 3114 { 3115 RTU0_CORE_DIV2_MON2_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3116 FXOSC_CLK, /* Name of the reference clock */ 3117 RTU0_REG_INTF_CLK, /* Name of the bus clock */ 3118 (Clock_Ip_ClockMonitorType*)IP_RTU0__CMU_FC_2, /* Cmu instance */ 3119 }, 3120 /* CLOCK_IP_RTU0_CMU_FC_3_INSTANCE */ 3121 { 3122 RTU0_CORE_MON2_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3123 FXOSC_CLK, /* Name of the reference clock */ 3124 RTU0_REG_INTF_CLK, /* Name of the bus clock */ 3125 (Clock_Ip_ClockMonitorType*)IP_RTU0__CMU_FC_3, /* Cmu instance */ 3126 }, 3127 /* CLOCK_IP_RTU0_CMU_FC_4_INSTANCE */ 3128 { 3129 RTU0_CORE_DIV2_MON3_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3130 FXOSC_CLK, /* Name of the reference clock */ 3131 RTU0_REG_INTF_CLK, /* Name of the bus clock */ 3132 (Clock_Ip_ClockMonitorType*)IP_RTU0__CMU_FC_4, /* Cmu instance */ 3133 }, 3134 /* CLOCK_IP_RTU1_CMU_FC_0_INSTANCE */ 3135 { 3136 RTU1_CORE_MON1_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3137 FXOSC_CLK, /* Name of the reference clock */ 3138 RTU1_REG_INTF_CLK, /* Name of the bus clock */ 3139 (Clock_Ip_ClockMonitorType*)IP_RTU1__CMU_FC_0, /* Cmu instance */ 3140 }, 3141 /* CLOCK_IP_RTU1_CMU_FC_1_INSTANCE */ 3142 { 3143 RTU1_CORE_DIV2_MON1_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3144 FXOSC_CLK, /* Name of the reference clock */ 3145 RTU1_REG_INTF_CLK, /* Name of the bus clock */ 3146 (Clock_Ip_ClockMonitorType*)IP_RTU1__CMU_FC_1, /* Cmu instance */ 3147 }, 3148 /* CLOCK_IP_RTU1_CMU_FC_2_INSTANCE */ 3149 { 3150 RTU1_CORE_DIV2_MON2_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3151 FXOSC_CLK, /* Name of the reference clock */ 3152 RTU1_REG_INTF_CLK, /* Name of the bus clock */ 3153 (Clock_Ip_ClockMonitorType*)IP_RTU1__CMU_FC_2, /* Cmu instance */ 3154 }, 3155 /* CLOCK_IP_RTU1_CMU_FC_3_INSTANCE */ 3156 { 3157 RTU1_CORE_MON2_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3158 FXOSC_CLK, /* Name of the reference clock */ 3159 RTU1_REG_INTF_CLK, /* Name of the bus clock */ 3160 (Clock_Ip_ClockMonitorType*)IP_RTU1__CMU_FC_3, /* Cmu instance */ 3161 }, 3162 /* CLOCK_IP_RTU1_CMU_FC_4_INSTANCE */ 3163 { 3164 RTU1_CORE_DIV2_MON3_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3165 FXOSC_CLK, /* Name of the reference clock */ 3166 RTU1_REG_INTF_CLK, /* Name of the bus clock */ 3167 (Clock_Ip_ClockMonitorType*)IP_RTU1__CMU_FC_4, /* Cmu instance */ 3168 }, 3169 /* CLOCK_IP_CMU_FC_DEBUG_1_INSTANCE */ 3170 { 3171 P0_CLKOUT_SRC_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3172 FXOSC_CLK, /* Name of the reference clock */ 3173 P0_REG_INTF_CLK, /* Name of the bus clock */ 3174 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_DEBUG_1, /* Cmu instance */ 3175 }, 3176 /* CLOCK_IP_CMU_FC_DEBUG_2_INSTANCE */ 3177 { 3178 P1_CLKOUT_SRC_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3179 FXOSC_CLK, /* Name of the reference clock */ 3180 P1_REG_INTF_CLK, /* Name of the bus clock */ 3181 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_DEBUG_2, /* Cmu instance */ 3182 }, 3183 3184 #if defined(CLOCK_IP_HAS_SYSTEM_DIV2_CLK) 3185 /* CLOCK_IP_CMU_FC_AE_1_INSTANCE */ 3186 { 3187 SYSTEM_DIV2_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3188 FIRC_AE_CLK, /* Name of the reference clock */ 3189 SYSTEM_DIV2_CLK, /* Name of the bus clock */ 3190 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_AE_1, /* Cmu instance */ 3191 }, 3192 #else 3193 { 3194 RESERVED_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3195 RESERVED_CLK, /* Name of the reference clock */ 3196 RESERVED_CLK, /* Name of the bus clock */ 3197 NULL_PTR, /* Cmu instance */ 3198 }, 3199 #endif 3200 3201 #if defined(CLOCK_IP_HAS_SYSTEM_DIV4_MON1_CLK) 3202 /* CLOCK_IP_CMU_FC_AE_2_INSTANCE */ 3203 { 3204 SYSTEM_DIV4_MON1_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3205 FIRC_AE_CLK, /* Name of the reference clock */ 3206 SYSTEM_DIV2_CLK, /* Name of the bus clock */ 3207 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_AE_2, /* Cmu instance */ 3208 }, 3209 #else 3210 { 3211 RESERVED_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3212 RESERVED_CLK, /* Name of the reference clock */ 3213 RESERVED_CLK, /* Name of the bus clock */ 3214 NULL_PTR, /* Cmu instance */ 3215 }, 3216 #endif 3217 3218 #if defined(CLOCK_IP_HAS_SYSTEM_DIV4_MON2_CLK) 3219 /* CLOCK_IP_CMU_FC_AE_3_INSTANCE */ 3220 { 3221 SYSTEM_DIV4_MON2_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3222 FIRC_AE_CLK, /* Name of the reference clock */ 3223 SYSTEM_DIV2_CLK, /* Name of the bus clock */ 3224 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_AE_3, /* Cmu instance */ 3225 }, 3226 #else 3227 { 3228 RESERVED_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3229 RESERVED_CLK, /* Name of the reference clock */ 3230 RESERVED_CLK, /* Name of the bus clock */ 3231 NULL_PTR, /* Cmu instance */ 3232 }, 3233 #endif 3234 }; 3235 3236 3237 Clock_Ip_GprClockControlEnable_Type* const Clock_Ip_apxGprClockControlEnable[CLOCK_IP_PERIPHERAL_GROUPS_COUNT] = 3238 { 3239 (Clock_Ip_GprClockControlEnable_Type*)(IP_GPR0_PCTL_BASE), 3240 (Clock_Ip_GprClockControlEnable_Type*)(IP_GPR1_PCTL_BASE), 3241 NULL_PTR, 3242 (Clock_Ip_GprClockControlEnable_Type*)(IP_GPR3_PCTL_BASE), 3243 (Clock_Ip_GprClockControlEnable_Type*)(IP_GPR4_PCTL_BASE), 3244 (Clock_Ip_GprClockControlEnable_Type*)(IP_GPR5_PCTL_BASE), 3245 (Clock_Ip_GprClockControlEnable_Type*)(IP_GPR6_PCTL_BASE), 3246 }; 3247 3248 const Clock_Ip_ClockNameSourceType Clock_Ip_aeSourceTypeClockName[CLOCK_IP_PRODUCERS_NO] = { 3249 UKNOWN_TYPE, /*!< CLOCK_IS_OFF */ 3250 IRCOSC_TYPE, /*!< FIRC_CLK */ 3251 XOSC_TYPE, /*!< FXOSC_CLK */ 3252 IRCOSC_TYPE, /*!< SIRC_CLK */ 3253 #if defined(CLOCK_IP_HAS_FIRC_AE_CLK) 3254 IRCOSC_TYPE, /*!< FIRC_AE_CLK */ 3255 #endif 3256 PLL_TYPE, /*!< COREPLL_CLK */ 3257 PLL_TYPE, /*!< PERIPHPLL_CLK */ 3258 PLL_TYPE, /*!< DDRPLL_CLK */ 3259 PLL_TYPE, /*!< LFAST0_PLL_CLK */ 3260 PLL_TYPE, /*!< LFAST1_PLL_CLK */ 3261 PLL_TYPE, /*!< CORE_PLL_PHI0_CLK */ 3262 PLL_TYPE, /*!< CORE_PLL_DFS0_CLK */ 3263 PLL_TYPE, /*!< CORE_PLL_DFS1_CLK */ 3264 PLL_TYPE, /*!< CORE_PLL_DFS2_CLK */ 3265 PLL_TYPE, /*!< CORE_PLL_DFS3_CLK */ 3266 PLL_TYPE, /*!< CORE_PLL_DFS4_CLK */ 3267 PLL_TYPE, /*!< CORE_PLL_DFS5_CLK */ 3268 PLL_TYPE, /*!< PERIPH_PLL_PHI0_CLK */ 3269 PLL_TYPE, /*!< PERIPH_PLL_PHI1_CLK */ 3270 PLL_TYPE, /*!< PERIPH_PLL_PHI2_CLK */ 3271 PLL_TYPE, /*!< PERIPH_PLL_PHI3_CLK */ 3272 PLL_TYPE, /*!< PERIPH_PLL_PHI4_CLK */ 3273 PLL_TYPE, /*!< PERIPH_PLL_PHI5_CLK */ 3274 PLL_TYPE, /*!< PERIPH_PLL_PHI6_CLK */ 3275 PLL_TYPE, /*!< PERIPH_PLL_DFS0_CLK */ 3276 PLL_TYPE, /*!< PERIPH_PLL_DFS1_CLK */ 3277 PLL_TYPE, /*!< PERIPH_PLL_DFS2_CLK */ 3278 PLL_TYPE, /*!< PERIPH_PLL_DFS3_CLK */ 3279 PLL_TYPE, /*!< PERIPH_PLL_DFS4_CLK */ 3280 PLL_TYPE, /*!< PERIPH_PLL_DFS5_CLK */ 3281 PLL_TYPE, /*!< DDR_PLL_PHI0_CLK */ 3282 UKNOWN_TYPE, /*!< LFAST0_PLL_PH0_CLK */ 3283 UKNOWN_TYPE, /*!< LFAST1_PLL_PH0_CLK */ 3284 EXT_CLK_TYPE, /*!< ENET_EXT_REF_CLK */ 3285 EXT_CLK_TYPE, /*!< ENET_EXT_TS_CLK */ 3286 EXT_CLK_TYPE, /*!< ENET0_EXT_RX_CLK */ 3287 EXT_CLK_TYPE, /*!< ENET0_EXT_TX_CLK */ 3288 EXT_CLK_TYPE, /*!< ENET1_EXT_RX_CLK */ 3289 EXT_CLK_TYPE, /*!< ENET1_EXT_TX_CLK */ 3290 EXT_CLK_TYPE, /*!< LFAST0_EXT_TX_CLK */ 3291 EXT_CLK_TYPE, /*!< LFAST1_EXT_TX_CLK */ 3292 UKNOWN_TYPE, /*!< DDR_CLK */ 3293 UKNOWN_TYPE, /*!< P0_SYS_CLK */ 3294 UKNOWN_TYPE, /*!< P1_SYS_CLK */ 3295 UKNOWN_TYPE, /*!< P1_SYS_DIV2_CLK */ 3296 UKNOWN_TYPE, /*!< P1_SYS_DIV4_CLK */ 3297 UKNOWN_TYPE, /*!< P2_SYS_CLK */ 3298 UKNOWN_TYPE, /*!< CORE_M33_CLK */ 3299 UKNOWN_TYPE, /*!< P2_SYS_DIV2_CLK */ 3300 UKNOWN_TYPE, /*!< P2_SYS_DIV4_CLK */ 3301 UKNOWN_TYPE, /*!< P3_SYS_CLK */ 3302 UKNOWN_TYPE, /*!< CE_SYS_DIV2_CLK */ 3303 UKNOWN_TYPE, /*!< CE_SYS_DIV4_CLK */ 3304 UKNOWN_TYPE, /*!< P3_SYS_DIV2_NOC_CLK */ 3305 UKNOWN_TYPE, /*!< P3_SYS_DIV4_CLK */ 3306 UKNOWN_TYPE, /*!< P4_SYS_CLK */ 3307 UKNOWN_TYPE, /*!< P4_SYS_DIV2_CLK */ 3308 UKNOWN_TYPE, /*!< HSE_SYS_DIV2_CLK */ 3309 UKNOWN_TYPE, /*!< P5_SYS_CLK */ 3310 UKNOWN_TYPE, /*!< P5_SYS_DIV2_CLK */ 3311 UKNOWN_TYPE, /*!< P5_SYS_DIV4_CLK */ 3312 UKNOWN_TYPE, /*!< P2_MATH_CLK */ 3313 UKNOWN_TYPE, /*!< P2_MATH_DIV3_CLK */ 3314 UKNOWN_TYPE, /*!< GLB_LBIST_CLK */ 3315 UKNOWN_TYPE, /*!< RTU0_CORE_CLK */ 3316 UKNOWN_TYPE, /*!< RTU0_CORE_DIV2_CLK */ 3317 UKNOWN_TYPE, /*!< RTU1_CORE_CLK */ 3318 UKNOWN_TYPE, /*!< RTU1_CORE_DIV2_CLK */ 3319 PLL_TYPE, /*!< P0_PSI5_S_UTIL_CLK */ 3320 PLL_TYPE, /*!< P4_PSI5_S_UTIL_CLK */ 3321 #if defined(CLOCK_IP_HAS_SYSTEM_DRUN_CLK) 3322 UKNOWN_TYPE, /*!< SYSTEM_DRUN_CLK */ 3323 #endif 3324 #if defined(CLOCK_IP_HAS_SYSTEM_RUN0_CLK) 3325 UKNOWN_TYPE, /*!< SYSTEM_RUN0_CLK */ 3326 #endif 3327 #if defined(CLOCK_IP_HAS_SYSTEM_SAFE_CLK) 3328 UKNOWN_TYPE, /*!< SYSTEM_SAFE_CLK */ 3329 #endif 3330 #if defined(CLOCK_IP_HAS_SYSTEM_CLK) 3331 UKNOWN_TYPE, /*!< SYSTEM_CLK */ 3332 #endif 3333 #if defined(CLOCK_IP_HAS_SYSTEM_DIV2_CLK) 3334 UKNOWN_TYPE, /*!< SYSTEM_DIV2_CL */ 3335 #endif 3336 #if defined(CLOCK_IP_HAS_SYSTEM_DIV4_MON1_CLK) 3337 UKNOWN_TYPE, /*!< SYSTEM_DIV4_MON1_CLK */ 3338 #endif 3339 #if defined(CLOCK_IP_HAS_SYSTEM_DIV4_MON2_CLK) 3340 UKNOWN_TYPE, /*!< SYSTEM_DIV4_MON2_CLK */ 3341 #endif 3342 }; 3343 3344 const Clock_Ip_NameType Clock_Ip_aeHwPllName[CLOCK_IP_HARDWARE_PLL_ARRAY_SIZE] = 3345 { 3346 COREPLL_CLK, /* COREPLL_CLK Clock */ 3347 PERIPHPLL_CLK, /* PERIPHPLL_CLK Clock */ 3348 DDRPLL_CLK, /* DDRPLL_CLK Clock */ 3349 LFAST0_PLL_CLK, /* LFAST0_PLL_CLK Clock */ 3350 LFAST1_PLL_CLK, /* LFAST1_PLL_CLK Clock */ 3351 }; 3352 const Clock_Ip_NameType Clock_Ip_aeHwDfsName[CLOCK_IP_NUMBER_OF_HARDWARE_DFS] = 3353 { 3354 COREPLL_DFS0_CLK, /* COREPLL_DFS0_CLK Clock */ 3355 COREPLL_DFS1_CLK, /* COREPLL_DFS1_CLK Clock */ 3356 COREPLL_DFS2_CLK, /* COREPLL_DFS2_CLK Clock */ 3357 COREPLL_DFS3_CLK, /* COREPLL_DFS3_CLK Clock */ 3358 COREPLL_DFS4_CLK, /* COREPLL_DFS4_CLK Clock */ 3359 COREPLL_DFS5_CLK, /* COREPLL_DFS5_CLK Clock */ 3360 PERIPHPLL_DFS0_CLK, /* PERIPHPLL_DFS0_CLK Clock */ 3361 PERIPHPLL_DFS1_CLK, /* PERIPHPLL_DFS1_CLK Clock */ 3362 PERIPHPLL_DFS2_CLK, /* PERIPHPLL_DFS2_CLK Clock */ 3363 PERIPHPLL_DFS3_CLK, /* PERIPHPLL_DFS3_CLK Clock */ 3364 PERIPHPLL_DFS4_CLK, /* PERIPHPLL_DFS4_CLK Clock */ 3365 PERIPHPLL_DFS5_CLK, /* PERIPHPLL_DFS5_CLK Clock */ 3366 3367 }; 3368 3369 3370 const Clock_Ip_ClockExtensionType Clock_Ip_axFeatureExtensions[CLOCK_IP_EXTENSIONS_SIZE] = { 3371 /* Selector value mask Selector value shift Divider value mask Divider value shift */ 3372 {MC_CGM_MUX_0_CSC_SELCTL_MASK, MC_CGM_MUX_0_CSC_SELCTL_SHIFT, MC_CGM_MUX_0_DC_0_DIV_MASK, MC_CGM_MUX_0_DC_0_DIV_SHIFT}, /* CLOCK_IP_DDR_EXTENSION */ 3373 {MC_CGM_MUX_0_CSC_SELCTL_MASK, MC_CGM_MUX_0_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P0_SYS_EXTENSION */ 3374 {MC_CGM_MUX_0_CSC_SELCTL_MASK, MC_CGM_MUX_0_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P1_SYS_EXTENSION */ 3375 {MC_CGM_MUX_0_CSC_SELCTL_MASK, MC_CGM_MUX_0_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P1_SYS_DIV2_EXTENSION */ 3376 {MC_CGM_MUX_0_CSC_SELCTL_MASK, MC_CGM_MUX_0_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P1_SYS_DIV4_EXTENSION */ 3377 {MC_CGM_MUX_0_CSC_SELCTL_MASK, MC_CGM_MUX_0_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P2_SYS_EXTENSION */ 3378 {MC_CGM_MUX_0_CSC_SELCTL_MASK, MC_CGM_MUX_0_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_CORE_M33_EXTENSION */ 3379 {MC_CGM_MUX_0_CSC_SELCTL_MASK, MC_CGM_MUX_0_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P2_SYS_DIV2_EXTENSION */ 3380 {MC_CGM_MUX_0_CSC_SELCTL_MASK, MC_CGM_MUX_0_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P2_SYS_DIV4_EXTENSION */ 3381 {MC_CGM_MUX_0_CSC_SELCTL_MASK, MC_CGM_MUX_0_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P3_SYS_EXTENSION */ 3382 {MC_CGM_MUX_0_CSC_SELCTL_MASK, MC_CGM_MUX_0_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_CE_SYS_DIV2_EXTENSION */ 3383 {MC_CGM_MUX_0_CSC_SELCTL_MASK, MC_CGM_MUX_0_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_CE_SYS_DIV4_EXTENSION */ 3384 {MC_CGM_MUX_0_CSC_SELCTL_MASK, MC_CGM_MUX_0_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P3_SYS_DIV2_NOC_EXTENSION */ 3385 {MC_CGM_MUX_0_CSC_SELCTL_MASK, MC_CGM_MUX_0_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P3_SYS_DIV4_EXTENSION */ 3386 {MC_CGM_MUX_0_CSC_SELCTL_MASK, MC_CGM_MUX_0_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P4_SYS_EXTENSION */ 3387 {MC_CGM_MUX_0_CSC_SELCTL_MASK, MC_CGM_MUX_0_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P4_SYS_DIV2_EXTENSION */ 3388 {MC_CGM_MUX_0_CSC_SELCTL_MASK, MC_CGM_MUX_0_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_HSE_SYS_DIV2_EXTENSION */ 3389 {MC_CGM_MUX_0_CSC_SELCTL_MASK, MC_CGM_MUX_0_CSC_SELCTL_SHIFT, MC_CGM_MUX_0_DC_0_DIV_MASK, MC_CGM_MUX_0_DC_0_DIV_SHIFT}, /* CLOCK_IP_P5_SYS_EXTENSION */ 3390 {MC_CGM_MUX_0_CSC_SELCTL_MASK, MC_CGM_MUX_0_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P5_SYS_DIV2_EXTENSION */ 3391 {MC_CGM_MUX_0_CSC_SELCTL_MASK, MC_CGM_MUX_0_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P5_SYS_DIV4_EXTENSION */ 3392 {MC_CGM_MUX_3_CSC_SELCTL_MASK, MC_CGM_MUX_3_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P2_MATH_EXTENSION */ 3393 {MC_CGM_MUX_3_CSC_SELCTL_MASK, MC_CGM_MUX_3_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P2_MATH_DIV3_EXTENSION */ 3394 {MC_CGM_MUX_8_CSC_SELCTL_MASK, MC_CGM_MUX_8_CSC_SELCTL_SHIFT, MC_CGM_MUX_8_DC_0_DIV_MASK, MC_CGM_MUX_8_DC_0_DIV_SHIFT}, /* CLOCK_IP_GLB_LBIST_EXTENSION */ 3395 {RTU_MC_CGM_MUX_0_CSC_SELCTL_MASK, RTU_MC_CGM_MUX_0_CSC_SELCTL_SHIFT, RTU_MC_CGM_MUX_0_DC_0_DIV_MASK, RTU_MC_CGM_MUX_0_DC_0_DIV_SHIFT}, /* CLOCK_IP_RTU0_CORE_EXTENSION */ 3396 {RTU_MC_CGM_MUX_0_CSC_SELCTL_MASK, RTU_MC_CGM_MUX_0_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_RTU0_CORE_DIV2_EXTENSION */ 3397 {RTU_MC_CGM_MUX_0_CSC_SELCTL_MASK, RTU_MC_CGM_MUX_0_CSC_SELCTL_SHIFT, RTU_MC_CGM_MUX_0_DC_0_DIV_MASK, RTU_MC_CGM_MUX_0_DC_0_DIV_SHIFT}, /* CLOCK_IP_RTU1_CORE_EXTENSION */ 3398 {RTU_MC_CGM_MUX_0_CSC_SELCTL_MASK, RTU_MC_CGM_MUX_0_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_RTU1_CORE_DIV2_EXTENSION */ 3399 {MC_CGM_MUX_2_CSC_SELCTL_MASK, MC_CGM_MUX_2_CSC_SELCTL_SHIFT, MC_CGM_MUX_2_DC_3_DIV_MASK, MC_CGM_MUX_2_DC_3_DIV_SHIFT}, /* CLOCK_IP_P0_PSI5_S_UTIL_EXTENSION */ 3400 {MC_CGM_MUX_2_CSC_SELCTL_MASK, MC_CGM_MUX_2_CSC_SELCTL_SHIFT, MC_CGM_MUX_2_DC_3_DIV_MASK, MC_CGM_MUX_2_DC_3_DIV_SHIFT}, /* CLOCK_IP_P4_PSI5_S_UTIL_EXTENSION */ 3401 {MC_CGM_MUX_10_CSC_SELCTL_MASK, MC_CGM_MUX_10_CSC_SELCTL_SHIFT, MC_CGM_MUX_10_DC_0_DIV_MASK, MC_CGM_MUX_10_DC_0_DIV_SHIFT}, /* CLOCK_IP_CLKOUT0_EXTENSION */ 3402 {MC_CGM_MUX_10_CSC_SELCTL_MASK, MC_CGM_MUX_10_CSC_SELCTL_SHIFT, MC_CGM_MUX_10_DC_0_DIV_MASK, MC_CGM_MUX_10_DC_0_DIV_SHIFT}, /* CLOCK_IP_CLKOUT1_EXTENSION */ 3403 {MC_CGM_MUX_6_CSC_SELCTL_MASK, MC_CGM_MUX_6_CSC_SELCTL_SHIFT, MC_CGM_MUX_6_DC_0_DIV_MASK, MC_CGM_MUX_6_DC_0_DIV_SHIFT}, /* CLOCK_IP_CLKOUT2_EXTENSION */ 3404 {MC_CGM_MUX_4_CSC_SELCTL_MASK, MC_CGM_MUX_4_CSC_SELCTL_SHIFT, MC_CGM_MUX_4_DC_0_DIV_MASK, MC_CGM_MUX_4_DC_0_DIV_SHIFT}, /* CLOCK_IP_CLKOUT3_EXTENSION */ 3405 {MC_CGM_MUX_4_CSC_SELCTL_MASK, MC_CGM_MUX_4_CSC_SELCTL_SHIFT, MC_CGM_MUX_4_DC_0_DIV_MASK, MC_CGM_MUX_4_DC_0_DIV_SHIFT}, /* CLOCK_IP_CLKOUT4_EXTENSION */ 3406 {MC_CGM_MUX_6_CSC_SELCTL_MASK, MC_CGM_MUX_6_CSC_SELCTL_SHIFT, MC_CGM_MUX_6_DC_0_DIV_MASK, MC_CGM_MUX_6_DC_0_DIV_SHIFT}, /* P1_ETH0_TX_MII_EXTENSION */ 3407 {MC_CGM_MUX_3_CSC_SELCTL_MASK, MC_CGM_MUX_3_CSC_SELCTL_SHIFT, MC_CGM_MUX_3_DC_0_DIV_MASK, MC_CGM_MUX_3_DC_0_DIV_SHIFT}, /* CLOCK_IP_P3_CAN_PE_EXTENSION */ 3408 {MC_CGM_MUX_6_CSC_SELCTL_MASK, MC_CGM_MUX_6_CSC_SELCTL_SHIFT, MC_CGM_MUX_6_DC_0_DIV_MASK, MC_CGM_MUX_6_DC_0_DIV_SHIFT}, /* CLOCK_IP_P0_FR_PE_EXTENSION */ 3409 {MC_CGM_MUX_4_CSC_SELCTL_MASK, MC_CGM_MUX_4_CSC_SELCTL_SHIFT, MC_CGM_MUX_4_DC_0_DIV_MASK, MC_CGM_MUX_4_DC_0_DIV_SHIFT}, /* CLOCK_IP_P0_LIN_BAUD_EXTENSION */ 3410 {MC_CGM_MUX_4_CSC_SELCTL_MASK, MC_CGM_MUX_4_CSC_SELCTL_SHIFT, MC_CGM_MUX_4_DC_0_DIV_MASK, MC_CGM_MUX_4_DC_0_DIV_SHIFT}, /* CLOCK_IP_P1_LIN_BAUD_EXTENSION */ 3411 {MC_CGM_MUX_8_CSC_SELCTL_MASK, MC_CGM_MUX_8_CSC_SELCTL_SHIFT, MC_CGM_MUX_8_DC_0_DIV_MASK, MC_CGM_MUX_8_DC_0_DIV_SHIFT}, /* CLOCK_IP_P4_LIN_BAUD_EXTENSION */ 3412 {MC_CGM_MUX_2_CSC_SELCTL_MASK, MC_CGM_MUX_2_CSC_SELCTL_SHIFT, MC_CGM_MUX_2_DC_0_DIV_MASK, MC_CGM_MUX_2_DC_0_DIV_SHIFT}, /* CLOCK_IP_P5_LIN_BAUD_EXTENSION */ 3413 {GPR0_CLKOUT0SEL_MUXSEL_MASK, GPR0_CLKOUT0SEL_MUXSEL_SHIFT, 0U, 0U}, /* CLOCK_IP_P0_CLKOUT_SRC_EXTENSION */ 3414 {MC_CGM_MUX_9_CSC_SELCTL_MASK, MC_CGM_MUX_9_CSC_SELCTL_SHIFT, MC_CGM_MUX_9_DC_0_DIV_MASK, MC_CGM_MUX_9_DC_0_DIV_SHIFT}, /* CLOCK_IP_P0_CTU_PER_EXTENSION */ 3415 {MC_CGM_MUX_7_CSC_SELCTL_MASK, MC_CGM_MUX_7_CSC_SELCTL_SHIFT, MC_CGM_MUX_7_DC_1_DIV_MASK, MC_CGM_MUX_7_DC_1_DIV_SHIFT}, /* CLOCK_IP_P0_DSPI_MSC_EXTENSION */ 3416 {MC_CGM_MUX_9_CSC_SELCTL_MASK, MC_CGM_MUX_9_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P0_EMIOS_LCU_EXTENSION */ 3417 {MC_CGM_MUX_7_CSC_SELCTL_MASK, MC_CGM_MUX_7_CSC_SELCTL_SHIFT, MC_CGM_MUX_7_DC_0_DIV_MASK, MC_CGM_MUX_7_DC_0_DIV_SHIFT}, /* CLOCK_IP_P0_GTM_EXTENSION */ 3418 {MC_CGM_MUX_7_CSC_SELCTL_MASK, MC_CGM_MUX_7_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P0_GTM_NOC_EXTENSION */ 3419 {MC_CGM_MUX_7_CSC_SELCTL_MASK, MC_CGM_MUX_7_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P0_GTM_TS_EXTENSION */ 3420 {MC_CGM_MUX_4_CSC_SELCTL_MASK, MC_CGM_MUX_4_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P0_LIN_EXTENSION */ 3421 {MC_CGM_MUX_7_CSC_SELCTL_MASK, MC_CGM_MUX_7_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P0_NANO_EXTENSION */ 3422 {MC_CGM_MUX_2_CSC_SELCTL_MASK, MC_CGM_MUX_2_CSC_SELCTL_SHIFT, MC_CGM_MUX_2_DC_1_DIV_MASK, MC_CGM_MUX_2_DC_1_DIV_SHIFT}, /* CLOCK_IP_P0_PSI5_125K_EXTENSION */ 3423 {MC_CGM_MUX_2_CSC_SELCTL_MASK, MC_CGM_MUX_2_CSC_SELCTL_SHIFT, MC_CGM_MUX_2_DC_2_DIV_MASK, MC_CGM_MUX_2_DC_2_DIV_SHIFT}, /* CLOCK_IP_P0_PSI5_189K_EXTENSION */ 3424 {MC_CGM_MUX_2_CSC_SELCTL_MASK, MC_CGM_MUX_2_CSC_SELCTL_SHIFT, MC_CGM_MUX_2_DC_5_DIV_MASK, MC_CGM_MUX_2_DC_5_DIV_SHIFT}, /* CLOCK_IP_P0_PSI5_S_BAUD_EXTENSION */ 3425 {MC_CGM_MUX_2_CSC_SELCTL_MASK, MC_CGM_MUX_2_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P0_PSI5_S_CORE_EXTENSION */ 3426 {MC_CGM_MUX_3_CSC_SELCTL_MASK, MC_CGM_MUX_3_CSC_SELCTL_SHIFT, MC_CGM_MUX_3_DC_0_DIV_MASK, MC_CGM_MUX_3_DC_0_DIV_SHIFT}, /* CLOCK_IP_P0_PSI5_S_TRIG0_EXTENSION */ 3427 {MC_CGM_MUX_3_CSC_SELCTL_MASK, MC_CGM_MUX_3_CSC_SELCTL_SHIFT, MC_CGM_MUX_3_DC_1_DIV_MASK, MC_CGM_MUX_3_DC_1_DIV_SHIFT}, /* CLOCK_IP_P0_PSI5_S_TRIG1_EXTENSION */ 3428 {MC_CGM_MUX_3_CSC_SELCTL_MASK, MC_CGM_MUX_3_CSC_SELCTL_SHIFT, MC_CGM_MUX_3_DC_2_DIV_MASK, MC_CGM_MUX_3_DC_2_DIV_SHIFT}, /* CLOCK_IP_P0_PSI5_S_TRIG2_EXTENSION */ 3429 {MC_CGM_MUX_3_CSC_SELCTL_MASK, MC_CGM_MUX_3_CSC_SELCTL_SHIFT, MC_CGM_MUX_3_DC_3_DIV_MASK, MC_CGM_MUX_3_DC_3_DIV_SHIFT}, /* CLOCK_IP_P0_PSI5_S_TRIG3_EXTENSION */ 3430 {MC_CGM_MUX_2_CSC_SELCTL_MASK, MC_CGM_MUX_2_CSC_SELCTL_SHIFT, MC_CGM_MUX_2_DC_4_DIV_MASK, MC_CGM_MUX_2_DC_4_DIV_SHIFT}, /* CLOCK_IP_P0_PSI5_S_UART_EXTENSION */ 3431 {MC_CGM_MUX_3_CSC_SELCTL_MASK, MC_CGM_MUX_3_CSC_SELCTL_SHIFT, MC_CGM_MUX_3_DC_4_DIV_MASK, MC_CGM_MUX_3_DC_4_DIV_SHIFT}, /* CLOCK_IP_P0_PSI5_S_WDOG0_EXTENSION */ 3432 {MC_CGM_MUX_3_CSC_SELCTL_MASK, MC_CGM_MUX_3_CSC_SELCTL_SHIFT, MC_CGM_MUX_3_DC_5_DIV_MASK, MC_CGM_MUX_3_DC_5_DIV_SHIFT}, /* CLOCK_IP_P0_PSI5_S_WDOG1_EXTENSION */ 3433 {MC_CGM_MUX_3_CSC_SELCTL_MASK, MC_CGM_MUX_3_CSC_SELCTL_SHIFT, MC_CGM_MUX_3_DC_6_DIV_MASK, MC_CGM_MUX_3_DC_6_DIV_SHIFT}, /* CLOCK_IP_P0_PSI5_S_WDOG2_EXTENSION */ 3434 {MC_CGM_MUX_3_CSC_SELCTL_MASK, MC_CGM_MUX_3_CSC_SELCTL_SHIFT, MC_CGM_MUX_3_DC_7_DIV_MASK, MC_CGM_MUX_3_DC_7_DIV_SHIFT}, /* CLOCK_IP_P0_PSI5_S_WDOG3_EXTENSION */ 3435 {MC_CGM_MUX_1_CSC_SELCTL_MASK, MC_CGM_MUX_1_CSC_SELCTL_SHIFT, MC_CGM_MUX_1_DC_1_DIV_MASK, MC_CGM_MUX_1_DC_1_DIV_SHIFT}, /* CLOCK_IP_P0_REG_INTF_2X_EXTENSION */ 3436 {MC_CGM_MUX_1_CSC_SELCTL_MASK, MC_CGM_MUX_1_CSC_SELCTL_SHIFT, MC_CGM_MUX_1_DC_0_DIV_MASK, MC_CGM_MUX_1_DC_0_DIV_SHIFT}, /* CLOCK_IP_P0_REG_INTF_EXTENSION */ 3437 {GPR1_CLKOUT1SEL_MUXSEL_MASK, GPR1_CLKOUT1SEL_MUXSEL_SHIFT, 0U, 0U}, /* CLOCK_IP_P1_CLKOUT_SRC_EXTENSION */ 3438 {MC_CGM_MUX_3_CSC_SELCTL_MASK, MC_CGM_MUX_3_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P1_DSPI60_EXTENSION */ 3439 {MC_CGM_MUX_11_CSC_SELCTL_MASK, MC_CGM_MUX_11_CSC_SELCTL_SHIFT, MC_CGM_MUX_11_DC_0_DIV_MASK, MC_CGM_MUX_11_DC_0_DIV_SHIFT}, /* CLOCK_IP_P1_LFAST0_REF_EXTENSION */ 3440 {MC_CGM_MUX_12_CSC_SELCTL_MASK, MC_CGM_MUX_12_CSC_SELCTL_SHIFT, MC_CGM_MUX_11_DC_0_DIV_MASK, MC_CGM_MUX_12_DC_0_DIV_SHIFT}, /* CLOCK_IP_P1_LFAST1_REF_EXTENSION */ 3441 {MC_CGM_MUX_14_CSC_SELCTL_MASK, MC_CGM_MUX_14_CSC_SELCTL_SHIFT, MC_CGM_MUX_14_DC_0_DIV_MASK, MC_CGM_MUX_14_DC_0_DIV_SHIFT}, /* CLOCK_IP_P1_NETC_AXI_EXTENSION */ 3442 {MC_CGM_MUX_4_CSC_SELCTL_MASK, MC_CGM_MUX_4_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P1_LIN_EXTENSION */ 3443 {MC_CGM_MUX_5_CSC_SELCTL_MASK, MC_CGM_MUX_5_CSC_SELCTL_SHIFT, MC_CGM_MUX_5_DC_0_DIV_MASK, MC_CGM_MUX_5_DC_0_DIV_SHIFT}, /* P1_ETH_TS_EXTENSION */ 3444 {MC_CGM_MUX_5_CSC_SELCTL_MASK, MC_CGM_MUX_5_CSC_SELCTL_SHIFT, MC_CGM_MUX_5_DC_0_DIV_MASK, MC_CGM_MUX_5_DC_0_DIV_SHIFT}, /* P1_ETH_TS_DIV4_EXTENSION */ 3445 {MC_CGM_MUX_7_CSC_SELCTL_MASK, MC_CGM_MUX_7_CSC_SELCTL_SHIFT, MC_CGM_MUX_7_DC_2_DIV_MASK, MC_CGM_MUX_7_DC_2_DIV_SHIFT}, /* P1_ETH0_REF_RMII_EXTENSION */ 3446 {MC_CGM_MUX_7_CSC_SELCTL_MASK, MC_CGM_MUX_7_CSC_SELCTL_SHIFT, MC_CGM_MUX_7_DC_0_DIV_MASK, MC_CGM_MUX_7_DC_0_DIV_SHIFT}, /* P1_ETH0_RX_MII_EXTENSION */ 3447 {MC_CGM_MUX_7_CSC_SELCTL_MASK, MC_CGM_MUX_7_CSC_SELCTL_SHIFT, MC_CGM_MUX_7_DC_1_DIV_MASK, MC_CGM_MUX_7_DC_1_DIV_SHIFT}, /* P1_ETH0_RX_RGMII_EXTENSION */ 3448 {MC_CGM_MUX_6_CSC_SELCTL_MASK, MC_CGM_MUX_6_CSC_SELCTL_SHIFT, MC_CGM_MUX_6_DC_1_DIV_MASK, MC_CGM_MUX_6_DC_1_DIV_SHIFT}, /* P1_ETH0_TX_RGMII_EXTENSION */ 3449 {MC_CGM_MUX_6_CSC_SELCTL_MASK, MC_CGM_MUX_6_CSC_SELCTL_SHIFT, MC_CGM_MUX_6_DC_1_DIV_MASK, MC_CGM_MUX_6_DC_1_DIV_SHIFT}, /* P1_ETH0_TX_RGMII_LPBK_EXTENION */ 3450 {MC_CGM_MUX_9_CSC_SELCTL_MASK, MC_CGM_MUX_9_CSC_SELCTL_SHIFT, MC_CGM_MUX_9_DC_2_DIV_MASK, MC_CGM_MUX_9_DC_2_DIV_SHIFT}, /* P1_ETH1_REF_RMII_EXTENSION */ 3451 {MC_CGM_MUX_9_CSC_SELCTL_MASK, MC_CGM_MUX_9_CSC_SELCTL_SHIFT, MC_CGM_MUX_9_DC_0_DIV_MASK, MC_CGM_MUX_9_DC_0_DIV_SHIFT}, /* P1_ETH1_RX_MII_EXTENSION */ 3452 {MC_CGM_MUX_9_CSC_SELCTL_MASK, MC_CGM_MUX_9_CSC_SELCTL_SHIFT, MC_CGM_MUX_9_DC_1_DIV_MASK, MC_CGM_MUX_9_DC_1_DIV_SHIFT}, /* P1_ETH1_RX_RGMII_EXTENSION */ 3453 {MC_CGM_MUX_8_CSC_SELCTL_MASK, MC_CGM_MUX_8_CSC_SELCTL_SHIFT, MC_CGM_MUX_8_DC_0_DIV_MASK, MC_CGM_MUX_8_DC_0_DIV_SHIFT}, /* P1_ETH1_TX_MII_EXTENSION */ 3454 {MC_CGM_MUX_8_CSC_SELCTL_MASK, MC_CGM_MUX_8_CSC_SELCTL_SHIFT, MC_CGM_MUX_8_DC_1_DIV_MASK, MC_CGM_MUX_8_DC_1_DIV_SHIFT}, /* P1_ETH1_TX_RGMII_EXTENSION */ 3455 {MC_CGM_MUX_8_CSC_SELCTL_MASK, MC_CGM_MUX_8_CSC_SELCTL_SHIFT, MC_CGM_MUX_8_DC_1_DIV_MASK, MC_CGM_MUX_8_DC_1_DIV_SHIFT}, /* P1_ETH1_TX_RGMII_LPBK_EXTENSION */ 3456 {MC_CGM_MUX_1_CSC_SELCTL_MASK, MC_CGM_MUX_1_CSC_SELCTL_SHIFT, MC_CGM_MUX_1_DC_0_DIV_MASK, MC_CGM_MUX_1_DC_0_DIV_SHIFT}, /* CLOCK_IP_P1_REG_INTF_EXTENSION */ 3457 {MC_CGM_MUX_2_CSC_SELCTL_MASK, MC_CGM_MUX_2_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P2_DBG_ATB_EXTENSION */ 3458 {MC_CGM_MUX_1_CSC_SELCTL_MASK, MC_CGM_MUX_1_CSC_SELCTL_SHIFT, MC_CGM_MUX_1_DC_0_DIV_MASK, MC_CGM_MUX_1_DC_0_DIV_SHIFT}, /* CLOCK_IP_P2_REG_INTF_EXTENSION */ 3459 {MC_CGM_MUX_2_CSC_SELCTL_MASK, MC_CGM_MUX_2_CSC_SELCTL_SHIFT, MC_CGM_MUX_2_DC_1_DIV_MASK, MC_CGM_MUX_2_DC_1_DIV_SHIFT}, /* CLOCK_IP_P3_AES_EXTENSION */ 3460 {GPR3_CLKOUT4SEL_MUXSEL_MASK, GPR3_CLKOUT4SEL_MUXSEL_SHIFT, 0U, 0U}, /* CLOCK_IP_P3_CLKOUT_SRC_EXTENSION */ 3461 {MC_CGM_MUX_2_CSC_SELCTL_MASK, MC_CGM_MUX_2_CSC_SELCTL_SHIFT, MC_CGM_MUX_2_DC_0_DIV_MASK, MC_CGM_MUX_2_DC_0_DIV_SHIFT}, /* CLOCK_IP_P3_DBG_TS_EXTENSION */ 3462 {MC_CGM_MUX_1_CSC_SELCTL_MASK, MC_CGM_MUX_1_CSC_SELCTL_SHIFT, MC_CGM_MUX_1_DC_0_DIV_MASK, MC_CGM_MUX_1_DC_0_DIV_SHIFT}, /* CLOCK_IP_P3_REG_INTF_EXTENSION */ 3463 {GPR4_CLKOUT2SEL_MUXSEL_MASK, GPR4_CLKOUT2SEL_MUXSEL_SHIFT, 0U, 0U}, /* CLOCK_IP_P4_CLKOUT_SRC_EXTENSION */ 3464 {MC_CGM_MUX_5_CSC_SELCTL_MASK, MC_CGM_MUX_5_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P4_DSPI60_EXTENSION */ 3465 {MC_CGM_MUX_11_CSC_SELCTL_MASK, MC_CGM_MUX_11_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P4_EMIOS_LCU_EXTENSION */ 3466 {MC_CGM_MUX_8_CSC_SELCTL_MASK, MC_CGM_MUX_8_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P4_LIN_EXTENSION */ 3467 {MC_CGM_MUX_2_CSC_SELCTL_MASK, MC_CGM_MUX_2_CSC_SELCTL_SHIFT, MC_CGM_MUX_2_DC_1_DIV_MASK, MC_CGM_MUX_2_DC_1_DIV_SHIFT}, /* CLOCK_IP_P4_PSI5_125K_EXTENSION */ 3468 {MC_CGM_MUX_2_CSC_SELCTL_MASK, MC_CGM_MUX_2_CSC_SELCTL_SHIFT, MC_CGM_MUX_2_DC_2_DIV_MASK, MC_CGM_MUX_2_DC_2_DIV_SHIFT}, /* CLOCK_IP_P4_PSI5_189K_EXTENSION */ 3469 {MC_CGM_MUX_2_CSC_SELCTL_MASK, MC_CGM_MUX_2_CSC_SELCTL_SHIFT, MC_CGM_MUX_2_DC_5_DIV_MASK, MC_CGM_MUX_2_DC_5_DIV_SHIFT}, /* CLOCK_IP_P4_PSI5_S_BAUD_EXTENSION */ 3470 {MC_CGM_MUX_2_CSC_SELCTL_MASK, MC_CGM_MUX_2_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P4_PSI5_S_CORE_EXTENSION */ 3471 {MC_CGM_MUX_3_CSC_SELCTL_MASK, MC_CGM_MUX_3_CSC_SELCTL_SHIFT, MC_CGM_MUX_3_DC_0_DIV_MASK, MC_CGM_MUX_3_DC_0_DIV_SHIFT}, /* CLOCK_IP_P4_PSI5_S_TRIG0_EXTENSION */ 3472 {MC_CGM_MUX_3_CSC_SELCTL_MASK, MC_CGM_MUX_3_CSC_SELCTL_SHIFT, MC_CGM_MUX_3_DC_1_DIV_MASK, MC_CGM_MUX_3_DC_1_DIV_SHIFT}, /* CLOCK_IP_P4_PSI5_S_TRIG1_EXTENSION */ 3473 {MC_CGM_MUX_3_CSC_SELCTL_MASK, MC_CGM_MUX_3_CSC_SELCTL_SHIFT, MC_CGM_MUX_3_DC_2_DIV_MASK, MC_CGM_MUX_3_DC_2_DIV_SHIFT}, /* CLOCK_IP_P4_PSI5_S_TRIG2_EXTENSION */ 3474 {MC_CGM_MUX_3_CSC_SELCTL_MASK, MC_CGM_MUX_3_CSC_SELCTL_SHIFT, MC_CGM_MUX_3_DC_3_DIV_MASK, MC_CGM_MUX_3_DC_3_DIV_SHIFT}, /* CLOCK_IP_P4_PSI5_S_TRIG3_EXTENSION */ 3475 {MC_CGM_MUX_2_CSC_SELCTL_MASK, MC_CGM_MUX_2_CSC_SELCTL_SHIFT, MC_CGM_MUX_2_DC_4_DIV_MASK, MC_CGM_MUX_2_DC_4_DIV_SHIFT}, /* CLOCK_IP_P4_PSI5_S_UART_EXTENSION */ 3476 {MC_CGM_MUX_3_CSC_SELCTL_MASK, MC_CGM_MUX_3_CSC_SELCTL_SHIFT, MC_CGM_MUX_3_DC_4_DIV_MASK, MC_CGM_MUX_3_DC_4_DIV_SHIFT}, /* CLOCK_IP_P4_PSI5_S_WDOG0_EXTENSION */ 3477 {MC_CGM_MUX_3_CSC_SELCTL_MASK, MC_CGM_MUX_3_CSC_SELCTL_SHIFT, MC_CGM_MUX_3_DC_5_DIV_MASK, MC_CGM_MUX_3_DC_5_DIV_SHIFT}, /* CLOCK_IP_P4_PSI5_S_WDOG1_EXTENSION */ 3478 {MC_CGM_MUX_3_CSC_SELCTL_MASK, MC_CGM_MUX_3_CSC_SELCTL_SHIFT, MC_CGM_MUX_3_DC_6_DIV_MASK, MC_CGM_MUX_3_DC_6_DIV_SHIFT}, /* CLOCK_IP_P4_PSI5_S_WDOG2_EXTENSION */ 3479 {MC_CGM_MUX_3_CSC_SELCTL_MASK, MC_CGM_MUX_3_CSC_SELCTL_SHIFT, MC_CGM_MUX_3_DC_7_DIV_MASK, MC_CGM_MUX_3_DC_7_DIV_SHIFT}, /* CLOCK_IP_P4_PSI5_S_WDOG3_EXTENSION */ 3480 {MC_CGM_MUX_7_CSC_SELCTL_MASK, MC_CGM_MUX_7_CSC_SELCTL_SHIFT, MC_CGM_MUX_7_DC_0_DIV_MASK, MC_CGM_MUX_7_DC_0_DIV_SHIFT}, /* CLOCK_IP_P4_QSPI0_2X_EXTENSION */ 3481 {MC_CGM_MUX_7_CSC_SELCTL_MASK, MC_CGM_MUX_7_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P4_QSPI0_1X_EXTENSION */ 3482 {MC_CGM_MUX_9_CSC_SELCTL_MASK, MC_CGM_MUX_9_CSC_SELCTL_SHIFT, MC_CGM_MUX_9_DC_1_DIV_MASK, MC_CGM_MUX_9_DC_1_DIV_SHIFT}, /* CLOCK_IP_P4_QSPI1_2X_EXTENSION */ 3483 {MC_CGM_MUX_9_CSC_SELCTL_MASK, MC_CGM_MUX_9_CSC_SELCTL_SHIFT, MC_CGM_MUX_9_DC_1_DIV_MASK, MC_CGM_MUX_9_DC_1_DIV_SHIFT}, /* CLOCK_IP_P4_QSPI1_1X_EXTENSION */ 3484 {MC_CGM_MUX_1_CSC_SELCTL_MASK, MC_CGM_MUX_1_CSC_SELCTL_SHIFT, MC_CGM_MUX_1_DC_1_DIV_MASK, MC_CGM_MUX_1_DC_1_DIV_SHIFT}, /* CLOCK_IP_P4_REG_INTF_2X_EXTENSION */ 3485 {MC_CGM_MUX_1_CSC_SELCTL_MASK, MC_CGM_MUX_1_CSC_SELCTL_SHIFT, MC_CGM_MUX_1_DC_0_DIV_MASK, MC_CGM_MUX_1_DC_0_DIV_SHIFT}, /* CLOCK_IP_P4_REG_INTF_EXTENSION */ 3486 {MC_CGM_MUX_10_CSC_SELCTL_MASK, MC_CGM_MUX_10_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P4_SDHC_IP_EXTENSION */ 3487 {MC_CGM_MUX_10_CSC_SELCTL_MASK, MC_CGM_MUX_10_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P4_SDHC_IP_DIV2_EXTENSION */ 3488 {MC_CGM_MUX_5_CSC_SELCTL_MASK, MC_CGM_MUX_5_CSC_SELCTL_SHIFT, MC_CGM_MUX_5_DC_0_DIV_MASK, MC_CGM_MUX_5_DC_0_DIV_SHIFT}, /* CLOCK_IP_P5_AE_EXTENSION */ 3489 {MC_CGM_MUX_5_CSC_SELCTL_MASK, MC_CGM_MUX_5_CSC_SELCTL_SHIFT, MC_CGM_MUX_5_DC_1_DIV_MASK, MC_CGM_MUX_5_DC_1_DIV_SHIFT}, /* CLOCK_IP_P5_CANXL_PE_EXTENSION */ 3490 {MC_CGM_MUX_5_CSC_SELCTL_MASK, MC_CGM_MUX_5_CSC_SELCTL_SHIFT, MC_CGM_MUX_5_DC_2_DIV_MASK, MC_CGM_MUX_5_DC_2_DIV_SHIFT}, /* CLOCK_IP_P5_CANXL_CHI_EXTENSION */ 3491 {GPR5_CLKOUT3SEL_MUXSEL_MASK, GPR5_CLKOUT3SEL_MUXSEL_SHIFT, 0U, 0U}, /* CLOCK_IP_P5_CLKOUT_SRC_EXTENSION */ 3492 {MC_CGM_MUX_2_CSC_SELCTL_MASK, MC_CGM_MUX_2_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P5_LIN_EXTENSION */ 3493 {MC_CGM_MUX_1_CSC_SELCTL_MASK, MC_CGM_MUX_1_CSC_SELCTL_SHIFT, MC_CGM_MUX_1_DC_0_DIV_MASK, MC_CGM_MUX_1_DC_0_DIV_SHIFT}, /* CLOCK_IP_P5_REG_INTF_EXTENSION */ 3494 {MC_CGM_MUX_1_CSC_SELCTL_MASK, MC_CGM_MUX_1_CSC_SELCTL_SHIFT, MC_CGM_MUX_1_DC_0_DIV_MASK, MC_CGM_MUX_1_DC_0_DIV_SHIFT}, /* CLOCK_IP_P6_REG_INTF_EXTENSION */ 3495 {MC_CGM_MUX_2_CSC_SELCTL_MASK, MC_CGM_MUX_2_CSC_SELCTL_SHIFT, MC_CGM_MUX_2_DC_0_DIV_MASK, MC_CGM_MUX_2_DC_0_DIV_SHIFT}, /* CLOCK_IP_P0_PSI5_1US_EXTENSION */ 3496 {MC_CGM_MUX_2_CSC_SELCTL_MASK, MC_CGM_MUX_2_CSC_SELCTL_SHIFT, MC_CGM_MUX_2_DC_0_DIV_MASK, MC_CGM_MUX_2_DC_0_DIV_SHIFT}, /* CLOCK_IP_P4_PSI5_1US_EXTENSION */ 3497 {RTU_MC_CGM_MUX_1_CSC_SELCTL_MASK, RTU_MC_CGM_MUX_1_CSC_SELCTL_SHIFT, RTU_MC_CGM_MUX_1_DC_0_DIV_MASK, RTU_MC_CGM_MUX_1_DC_0_DIV_SHIFT}, /* CLOCK_IP_RTU0_REG_INTF_EXTENSION */ 3498 {RTU_MC_CGM_MUX_1_CSC_SELCTL_MASK, RTU_MC_CGM_MUX_1_CSC_SELCTL_SHIFT, RTU_MC_CGM_MUX_1_DC_0_DIV_MASK, RTU_MC_CGM_MUX_1_DC_0_DIV_SHIFT}, /* CLOCK_IP_RTU1_REG_INTF_EXTENSION */ 3499 {MC_CGM_MUX_9_CSC_SELCTL_MASK, MC_CGM_MUX_9_CSC_SELCTL_SHIFT, MC_CGM_MUX_9_DC_0_DIV_MASK, MC_CGM_MUX_9_DC_0_DIV_SHIFT}, /* CLOCK_IP_P4_SDHC_EXTENSION */ 3500 {MC_CGM_MUX_5_CSC_SELCTL_MASK, MC_CGM_MUX_5_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P0_DSPI_EXTENSION */ 3501 {MC_CGM_MUX_2_CSC_SELCTL_MASK, MC_CGM_MUX_2_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P1_DSPI_EXTENSION */ 3502 {MC_CGM_MUX_4_CSC_SELCTL_MASK, MC_CGM_MUX_4_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P4_DSPI_EXTENSION */ 3503 {MC_CGM_MUX_3_CSC_SELCTL_MASK, MC_CGM_MUX_3_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P5_DSPI_EXTENSION */ 3504 }; 3505 3506 Clock_Ip_GateInfoType const Clock_Ip_axGateInfo[CLOCK_IP_GATE_INFO_SIZE] = { 3507 /* Group index Gate index */ 3508 {CLOCK_IP_GROUP_6_INDEX, CLOCK_IP_GATE_0_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P6_GROUP_0_BIT0_INDEX */ 3509 {CLOCK_IP_GROUP_0_INDEX, CLOCK_IP_GATE_13_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P0_GROUP_13_BIT0_INDEX */ 3510 {CLOCK_IP_GROUP_0_INDEX, CLOCK_IP_GATE_12_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P0_GROUP_12_BIT0_INDEX */ 3511 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_1_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_1_BIT0_INDEX */ 3512 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_27_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_27_BIT0_INDEX */ 3513 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_28_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_28_BIT0_INDEX */ 3514 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_29_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_29_BIT0_INDEX */ 3515 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_30_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_30_BIT0_INDEX */ 3516 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_31_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_31_BIT0_INDEX */ 3517 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_32_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_32_BIT0_INDEX */ 3518 {CLOCK_IP_GROUP_0_INDEX, CLOCK_IP_GATE_20_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P0_GROUP_20_BIT0_INDEX */ 3519 {CLOCK_IP_GROUP_0_INDEX, CLOCK_IP_GATE_5_INDEX, CLOCK_IP_GATE_PCTL_1}, /* CLOCK_IP_P0_GROUP_5_BIT1_INDEX */ 3520 {CLOCK_IP_GROUP_1_INDEX, CLOCK_IP_GATE_1_INDEX, CLOCK_IP_GATE_PCTL_1}, /* CLOCK_IP_P1_GROUP_1_BIT1_INDEX */ 3521 {CLOCK_IP_GROUP_4_INDEX, CLOCK_IP_GATE_2_INDEX, CLOCK_IP_GATE_PCTL_1}, /* CLOCK_IP_P4_GROUP_2_BIT1_INDEX */ 3522 {CLOCK_IP_GROUP_5_INDEX, CLOCK_IP_GATE_0_INDEX, CLOCK_IP_GATE_PCTL_1}, /* CLOCK_IP_P5_GROUP_0_BIT1_INDEX */ 3523 {CLOCK_IP_GROUP_0_INDEX, CLOCK_IP_GATE_5_INDEX, CLOCK_IP_GATE_PCTL_2}, /* CLOCK_IP_P0_GROUP_5_BIT2_INDEX */ 3524 {CLOCK_IP_GROUP_1_INDEX, CLOCK_IP_GATE_1_INDEX, CLOCK_IP_GATE_PCTL_2}, /* CLOCK_IP_P1_GROUP_1_BIT2_INDEX */ 3525 {CLOCK_IP_GROUP_4_INDEX, CLOCK_IP_GATE_2_INDEX, CLOCK_IP_GATE_PCTL_2}, /* CLOCK_IP_P4_GROUP_2_BIT2_INDEX */ 3526 {CLOCK_IP_GROUP_5_INDEX, CLOCK_IP_GATE_0_INDEX, CLOCK_IP_GATE_PCTL_2}, /* CLOCK_IP_P5_GROUP_0_BIT2_INDEX */ 3527 {CLOCK_IP_GROUP_0_INDEX, CLOCK_IP_GATE_5_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P0_GROUP_5_BIT0_INDEX */ 3528 {CLOCK_IP_GROUP_1_INDEX, CLOCK_IP_GATE_1_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P1_GROUP_1_BIT0_INDEX */ 3529 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_0_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_0_BIT0_INDEX */ 3530 {CLOCK_IP_GROUP_4_INDEX, CLOCK_IP_GATE_2_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P4_GROUP_2_BIT0_INDEX */ 3531 {CLOCK_IP_GROUP_5_INDEX, CLOCK_IP_GATE_0_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P5_GROUP_0_BIT0_INDEX */ 3532 {CLOCK_IP_GROUP_1_INDEX, CLOCK_IP_GATE_12_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P1_GROUP_12_BIT0_INDEX */ 3533 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_3_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_3_BIT0_INDEX */ 3534 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_4_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_4_BIT0_INDEX */ 3535 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_5_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_5_BIT0_INDEX */ 3536 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_6_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_6_BIT0_INDEX */ 3537 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_7_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_7_BIT0_INDEX */ 3538 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_8_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_8_BIT0_INDEX */ 3539 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_9_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_9_BIT0_INDEX */ 3540 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_10_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_10_BIT0_INDEX */ 3541 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_11_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_11_BIT0_INDEX */ 3542 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_12_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_12_BIT0_INDEX */ 3543 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_13_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_13_BIT0_INDEX */ 3544 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_14_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_14_BIT0_INDEX */ 3545 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_15_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_15_BIT0_INDEX */ 3546 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_16_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_16_BIT0_INDEX */ 3547 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_17_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_17_BIT0_INDEX */ 3548 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_18_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_18_BIT0_INDEX */ 3549 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_19_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_19_BIT0_INDEX */ 3550 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_20_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_20_BIT0_INDEX */ 3551 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_21_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_21_BIT0_INDEX */ 3552 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_22_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_22_BIT0_INDEX */ 3553 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_23_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_23_BIT0_INDEX */ 3554 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_24_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_24_BIT0_INDEX */ 3555 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_25_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_25_BIT0_INDEX */ 3556 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_26_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_26_BIT0_INDEX */ 3557 {CLOCK_IP_GROUP_0_INDEX, CLOCK_IP_GATE_2_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P0_GROUP_2_BIT0_INDEX */ 3558 {CLOCK_IP_GROUP_0_INDEX, CLOCK_IP_GATE_3_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P0_GROUP_3_BIT0_INDEX */ 3559 {CLOCK_IP_GROUP_0_INDEX, CLOCK_IP_GATE_22_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P0_GROUP_22_BIT0_INDEX */ 3560 {CLOCK_IP_GROUP_0_INDEX, CLOCK_IP_GATE_4_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P0_GROUP_4_BIT0_INDEX */ 3561 {CLOCK_IP_GROUP_1_INDEX, CLOCK_IP_GATE_0_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P1_GROUP_0_BIT0_INDEX */ 3562 {CLOCK_IP_GROUP_4_INDEX, CLOCK_IP_GATE_11_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P4_GROUP_11_BIT0_INDEX */ 3563 {CLOCK_IP_GROUP_0_INDEX, CLOCK_IP_GATE_8_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P0_GROUP_8_BIT0_INDEX */ 3564 {CLOCK_IP_GROUP_0_INDEX, CLOCK_IP_GATE_9_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P0_GROUP_9_BIT0_INDEX */ 3565 {CLOCK_IP_GROUP_0_INDEX, CLOCK_IP_GATE_10_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P0_GROUP_10_BIT0_INDEX */ 3566 {CLOCK_IP_GROUP_1_INDEX, CLOCK_IP_GATE_5_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P1_GROUP_5_BIT0_INDEX */ 3567 {CLOCK_IP_GROUP_1_INDEX, CLOCK_IP_GATE_6_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P1_GROUP_6_BIT0_INDEX */ 3568 {CLOCK_IP_GROUP_1_INDEX, CLOCK_IP_GATE_7_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P1_GROUP_7_BIT0_INDEX */ 3569 {CLOCK_IP_GROUP_4_INDEX, CLOCK_IP_GATE_6_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P4_GROUP_6_BIT0_INDEX */ 3570 {CLOCK_IP_GROUP_4_INDEX, CLOCK_IP_GATE_7_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P4_GROUP_7_BIT0_INDEX */ 3571 {CLOCK_IP_GROUP_4_INDEX, CLOCK_IP_GATE_8_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P4_GROUP_8_BIT0_INDEX */ 3572 {CLOCK_IP_GROUP_5_INDEX, CLOCK_IP_GATE_3_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P5_GROUP_3_BIT0_INDEX */ 3573 {CLOCK_IP_GROUP_5_INDEX, CLOCK_IP_GATE_4_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P5_GROUP_4_BIT0_INDEX */ 3574 {CLOCK_IP_GROUP_5_INDEX, CLOCK_IP_GATE_5_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P5_GROUP_5_BIT0_INDEX */ 3575 {CLOCK_IP_GROUP_0_INDEX, CLOCK_IP_GATE_6_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P0_GROUP_6_BIT0_INDEX */ 3576 {CLOCK_IP_GROUP_0_INDEX, CLOCK_IP_GATE_11_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P0_GROUP_11_BIT0_INDEX */ 3577 {CLOCK_IP_GROUP_0_INDEX, CLOCK_IP_GATE_22_INDEX, CLOCK_IP_GATE_PCTL_1}, /* CLOCK_IP_P0_GROUP_22_BIT1_INDEX */ 3578 {CLOCK_IP_GROUP_0_INDEX, CLOCK_IP_GATE_5_INDEX, CLOCK_IP_GATE_PCTL_3}, /* CLOCK_IP_P0_GROUP_5_BIT3_INDEX */ 3579 {CLOCK_IP_GROUP_1_INDEX, CLOCK_IP_GATE_1_INDEX, CLOCK_IP_GATE_PCTL_3}, /* CLOCK_IP_P1_GROUP_1_BIT3_INDEX */ 3580 {CLOCK_IP_GROUP_4_INDEX, CLOCK_IP_GATE_2_INDEX, CLOCK_IP_GATE_PCTL_3}, /* CLOCK_IP_P4_GROUP_2_BIT3_INDEX */ 3581 {CLOCK_IP_GROUP_5_INDEX, CLOCK_IP_GATE_0_INDEX, CLOCK_IP_GATE_PCTL_3}, /* CLOCK_IP_P5_GROUP_0_BIT3_INDEX */ 3582 {CLOCK_IP_GROUP_0_INDEX, CLOCK_IP_GATE_19_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P0_GROUP_19_BIT0_INDEX */ 3583 {CLOCK_IP_GROUP_4_INDEX, CLOCK_IP_GATE_12_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P4_GROUP_12_BIT0_INDEX */ 3584 {CLOCK_IP_GROUP_0_INDEX, CLOCK_IP_GATE_23_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P0_GROUP_23_BIT0_INDEX */ 3585 {CLOCK_IP_GROUP_4_INDEX, CLOCK_IP_GATE_14_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P4_GROUP_14_BIT0_INDEX */ 3586 {CLOCK_IP_GROUP_4_INDEX, CLOCK_IP_GATE_0_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P4_GROUP_0_BIT0_INDEX */ 3587 {CLOCK_IP_GROUP_4_INDEX, CLOCK_IP_GATE_1_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P4_GROUP_1_BIT0_INDEX */ 3588 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_33_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_33_BIT0_INDEX */ 3589 {CLOCK_IP_GROUP_4_INDEX, CLOCK_IP_GATE_9_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P4_GROUP_9_BIT0_INDEX */ 3590 {CLOCK_IP_GROUP_0_INDEX, CLOCK_IP_GATE_24_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P0_GROUP_24_BIT0_INDEX */ 3591 {CLOCK_IP_GROUP_1_INDEX, CLOCK_IP_GATE_8_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P1_GROUP_8_BIT0_INDEX */ 3592 {CLOCK_IP_GROUP_1_INDEX, CLOCK_IP_GATE_9_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P1_GROUP_9_BIT0_INDEX */ 3593 {CLOCK_IP_GROUP_0_INDEX, CLOCK_IP_GATE_21_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P0_GROUP_21_BIT0_INDEX */ 3594 {CLOCK_IP_GROUP_1_INDEX, CLOCK_IP_GATE_14_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P1_GROUP_14_BIT0_INDEX */ 3595 {CLOCK_IP_GROUP_4_INDEX, CLOCK_IP_GATE_13_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P4_GROUP_13_BIT0_INDEX */ 3596 {CLOCK_IP_GROUP_5_INDEX, CLOCK_IP_GATE_6_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P5_GROUP_6_BIT0_INDEX */ 3597 {CLOCK_IP_GROUP_0_INDEX, CLOCK_IP_GATE_1_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P0_GROUP_1_BIT0_INDEX */ 3598 {CLOCK_IP_GROUP_0_INDEX, CLOCK_IP_GATE_7_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P0_GROUP_7_BIT0_INDEX */ 3599 {CLOCK_IP_GROUP_1_INDEX, CLOCK_IP_GATE_2_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P1_GROUP_2_BIT0_INDEX */ 3600 {CLOCK_IP_GROUP_1_INDEX, CLOCK_IP_GATE_3_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P1_GROUP_3_BIT0_INDEX */ 3601 {CLOCK_IP_GROUP_1_INDEX, CLOCK_IP_GATE_4_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P1_GROUP_4_BIT0_INDEX */ 3602 {CLOCK_IP_GROUP_4_INDEX, CLOCK_IP_GATE_3_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P4_GROUP_3_BIT0_INDEX */ 3603 {CLOCK_IP_GROUP_4_INDEX, CLOCK_IP_GATE_4_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P4_GROUP_4_BIT0_INDEX */ 3604 {CLOCK_IP_GROUP_4_INDEX, CLOCK_IP_GATE_5_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P4_GROUP_5_BIT0_INDEX */ 3605 {CLOCK_IP_GROUP_5_INDEX, CLOCK_IP_GATE_1_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P5_GROUP_1_BIT0_INDEX */ 3606 {CLOCK_IP_GROUP_5_INDEX, CLOCK_IP_GATE_2_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P5_GROUP_2_BIT0_INDEX */ 3607 {CLOCK_IP_GROUP_1_INDEX, CLOCK_IP_GATE_10_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P1_GROUP_10_BIT0_INDEX */ 3608 {CLOCK_IP_GROUP_4_INDEX, CLOCK_IP_GATE_10_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P4_GROUP_10_BIT0_INDEX */ 3609 }; 3610 3611 3612 3613 /* Clock stop constant section data */ 3614 #define MCU_STOP_SEC_CONST_UNSPECIFIED 3615 #include "Mcu_MemMap.h" 3616 3617 /*================================================================================================== 3618 GLOBAL VARIABLES 3619 ==================================================================================================*/ 3620 3621 /*================================================================================================== 3622 * LOCAL FUNCTION PROTOTYPES 3623 ==================================================================================================*/ 3624 3625 /*================================================================================================== 3626 * LOCAL FUNCTIONS 3627 ==================================================================================================*/ 3628 3629 /*================================================================================================== 3630 * GLOBAL FUNCTIONS 3631 ==================================================================================================*/ 3632 3633 3634 3635 3636 #ifdef __cplusplus 3637 } 3638 #endif 3639 3640 /** @} */ 3641 3642
