CLOCK_IP_HAS_SIRC_VLP_CLK (reference) in projects: hal_nxp-3.7.0

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Searched refs:CLOCK_IP_HAS_SIRC_VLP_CLK (Results 1 – 4 of 4) sorted by relevance

/hal_nxp-3.7.0/s32/soc/s32k146/include/
D	Clock_Ip_Cfg_Defines.h	`181 #define CLOCK_IP_HAS_SIRC_VLP_CLK 3U macro`
/hal_nxp-3.7.0/s32/drivers/s32ze/Mcu/include/
D	Clock_Ip_Types.h	`149 #if defined(CLOCK_IP_HAS_SIRC_VLP_CLK) 150 SIRC_VLP_CLK = CLOCK_IP_HAS_SIRC_VLP_CLK,`
/hal_nxp-3.7.0/s32/drivers/s32k3/Mcu/include/
D	Clock_Ip_Types.h	`142 #if defined(CLOCK_IP_HAS_SIRC_VLP_CLK) 143 SIRC_VLP_CLK = CLOCK_IP_HAS_SIRC_VLP_CLK,`
/hal_nxp-3.7.0/s32/drivers/s32k1/Mcu/include/
D	Clock_Ip_Types.h	`232 #if defined(CLOCK_IP_HAS_SIRC_VLP_CLK) 233 SIRC_VLP_CLK = CLOCK_IP_HAS_SIRC_VLP_CLK,`

TraceRecorderSource-2.7.6
TraceRecorderSource-3.4.0
Zephyr-Core-2.7.6
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Zephyr-Core-3.5.0
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babblesim_ext_2G4_channel_multiatt-3.4.0
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babblesim_ext_2G4_device_burst_interferer-3.7.0-3.6.0-3.5.0-3.4.0
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babblesim_ext_2G4_device_playback-3.7.0
babblesim_ext_2G4_libPhyComv1-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_libPhyComv1-3.7.0
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babblesim_ext_2G4_modem_BLE_simple-3.6.0-3.5.0
babblesim_ext_2G4_modem_BLE_simple-3.7.0
babblesim_ext_2G4_modem_magic-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_modem_magic-3.7.0
babblesim_ext_2G4_phy_v1-3.4.0
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edtt-3.7.0
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