CLOCK_IP_HAS_P5_AE_CLK (reference) in projects: hal_nxp-3.7.0

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Searched refs:CLOCK_IP_HAS_P5_AE_CLK (Results 1 – 5 of 5) sorted by relevance

/hal_nxp-3.7.0/s32/soc/s32z270/include/
D	Clock_Ip_Cfg_Defines.h	`413 #define CLOCK_IP_HAS_P5_AE_CLK 230U macro`
/hal_nxp-3.7.0/s32/drivers/s32ze/Mcu/src/
D	Clock_Ip_ProgFreqSwitch.c	`205 #if (defined(CLOCK_IP_HAS_P5_AE_CLK) && defined(CLOCK_IP_HAS_FIRC_AE_CLK)) in Clock_Ip_CgmXPcfsSdurDivcDiveDivs()`
/hal_nxp-3.7.0/s32/drivers/s32ze/Mcu/include/
D	Clock_Ip_Types.h	`2367 #if defined(CLOCK_IP_HAS_P5_AE_CLK) 2368 P5_AE_CLK = CLOCK_IP_HAS_P5_AE_CLK,`
/hal_nxp-3.7.0/s32/drivers/s32k3/Mcu/include/
D	Clock_Ip_Types.h	`2342 #if defined(CLOCK_IP_HAS_P5_AE_CLK) 2343 P5_AE_CLK = CLOCK_IP_HAS_P5_AE_CLK,`
/hal_nxp-3.7.0/s32/drivers/s32k1/Mcu/include/
D	Clock_Ip_Types.h	`2438 #if defined(CLOCK_IP_HAS_P5_AE_CLK) 2439 P5_AE_CLK = CLOCK_IP_HAS_P5_AE_CLK,`

TraceRecorderSource-2.7.6
TraceRecorderSource-3.4.0
Zephyr-Core-2.7.6
Zephyr-Core-3.4.0
Zephyr-Core-3.5.0
Zephyr-Core-3.6.0
Zephyr-Core-3.7.0
acpica-3.5.0
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acpica-3.7.0
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babblesim_ext_2G4_channel_multiatt-3.4.0
babblesim_ext_2G4_channel_multiatt-3.7.0-3.6.0-3.5.0
babblesim_ext_2G4_device_WLAN_actmod-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_burst_interferer-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.7.0
babblesim_ext_2G4_libPhyComv1-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_libPhyComv1-3.7.0
babblesim_ext_2G4_modem_BLE_simple-3.4.0
babblesim_ext_2G4_modem_BLE_simple-3.6.0-3.5.0
babblesim_ext_2G4_modem_BLE_simple-3.7.0
babblesim_ext_2G4_modem_magic-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_modem_magic-3.7.0
babblesim_ext_2G4_phy_v1-3.4.0
babblesim_ext_2G4_phy_v1-3.6.0-3.5.0
babblesim_ext_2G4_phy_v1-3.7.0
babblesim_ext_libCryptov1-3.7.0-3.6.0-3.5.0-3.4.0
bsim-3.4.0
bsim-3.6.0-3.5.0
bsim-3.7.0
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cmsis-nn-3.6.0-3.5.0
cmsis-nn-3.7.0
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edtt-3.6.0-3.5.0-3.4.0
edtt-3.7.0
fatfs-2.7.6
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