Searched refs:CLOCK_IP_GATE (Results 1 – 3 of 3) sorted by relevance
| /hal_nxp-3.7.0/s32/drivers/s32k3/Mcu/src/ |
| D | Clock_Ip_Data.c | 100 #define CLOCK_IP_GATE 1U macro
1080 /* ADC0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, …
1081 /* ADC1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, …
1083 /* ADC2_CLK clock */ {0U, CLOCK_IP_GATE, 0U, …
1086 /* ADC3_CLK clock */ {0U, CLOCK_IP_GATE, 0U, …
1089 /* ADC4_CLK clock */ {0U, CLOCK_IP_GATE, 0U, …
1092 /* ADC5_CLK clock */ {0U, CLOCK_IP_GATE, 0U, …
1095 /* ADC6_CLK clock */ {0U, CLOCK_IP_GATE, 0U, …
1098 /* ADCBIST_CLK clock */ {0U, CLOCK_IP_GATE, 0U, …
1101 /* AES_ACCEL_CLK clock */ {0U, CLOCK_IP_GATE, 0U, …
[all …]
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| /hal_nxp-3.7.0/s32/drivers/s32ze/Mcu/src/ |
| D | Clock_Ip_Data.c | 101 #define CLOCK_IP_GATE 1U macro
780 /* ADC0_CLK clock */ {0U, CLOCK_IP_GATE, …
781 /* ADC1_CLK clock */ {0U, CLOCK_IP_GATE, …
782 /* CE_EDMA_CLK clock */ {0U, CLOCK_IP_GATE, …
783 /* CE_PIT0_CLK clock */ {0U, CLOCK_IP_GATE, …
784 /* CE_PIT1_CLK clock */ {0U, CLOCK_IP_GATE, …
785 /* CE_PIT2_CLK clock */ {0U, CLOCK_IP_GATE, …
786 /* CE_PIT3_CLK clock */ {0U, CLOCK_IP_GATE, …
787 /* CE_PIT4_CLK clock */ {0U, CLOCK_IP_GATE, …
788 /* CE_PIT5_CLK clock */ {0U, CLOCK_IP_GATE, …
[all …]
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| /hal_nxp-3.7.0/s32/drivers/s32k1/Mcu/src/ |
| D | Clock_Ip_Data.c | 116 #define CLOCK_IP_GATE 6U macro
152 #define CLOCK_IP_GATE 7U
186 #define CLOCK_IP_GATE 7U
883 /* CMP0_CLK clock */ {0U, CLOCK_IP_GATE, …
885 /* CMU0_CLK clock */ {0U, CLOCK_IP_GATE, …
888 /* CMU1_CLK clock */ {0U, CLOCK_IP_GATE, …
890 /* CRC0_CLK clock */ {0U, CLOCK_IP_GATE, …
892 /* DMAMUX0_CLK clock */ {0U, CLOCK_IP_GATE, …
899 /* EWM0_CLK clock */ {0U, CLOCK_IP_GATE, …
907 /* FLEXCAN0_CLK clock */ {0U, CLOCK_IP_GATE, …
[all …]
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