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Searched refs:C0 (Results 1 – 25 of 98) sorted by relevance

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/hal_nxp-3.7.0/mcux/mcux-sdk/drivers/acmp/
Dfsl_acmp.c87 … tmp32 = (base->C0 & (~(CMP_C0_PMODE_MASK | CMP_C0_INVT_MASK | CMP_C0_COS_MASK | CMP_C0_OPE_MASK | in ACMP_Init()
117 base->C0 = tmp32; in ACMP_Init()
186 base->C0 = ((base->C0 | CMP_C0_EN_MASK) & ~CMP_C0_CFx_MASK); in ACMP_Enable()
190 base->C0 &= ~(CMP_C0_EN_MASK | CMP_C0_CFx_MASK); in ACMP_Enable()
210 base->C0 = ((base->C0 | CMP_C0_LINKEN_MASK) & ~CMP_C0_CFx_MASK); in ACMP_EnableLinkToDAC()
214 base->C0 &= ~(CMP_C0_LINKEN_MASK | CMP_C0_CFx_MASK); in ACMP_EnableLinkToDAC()
274 base->C0 = ((base->C0 | CMP_C0_DMAEN_MASK) & ~CMP_C0_CFx_MASK); in ACMP_EnableDMA()
278 base->C0 &= ~(CMP_C0_DMAEN_MASK | CMP_C0_CFx_MASK); in ACMP_EnableDMA()
295 base->C0 = ((base->C0 | CMP_C0_WE_MASK) & ~CMP_C0_CFx_MASK); in ACMP_EnableWindowMode()
299 base->C0 &= ~(CMP_C0_WE_MASK | CMP_C0_CFx_MASK); in ACMP_EnableWindowMode()
[all …]
/hal_nxp-3.7.0/mcux/mcux-sdk/drivers/dac/
Dfsl_dac.c81 tmp8 = base->C0 & (uint8_t)(~(DAC_C0_DACRFS_MASK | DAC_C0_LPEN_MASK)); in DAC_Init()
90 base->C0 = tmp8; in DAC_Init()
149 tmp8 = base->C0 & (uint8_t)(~DAC_C0_DACTRGSEL_MASK); in DAC_SetBufferConfig()
154 base->C0 = tmp8; in DAC_SetBufferConfig()
251 base->C0 |= ((uint8_t)mask); /* Write 1 to enable. */ in DAC_EnableBufferInterrupts()
267 base->C0 &= (uint8_t)(~((uint8_t)mask)); /* Write 0 to disable. */ in DAC_DisableBufferInterrupts()
Dfsl_dac.h191 base->C0 |= (uint8_t)DAC_C0_DACEN_MASK; in DAC_Enable()
195 base->C0 &= (uint8_t)(~DAC_C0_DACEN_MASK); in DAC_Enable()
285 base->C0 |= DAC_C0_DACSWTRG_MASK; in DAC_DoSoftwareTriggerBuffer()
/hal_nxp-3.7.0/mcux/mcux-sdk/drivers/acmp_1/
Dfsl_acmp.c165 base->C0 = tmp8; in ACMP_SetChannelConfig()
/hal_nxp-3.7.0/s32/drivers/s32k1/BaseNXP/header/
DS32K146_CMP.h73 __IO uint32_t C0; /**< CMP Control Register 0, offset: 0x0 */ member
DS32K118_CMP.h73 __IO uint32_t C0; /**< CMP Control Register 0, offset: 0x0 */ member
DS32K142W_CMP.h73 __IO uint32_t C0; /**< CMP Control Register 0, offset: 0x0 */ member
DS32K144W_CMP.h73 __IO uint32_t C0; /**< CMP Control Register 0, offset: 0x0 */ member
DS32K142_CMP.h73 __IO uint32_t C0; /**< CMP Control Register 0, offset: 0x0 */ member
DS32K144_CMP.h73 __IO uint32_t C0; /**< CMP Control Register 0, offset: 0x0 */ member
DS32K148_CMP.h73 __IO uint32_t C0; /**< CMP Control Register 0, offset: 0x0 */ member
DS32K116_CMP.h73 __IO uint32_t C0; /**< CMP Control Register 0, offset: 0x0 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKE04Z4/
DMKE04Z4.h184 __IO uint8_t C0; /**< ACMP Control Register 0, offset: 0x1 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKE02Z4/
DMKE02Z4.h194 __IO uint8_t C0; /**< ACMP Control Register 0, offset: 0x1 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKE04Z1284/
DMKE04Z1284.h189 __IO uint8_t C0; /**< ACMP Control Register 0, offset: 0x1 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKE06Z4/
DMKE06Z4.h189 __IO uint8_t C0; /**< ACMP Control Register 0, offset: 0x1 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKL25Z4/
DMKL25Z4.h741 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKV10Z7/
DMKV10Z7.h1267 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKE14Z4/
DMKE14Z4.h752 __IO uint32_t C0; /**< CMP Control Register 0, offset: 0x0 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKV30F12810/
DMKV30F12810.h1352 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MK02F12810/
DMK02F12810.h1348 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKV31F12810/
DMKV31F12810.h1365 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKV10Z1287/
DMKV10Z1287.h1258 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKE15Z4/
DMKE15Z4.h753 __IO uint32_t C0; /**< CMP Control Register 0, offset: 0x0 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKW40Z4/
DMKW40Z4.h1122 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */ member
1143 #define DAC_C0_REG(base) ((base)->C0)

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