| /hal_nxp-3.7.0/s32/drivers/s32k3/Fls/src/ |
| D | Qspi_Ip_Controller.c | 1960 BaseAddr->BUF0IND = (uint32)0x00000000UL; in Qspi_Ip_ResetAllRegisters()
2027 BaseAddr->BUF0IND = (uint32)0x00000000UL; in Qspi_Ip_ResetAllRegisters()
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| /hal_nxp-3.7.0/s32/drivers/s32k1/BaseNXP/header/ |
| D | S32K148_QUADSPI.h | 88 __IO uint32_t BUF0IND; /**< Buffer0 Top Index Register, offset: 0x30 */ member
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| /hal_nxp-3.7.0/s32/drivers/s32k3/BaseNXP/header/ |
| D | S32K344_QUADSPI.h | 88 __IO uint32_t BUF0IND; /**< Buffer 0 Top Index Register, offset: 0x30 */ member
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| /hal_nxp-3.7.0/s32/drivers/s32k3/Fls/include/ |
| D | Qspi_Ip_HwAccess.h | 612 BaseAddr->BUF0IND = Index; in Qspi_Ip_SetAhbBuf0Ind()
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| /hal_nxp-3.7.0/s32/drivers/s32ze/BaseNXP/header/ |
| D | S32Z2_QUADSPI.h | 90 __IO uint32_t BUF0IND; /**< Buffer 0 Top Index Register, offset: 0x30 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MK80F25615/ |
| D | MK80F25615.h | 18266 __IO uint32_t BUF0IND; /**< Buffer0 Top Index Register, offset: 0x30 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MK82F25615/ |
| D | MK82F25615.h | 19239 __IO uint32_t BUF0IND; /**< Buffer0 Top Index Register, offset: 0x30 */ member
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| /hal_nxp-3.7.0/imx/devices/MCIMX6X/ |
| D | MCIMX6X_M4.h | 30424 …__IO uint32_t BUF0IND; /**< Buffer0 Top Index Register, offset: 0x… member
30474 #define QuadSPI_BUF0IND_REG(base) ((base)->BUF0IND)
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MK27FA15/ |
| D | MK27FA15.h | 17768 __IO uint32_t BUF0IND; /**< Buffer0 Top Index Register, offset: 0x30 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MK28FA15/ |
| D | MK28FA15.h | 17770 __IO uint32_t BUF0IND; /**< Buffer0 Top Index Register, offset: 0x30 */ member
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| /hal_nxp-3.7.0/imx/devices/MCIMX7D/ |
| D | MCIMX7D_M4.h | 37622 …__IO uint32_t BUF0IND; /**< Buffer0 Top Index Register, offset: 0x… member
37672 #define QuadSPI_BUF0IND_REG(base) ((base)->BUF0IND)
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MCIMX7U3/ |
| D | MCIMX7U3_cm4.h | 25109 __IO uint32_t BUF0IND; /**< Buffer0 Top Index Register, offset: 0x30 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MCIMX7U5/ |
| D | MCIMX7U5_cm4.h | 25110 __IO uint32_t BUF0IND; /**< Buffer0 Top Index Register, offset: 0x30 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8MQ5/ |
| D | MIMX8MQ5_cm4.h | 43998 __IO uint32_t BUF0IND; /**< Buffer0 Top Index Register, offset: 0x30 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8MQ7/ |
| D | MIMX8MQ7_cm4.h | 46171 __IO uint32_t BUF0IND; /**< Buffer0 Top Index Register, offset: 0x30 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8MD7/ |
| D | MIMX8MD7_cm4.h | 46171 __IO uint32_t BUF0IND; /**< Buffer0 Top Index Register, offset: 0x30 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8MD6/ |
| D | MIMX8MD6_cm4.h | 46171 __IO uint32_t BUF0IND; /**< Buffer0 Top Index Register, offset: 0x30 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8MQ6/ |
| D | MIMX8MQ6_cm4.h | 46171 __IO uint32_t BUF0IND; /**< Buffer0 Top Index Register, offset: 0x30 */ member
|
