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Searched refs:BCH_STATUS0_CLR_RSVD0_MASK (Results 1 – 7 of 7) sorted by relevance

/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8MQ5/
DMIMX8MQ5_cm4.h6790 #define BCH_STATUS0_CLR_RSVD0_MASK (0x3U) macro
6794 … (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_RSVD0_SHIFT)) & BCH_STATUS0_CLR_RSVD0_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8MQ7/
DMIMX8MQ7_cm4.h6790 #define BCH_STATUS0_CLR_RSVD0_MASK (0x3U) macro
6794 … (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_RSVD0_SHIFT)) & BCH_STATUS0_CLR_RSVD0_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8MD7/
DMIMX8MD7_cm4.h6790 #define BCH_STATUS0_CLR_RSVD0_MASK (0x3U) macro
6794 … (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_RSVD0_SHIFT)) & BCH_STATUS0_CLR_RSVD0_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8MD6/
DMIMX8MD6_cm4.h6790 #define BCH_STATUS0_CLR_RSVD0_MASK (0x3U) macro
6794 … (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_RSVD0_SHIFT)) & BCH_STATUS0_CLR_RSVD0_MASK)
/hal_nxp-3.7.0/imx/devices/MCIMX6X/
DMCIMX6X_M4.h2232 #define BCH_STATUS0_CLR_RSVD0_MASK 0x3u macro
2234 … (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_CLR_RSVD0_SHIFT))&BCH_STATUS0_CLR_RSVD0_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8MQ6/
DMIMX8MQ6_cm4.h6790 #define BCH_STATUS0_CLR_RSVD0_MASK (0x3U) macro
6794 … (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_RSVD0_SHIFT)) & BCH_STATUS0_CLR_RSVD0_MASK)
/hal_nxp-3.7.0/imx/devices/MCIMX7D/
DMCIMX7D_M4.h2287 #define BCH_STATUS0_CLR_RSVD0_MASK 0x3u macro
2289 … (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_CLR_RSVD0_SHIFT))&BCH_STATUS0_CLR_RSVD0_MASK)