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Searched refs:AUX0PLLCLKDIV (Results 1 – 16 of 16) sorted by relevance

/hal_nxp-3.7.0/mcux/mcux-sdk/devices/RW610/drivers/
Dfsl_clock.c526 …return CLOCK_GetTcpuMciClkFreq() / ((CLKCTL0->AUX0PLLCLKDIV & CLKCTL0_AUX0PLLCLKDIV_DIV_MASK) + 1U… in CLOCK_GetAux0PllClkFreq()
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/RW612/drivers/
Dfsl_clock.c526 …return CLOCK_GetTcpuMciClkFreq() / ((CLKCTL0->AUX0PLLCLKDIV & CLKCTL0_AUX0PLLCLKDIV_DIV_MASK) + 1U… in CLOCK_GetAux0PllClkFreq()
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT685S/drivers/
Dfsl_clock.c228 …return CLOCK_GetSysPfdFreq(kCLOCK_Pfd2) / ((CLKCTL0->AUX0PLLCLKDIV & CLKCTL0_AUX0PLLCLKDIV_DIV_MAS… in CLOCK_GetAux0PllClkFreq()
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT633S/drivers/
Dfsl_clock.c228 …return CLOCK_GetSysPfdFreq(kCLOCK_Pfd2) / ((CLKCTL0->AUX0PLLCLKDIV & CLKCTL0_AUX0PLLCLKDIV_DIV_MAS… in CLOCK_GetAux0PllClkFreq()
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT595S/drivers/
Dfsl_clock.c209 …return CLOCK_GetSysPfdFreq(kCLOCK_Pfd2) / ((CLKCTL0->AUX0PLLCLKDIV & CLKCTL0_AUX0PLLCLKDIV_DIV_MAS… in CLOCK_GetAux0PllClkFreq()
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT533S/drivers/
Dfsl_clock.c209 …return CLOCK_GetSysPfdFreq(kCLOCK_Pfd2) / ((CLKCTL0->AUX0PLLCLKDIV & CLKCTL0_AUX0PLLCLKDIV_DIV_MAS… in CLOCK_GetAux0PllClkFreq()
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT555S/drivers/
Dfsl_clock.c209 …return CLOCK_GetSysPfdFreq(kCLOCK_Pfd2) / ((CLKCTL0->AUX0PLLCLKDIV & CLKCTL0_AUX0PLLCLKDIV_DIV_MAS… in CLOCK_GetAux0PllClkFreq()
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h1261 __IO uint32_t AUX0PLLCLKDIV; /**< aux0 pll clk divider, offset: 0x248 */ member
DMIMXRT685S_cm33.h6972 __IO uint32_t AUX0PLLCLKDIV; /**< aux0 pll clk divider, offset: 0x248 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h6972 __IO uint32_t AUX0PLLCLKDIV; /**< aux0 pll clk divider, offset: 0x248 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h1947 __IO uint32_t AUX0PLLCLKDIV; /**< AUX0 PLL Clock Divider, offset: 0x248 */ member
DMIMXRT595S_cm33.h8185 __IO uint32_t AUX0PLLCLKDIV; /**< AUX0 PLL Clock Divider, offset: 0x248 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h8181 __IO uint32_t AUX0PLLCLKDIV; /**< AUX0 PLL Clock Divider, offset: 0x248 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h8184 __IO uint32_t AUX0PLLCLKDIV; /**< AUX0 PLL Clock Divider, offset: 0x248 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/RW610/
DRW610.h19745 __IO uint32_t AUX0PLLCLKDIV; /**< AUX0 PLL clock divider, offset: 0x248 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/RW612/
DRW612.h19745 __IO uint32_t AUX0PLLCLKDIV; /**< AUX0 PLL clock divider, offset: 0x248 */ member