1 /* 2 * Copyright (c) 2013-2020 ARM Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Licensed under the Apache License, Version 2.0 (the License); you may 7 * not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 * 18 * $Date: 31. March 2020 19 * $Revision: V1.2 20 * 21 * Project: SAI (Serial Audio Interface) Driver definitions 22 */ 23 24 /* History: 25 * Version 1.2 26 * Removed volatile from ARM_SAI_STATUS 27 * Version 1.1 28 * ARM_SAI_STATUS made volatile 29 * Version 1.0 30 * Initial release 31 */ 32 33 #ifndef DRIVER_SAI_H_ 34 #define DRIVER_SAI_H_ 35 36 #ifdef __cplusplus 37 extern "C" 38 { 39 #endif 40 41 #include "Driver_Common.h" 42 43 #define ARM_SAI_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,2) /* API version */ 44 45 46 #define _ARM_Driver_SAI_(n) Driver_SAI##n 47 #define ARM_Driver_SAI_(n) _ARM_Driver_SAI_(n) 48 49 50 /****** SAI Control Codes *****/ 51 52 #define ARM_SAI_CONTROL_Msk (0xFFUL) 53 #define ARM_SAI_CONFIGURE_TX (0x01UL) ///< Configure Transmitter; arg1 and arg2 provide additional configuration 54 #define ARM_SAI_CONFIGURE_RX (0x02UL) ///< Configure Receiver; arg1 and arg2 provide additional configuration 55 #define ARM_SAI_CONTROL_TX (0x03UL) ///< Control Transmitter; arg1.0: 0=disable (default), 1=enable; arg1.1: mute 56 #define ARM_SAI_CONTROL_RX (0x04UL) ///< Control Receiver; arg1.0: 0=disable (default), 1=enable 57 #define ARM_SAI_MASK_SLOTS_TX (0x05UL) ///< Mask Transmitter slots; arg1 = mask (bit: 0=active, 1=inactive); all configured slots are active by default 58 #define ARM_SAI_MASK_SLOTS_RX (0x06UL) ///< Mask Receiver slots; arg1 = mask (bit: 0=active, 1=inactive); all configured slots are active by default 59 #define ARM_SAI_ABORT_SEND (0x07UL) ///< Abort \ref ARM_SAI_Send 60 #define ARM_SAI_ABORT_RECEIVE (0x08UL) ///< Abort \ref ARM_SAI_Receive 61 62 /*----- SAI Control Codes: Configuration Parameters: Mode -----*/ 63 #define ARM_SAI_MODE_Pos 8 64 #define ARM_SAI_MODE_Msk (1UL << ARM_SAI_MODE_Pos) 65 #define ARM_SAI_MODE_MASTER (1UL << ARM_SAI_MODE_Pos) ///< Master Mode 66 #define ARM_SAI_MODE_SLAVE (0UL << ARM_SAI_MODE_Pos) ///< Slave Mode (default) 67 68 /*----- SAI Control Codes: Configuration Parameters: Synchronization -----*/ 69 #define ARM_SAI_SYNCHRONIZATION_Pos 9 70 #define ARM_SAI_SYNCHRONIZATION_Msk (1UL << ARM_SAI_SYNCHRONIZATION_Pos) 71 #define ARM_SAI_ASYNCHRONOUS (0UL << ARM_SAI_SYNCHRONIZATION_Pos) ///< Asynchronous (default) 72 #define ARM_SAI_SYNCHRONOUS (1UL << ARM_SAI_SYNCHRONIZATION_Pos) ///< Synchronous 73 74 /*----- SAI Control Codes: Configuration Parameters: Protocol -----*/ 75 #define ARM_SAI_PROTOCOL_Pos 10 76 #define ARM_SAI_PROTOCOL_Msk (7UL << ARM_SAI_PROTOCOL_Pos) 77 #define ARM_SAI_PROTOCOL_USER (0UL << ARM_SAI_PROTOCOL_Pos) ///< User defined (default) 78 #define ARM_SAI_PROTOCOL_I2S (1UL << ARM_SAI_PROTOCOL_Pos) ///< I2S 79 #define ARM_SAI_PROTOCOL_MSB_JUSTIFIED (2UL << ARM_SAI_PROTOCOL_Pos) ///< MSB (left) justified 80 #define ARM_SAI_PROTOCOL_LSB_JUSTIFIED (3UL << ARM_SAI_PROTOCOL_Pos) ///< LSB (right) justified 81 #define ARM_SAI_PROTOCOL_PCM_SHORT (4UL << ARM_SAI_PROTOCOL_Pos) ///< PCM with short frame 82 #define ARM_SAI_PROTOCOL_PCM_LONG (5UL << ARM_SAI_PROTOCOL_Pos) ///< PCM with long frame 83 #define ARM_SAI_PROTOCOL_AC97 (6UL << ARM_SAI_PROTOCOL_Pos) ///< AC'97 84 85 /*----- SAI Control Codes: Configuration Parameters: Data Size -----*/ 86 #define ARM_SAI_DATA_SIZE_Pos 13 87 #define ARM_SAI_DATA_SIZE_Msk (0x1FUL << ARM_SAI_DATA_SIZE_Pos) 88 #define ARM_SAI_DATA_SIZE(n) ((((n)-1UL)&0x1FUL) << ARM_SAI_DATA_SIZE_Pos) ///< Data size in bits (8..32) 89 90 /*----- SAI Control Codes: Configuration Parameters: Bit Order -----*/ 91 #define ARM_SAI_BIT_ORDER_Pos 18 92 #define ARM_SAI_BIT_ORDER_Msk (1UL << ARM_SAI_BIT_ORDER_Pos) 93 #define ARM_SAI_MSB_FIRST (0UL << ARM_SAI_BIT_ORDER_Pos) ///< Data is transferred with MSB first (default) 94 #define ARM_SAI_LSB_FIRST (1UL << ARM_SAI_BIT_ORDER_Pos) ///< Data is transferred with LSB first; User Protocol only (ignored otherwise) 95 96 /*----- SAI Control Codes: Configuration Parameters: Mono Mode -----*/ 97 #define ARM_SAI_MONO_MODE (1UL << 19) ///< Mono Mode (only for I2S, MSB/LSB justified) 98 99 /*----- SAI Control Codes:Configuration Parameters: Companding -----*/ 100 #define ARM_SAI_COMPANDING_Pos 20 101 #define ARM_SAI_COMPANDING_Msk (3UL << ARM_SAI_COMPANDING_Pos) 102 #define ARM_SAI_COMPANDING_NONE (0UL << ARM_SAI_COMPANDING_Pos) ///< No companding (default) 103 #define ARM_SAI_COMPANDING_A_LAW (2UL << ARM_SAI_COMPANDING_Pos) ///< A-Law companding 104 #define ARM_SAI_COMPANDING_U_LAW (3UL << ARM_SAI_COMPANDING_Pos) ///< u-Law companding 105 106 /*----- SAI Control Codes: Configuration Parameters: Clock Polarity -----*/ 107 #define ARM_SAI_CLOCK_POLARITY_Pos 23 108 #define ARM_SAI_CLOCK_POLARITY_Msk (1UL << ARM_SAI_CLOCK_POLARITY_Pos) 109 #define ARM_SAI_CLOCK_POLARITY_0 (0UL << ARM_SAI_CLOCK_POLARITY_Pos) ///< Drive on falling edge, Capture on rising edge (default) 110 #define ARM_SAI_CLOCK_POLARITY_1 (1UL << ARM_SAI_CLOCK_POLARITY_Pos) ///< Drive on rising edge, Capture on falling edge 111 112 /*----- SAI Control Codes: Configuration Parameters: Master Clock Pin -----*/ 113 #define ARM_SAI_MCLK_PIN_Pos 24 114 #define ARM_SAI_MCLK_PIN_Msk (3UL << ARM_SAI_MCLK_PIN_Pos) 115 #define ARM_SAI_MCLK_PIN_INACTIVE (0UL << ARM_SAI_MCLK_PIN_Pos) ///< MCLK not used (default) 116 #define ARM_SAI_MCLK_PIN_OUTPUT (1UL << ARM_SAI_MCLK_PIN_Pos) ///< MCLK is output (Master only) 117 #define ARM_SAI_MCLK_PIN_INPUT (2UL << ARM_SAI_MCLK_PIN_Pos) ///< MCLK is input (Master only) 118 119 120 /****** SAI Configuration (arg1) *****/ 121 122 /*----- SAI Configuration (arg1): Frame Length -----*/ 123 #define ARM_SAI_FRAME_LENGTH_Pos 0 124 #define ARM_SAI_FRAME_LENGTH_Msk (0x3FFUL << ARM_SAI_FRAME_LENGTH_Pos) 125 #define ARM_SAI_FRAME_LENGTH(n) ((((n)-1UL)&0x3FFUL) << ARM_SAI_FRAME_LENGTH_Pos) ///< Frame length in bits (8..1024); default depends on protocol and data 126 127 /*----- SAI Configuration (arg1): Frame Sync Width -----*/ 128 #define ARM_SAI_FRAME_SYNC_WIDTH_Pos 10 129 #define ARM_SAI_FRAME_SYNC_WIDTH_Msk (0xFFUL << ARM_SAI_FRAME_SYNC_WIDTH_Pos) 130 #define ARM_SAI_FRAME_SYNC_WIDTH(n) ((((n)-1UL)&0xFFUL) << ARM_SAI_FRAME_SYNC_WIDTH_Pos) ///< Frame Sync width in bits (1..256); default=1; User Protocol only (ignored otherwise) 131 132 /*----- SAI Configuration (arg1): Frame Sync Polarity -----*/ 133 #define ARM_SAI_FRAME_SYNC_POLARITY_Pos 18 134 #define ARM_SAI_FRAME_SYNC_POLARITY_Msk (1UL << ARM_SAI_FRAME_SYNC_POLARITY_Pos) 135 #define ARM_SAI_FRAME_SYNC_POLARITY_HIGH (0UL << ARM_SAI_FRAME_SYNC_POLARITY_Pos) ///< Frame Sync is active high (default); User Protocol only (ignored otherwise) 136 #define ARM_SAI_FRAME_SYNC_POLARITY_LOW (1UL << ARM_SAI_FRAME_SYNC_POLARITY_Pos) ///< Frame Sync is active low; User Protocol only (ignored otherwise) 137 138 /*----- SAI Configuration (arg1): Frame Sync Early -----*/ 139 #define ARM_SAI_FRAME_SYNC_EARLY (1UL << 19) ///< Frame Sync one bit before the first bit of the frame; User Protocol only (ignored otherwise) 140 141 /*----- SAI Configuration (arg1): Slot Count -----*/ 142 #define ARM_SAI_SLOT_COUNT_Pos 20 143 #define ARM_SAI_SLOT_COUNT_Msk (0x1FUL << ARM_SAI_SLOT_COUNT_Pos) 144 #define ARM_SAI_SLOT_COUNT(n) ((((n)-1UL)&0x1FUL) << ARM_SAI_SLOT_COUNT_Pos) ///< Number of slots in frame (1..32); default=1; User Protocol only (ignored otherwise) 145 146 /*----- SAI Configuration (arg1): Slot Size -----*/ 147 #define ARM_SAI_SLOT_SIZE_Pos 25 148 #define ARM_SAI_SLOT_SIZE_Msk (3UL << ARM_SAI_SLOT_SIZE_Pos) 149 #define ARM_SAI_SLOT_SIZE_DEFAULT (0UL << ARM_SAI_SLOT_SIZE_Pos) ///< Slot size is equal to data size (default) 150 #define ARM_SAI_SLOT_SIZE_16 (1UL << ARM_SAI_SLOT_SIZE_Pos) ///< Slot size = 16 bits; User Protocol only (ignored otherwise) 151 #define ARM_SAI_SLOT_SIZE_32 (3UL << ARM_SAI_SLOT_SIZE_Pos) ///< Slot size = 32 bits; User Protocol only (ignored otherwise) 152 153 /*----- SAI Configuration (arg1): Slot Offset -----*/ 154 #define ARM_SAI_SLOT_OFFSET_Pos 27 155 #define ARM_SAI_SLOT_OFFSET_Msk (0x1FUL << ARM_SAI_SLOT_OFFSET_Pos) 156 #define ARM_SAI_SLOT_OFFSET(n) (((n)&0x1FUL) << ARM_SAI_SLOT_OFFSET_Pos) ///< Offset of first data bit in slot (0..31); default=0; User Protocol only (ignored otherwise) 157 158 /****** SAI Configuration (arg2) *****/ 159 160 /*----- SAI Control Codes: Configuration Parameters: Audio Frequency (Master only) -----*/ 161 #define ARM_SAI_AUDIO_FREQ_Msk (0x0FFFFFUL) ///< Audio frequency mask 162 163 /*----- SAI Control Codes: Configuration Parameters: Master Clock Prescaler (Master only and MCLK Pin) -----*/ 164 #define ARM_SAI_MCLK_PRESCALER_Pos 20 165 #define ARM_SAI_MCLK_PRESCALER_Msk (0xFFFUL << ARM_SAI_MCLK_PRESCALER_Pos) 166 #define ARM_SAI_MCLK_PRESCALER(n) ((((n)-1UL)&0xFFFUL) << ARM_SAI_MCLK_PRESCALER_Pos) ///< MCLK prescaler; Audio_frequency = MCLK/n; n = 1..4096 (default=1) 167 168 169 /****** SAI specific error codes *****/ 170 #define ARM_SAI_ERROR_SYNCHRONIZATION (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< Specified Synchronization not supported 171 #define ARM_SAI_ERROR_PROTOCOL (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Specified Protocol not supported 172 #define ARM_SAI_ERROR_DATA_SIZE (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Specified Data size not supported 173 #define ARM_SAI_ERROR_BIT_ORDER (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< Specified Bit order not supported 174 #define ARM_SAI_ERROR_MONO_MODE (ARM_DRIVER_ERROR_SPECIFIC - 5) ///< Specified Mono mode not supported 175 #define ARM_SAI_ERROR_COMPANDING (ARM_DRIVER_ERROR_SPECIFIC - 6) ///< Specified Companding not supported 176 #define ARM_SAI_ERROR_CLOCK_POLARITY (ARM_DRIVER_ERROR_SPECIFIC - 7) ///< Specified Clock polarity not supported 177 #define ARM_SAI_ERROR_AUDIO_FREQ (ARM_DRIVER_ERROR_SPECIFIC - 8) ///< Specified Audio frequency not supported 178 #define ARM_SAI_ERROR_MCLK_PIN (ARM_DRIVER_ERROR_SPECIFIC - 9) ///< Specified MCLK Pin setting not supported 179 #define ARM_SAI_ERROR_MCLK_PRESCALER (ARM_DRIVER_ERROR_SPECIFIC - 10) ///< Specified MCLK Prescaler not supported 180 #define ARM_SAI_ERROR_FRAME_LENGTH (ARM_DRIVER_ERROR_SPECIFIC - 11) ///< Specified Frame length not supported 181 #define ARM_SAI_ERROR_FRAME_LENGHT (ARM_DRIVER_ERROR_SPECIFIC - 11) ///< Specified Frame length not supported @deprecated use \ref ARM_SAI_ERROR_FRAME_LENGTH instead 182 #define ARM_SAI_ERROR_FRAME_SYNC_WIDTH (ARM_DRIVER_ERROR_SPECIFIC - 12) ///< Specified Frame Sync width not supported 183 #define ARM_SAI_ERROR_FRAME_SYNC_POLARITY (ARM_DRIVER_ERROR_SPECIFIC - 13) ///< Specified Frame Sync polarity not supported 184 #define ARM_SAI_ERROR_FRAME_SYNC_EARLY (ARM_DRIVER_ERROR_SPECIFIC - 14) ///< Specified Frame Sync early not supported 185 #define ARM_SAI_ERROR_SLOT_COUNT (ARM_DRIVER_ERROR_SPECIFIC - 15) ///< Specified Slot count not supported 186 #define ARM_SAI_ERROR_SLOT_SIZE (ARM_DRIVER_ERROR_SPECIFIC - 16) ///< Specified Slot size not supported 187 #define ARM_SAI_ERROR_SLOT_OFFESET (ARM_DRIVER_ERROR_SPECIFIC - 17) ///< Specified Slot offset not supported 188 189 190 /** 191 \brief SAI Status 192 */ 193 typedef struct _ARM_SAI_STATUS { 194 uint32_t tx_busy : 1; ///< Transmitter busy flag 195 uint32_t rx_busy : 1; ///< Receiver busy flag 196 uint32_t tx_underflow : 1; ///< Transmit data underflow detected (cleared on start of next send operation) 197 uint32_t rx_overflow : 1; ///< Receive data overflow detected (cleared on start of next receive operation) 198 uint32_t frame_error : 1; ///< Sync Frame error detected (cleared on start of next send/receive operation) 199 uint32_t reserved : 27; 200 } ARM_SAI_STATUS; 201 202 203 /****** SAI Event *****/ 204 #define ARM_SAI_EVENT_SEND_COMPLETE (1UL << 0) ///< Send completed 205 #define ARM_SAI_EVENT_RECEIVE_COMPLETE (1UL << 1) ///< Receive completed 206 #define ARM_SAI_EVENT_TX_UNDERFLOW (1UL << 2) ///< Transmit data not available 207 #define ARM_SAI_EVENT_RX_OVERFLOW (1UL << 3) ///< Receive data overflow 208 #define ARM_SAI_EVENT_FRAME_ERROR (1UL << 4) ///< Sync Frame error in Slave mode (optional) 209 210 211 // Function documentation 212 /** 213 \fn ARM_DRIVER_VERSION ARM_SAI_GetVersion (void) 214 \brief Get driver version. 215 \return \ref ARM_DRIVER_VERSION 216 217 \fn ARM_SAI_CAPABILITIES ARM_SAI_GetCapabilities (void) 218 \brief Get driver capabilities. 219 \return \ref ARM_SAI_CAPABILITIES 220 221 \fn int32_t ARM_SAI_Initialize (ARM_SAI_SignalEvent_t cb_event) 222 \brief Initialize SAI Interface. 223 \param[in] cb_event Pointer to \ref ARM_SAI_SignalEvent 224 \return \ref execution_status 225 226 \fn int32_t ARM_SAI_Uninitialize (void) 227 \brief De-initialize SAI Interface. 228 \return \ref execution_status 229 230 \fn int32_t ARM_SAI_PowerControl (ARM_POWER_STATE state) 231 \brief Control SAI Interface Power. 232 \param[in] state Power state 233 \return \ref execution_status 234 235 \fn int32_t ARM_SAI_Send (const void *data, uint32_t num) 236 \brief Start sending data to SAI transmitter. 237 \param[in] data Pointer to buffer with data to send to SAI transmitter 238 \param[in] num Number of data items to send 239 \return \ref execution_status 240 241 \fn int32_t ARM_SAI_Receive (void *data, uint32_t num) 242 \brief Start receiving data from SAI receiver. 243 \param[out] data Pointer to buffer for data to receive from SAI receiver 244 \param[in] num Number of data items to receive 245 \return \ref execution_status 246 247 \fn uint32_t ARM_SAI_GetTxCount (void) 248 \brief Get transmitted data count. 249 \return number of data items transmitted 250 251 \fn uint32_t ARM_SAI_GetRxCount (void) 252 \brief Get received data count. 253 \return number of data items received 254 255 \fn int32_t ARM_SAI_Control (uint32_t control, uint32_t arg1, uint32_t arg2) 256 \brief Control SAI Interface. 257 \param[in] control Operation 258 \param[in] arg1 Argument 1 of operation (optional) 259 \param[in] arg2 Argument 2 of operation (optional) 260 \return common \ref execution_status and driver specific \ref sai_execution_status 261 262 \fn ARM_SAI_STATUS ARM_SAI_GetStatus (void) 263 \brief Get SAI status. 264 \return SAI status \ref ARM_SAI_STATUS 265 266 \fn void ARM_SAI_SignalEvent (uint32_t event) 267 \brief Signal SAI Events. 268 \param[in] event \ref SAI_events notification mask 269 \return none 270 */ 271 272 typedef void (*ARM_SAI_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_SAI_SignalEvent : Signal SAI Event. 273 274 275 /** 276 \brief SAI Driver Capabilities. 277 */ 278 typedef struct _ARM_SAI_CAPABILITIES { 279 uint32_t asynchronous : 1; ///< supports asynchronous Transmit/Receive 280 uint32_t synchronous : 1; ///< supports synchronous Transmit/Receive 281 uint32_t protocol_user : 1; ///< supports user defined Protocol 282 uint32_t protocol_i2s : 1; ///< supports I2S Protocol 283 uint32_t protocol_justified : 1; ///< supports MSB/LSB justified Protocol 284 uint32_t protocol_pcm : 1; ///< supports PCM short/long frame Protocol 285 uint32_t protocol_ac97 : 1; ///< supports AC'97 Protocol 286 uint32_t mono_mode : 1; ///< supports Mono mode 287 uint32_t companding : 1; ///< supports Companding 288 uint32_t mclk_pin : 1; ///< supports MCLK (Master Clock) pin 289 uint32_t event_frame_error : 1; ///< supports Frame error event: \ref ARM_SAI_EVENT_FRAME_ERROR 290 uint32_t reserved : 21; ///< Reserved (must be zero) 291 } ARM_SAI_CAPABILITIES; 292 293 294 /** 295 \brief Access structure of the SAI Driver. 296 */ 297 typedef struct _ARM_DRIVER_SAI { 298 ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_SAI_GetVersion : Get driver version. 299 ARM_SAI_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_SAI_GetCapabilities : Get driver capabilities. 300 int32_t (*Initialize) (ARM_SAI_SignalEvent_t cb_event); ///< Pointer to \ref ARM_SAI_Initialize : Initialize SAI Interface. 301 int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_SAI_Uninitialize : De-initialize SAI Interface. 302 int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_SAI_PowerControl : Control SAI Interface Power. 303 int32_t (*Send) (const void *data, uint32_t num); ///< Pointer to \ref ARM_SAI_Send : Start sending data to SAI Interface. 304 int32_t (*Receive) ( void *data, uint32_t num); ///< Pointer to \ref ARM_SAI_Receive : Start receiving data from SAI Interface. 305 uint32_t (*GetTxCount) (void); ///< Pointer to \ref ARM_SAI_GetTxCount : Get transmitted data count. 306 uint32_t (*GetRxCount) (void); ///< Pointer to \ref ARM_SAI_GetRxCount : Get received data count. 307 int32_t (*Control) (uint32_t control, uint32_t arg1, uint32_t arg2); ///< Pointer to \ref ARM_SAI_Control : Control SAI Interface. 308 ARM_SAI_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_SAI_GetStatus : Get SAI status. 309 } const ARM_DRIVER_SAI; 310 311 #ifdef __cplusplus 312 } 313 #endif 314 315 #endif /* DRIVER_SAI_H_ */ 316
