Home
last modified time | relevance | path

Searched refs:ADC_CLP0_CLP0_MASK (Results 1 – 25 of 69) sorted by relevance

123

/hal_nxp-3.7.0/s32/drivers/s32k1/BaseNXP/header/
DS32K118_ADC.h380 #define ADC_CLP0_CLP0_MASK (0xFFU) macro
383 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
DS32K144W_ADC.h384 #define ADC_CLP0_CLP0_MASK (0xFFU) macro
387 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
DS32K142_ADC.h384 #define ADC_CLP0_CLP0_MASK (0xFFU) macro
387 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
DS32K144_ADC.h384 #define ADC_CLP0_CLP0_MASK (0xFFU) macro
387 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
DS32K142W_ADC.h384 #define ADC_CLP0_CLP0_MASK (0xFFU) macro
387 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
DS32K116_ADC.h380 #define ADC_CLP0_CLP0_MASK (0xFFU) macro
383 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
DS32K146_ADC.h870 #define ADC_CLP0_CLP0_MASK (0xFFU) macro
873 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
DS32K148_ADC.h869 #define ADC_CLP0_CLP0_MASK (0xFFU) macro
872 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/drivers/adc12/
Dfsl_adc12.c100 uint32_t CLP0 = ((base->CLP0 & ADC_CLP0_CLP0_MASK) >> ADC_CLP0_CLP0_SHIFT); in ADC12_GetCalibrationStatus()
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKL25Z4/
DMKL25Z4.h530 #define ADC_CLP0_CLP0_MASK (0x3FU) macro
532 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKL17Z644/
DMKL17Z644.h674 #define ADC_CLP0_CLP0_MASK (0x3FU) macro
676 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKL27Z644/
DMKL27Z644.h683 #define ADC_CLP0_CLP0_MASK (0x3FU) macro
685 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKV10Z7/
DMKV10Z7.h656 #define ADC_CLP0_CLP0_MASK (0x3FU) macro
658 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKE14Z4/
DMKE14Z4.h630 #define ADC_CLP0_CLP0_MASK (0xFFU) macro
634 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKV30F12810/
DMKV30F12810.h742 #define ADC_CLP0_CLP0_MASK (0x3FU) macro
744 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MK02F12810/
DMK02F12810.h742 #define ADC_CLP0_CLP0_MASK (0x3FU) macro
744 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKV31F12810/
DMKV31F12810.h755 #define ADC_CLP0_CLP0_MASK (0x3FU) macro
757 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKV10Z1287/
DMKV10Z1287.h647 #define ADC_CLP0_CLP0_MASK (0x3FU) macro
649 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKE15Z4/
DMKE15Z4.h631 #define ADC_CLP0_CLP0_MASK (0xFFU) macro
635 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKE12Z7/
DMKE12Z7.h777 #define ADC_CLP0_CLP0_MASK (0xFFU) macro
781 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKM14ZA5/
DMKM14ZA5.h948 #define ADC_CLP0_CLP0_MASK (0x3FU) macro
952 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKE16Z4/
DMKE16Z4.h629 #define ADC_CLP0_CLP0_MASK (0xFFU) macro
633 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKV11Z7/
DMKV11Z7.h647 #define ADC_CLP0_CLP0_MASK (0x3FU) macro
649 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKE12Z9/
DMKE12Z9.h795 #define ADC_CLP0_CLP0_MASK (0xFFU) macro
798 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKE13Z7/
DMKE13Z7.h778 #define ADC_CLP0_CLP0_MASK (0xFFU) macro
782 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)

123