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Searched refs:ADC_CH_A_CFG1_REG (Results 1 – 2 of 2) sorted by relevance

/hal_nxp-3.7.0/imx/drivers/
Dadc_imx7d.c83 ADC_CH_A_CFG1_REG(base) = 0x0; in ADC_Deinit()
215 ADC_CH_A_CFG1_REG(base) = 0x0; in ADC_LogicChDeinit()
251 ADC_CH_A_CFG1_REG(base) = (ADC_CH_A_CFG1_REG(base) & ~ADC_CH_A_CFG1_CHA_SEL_MASK) | \ in ADC_SelectInputCh()
295 ADC_CH_A_CFG1_REG(base) = (ADC_CH_A_CFG1_REG(base) & ~ADC_CH_A_CFG1_CHA_TIMER_MASK) | \ in ADC_SetConvertRate()
331 ADC_CH_A_CFG1_REG(base) |= ADC_CH_A_CFG1_CHA_AVG_EN_MASK; in ADC_SetAverageCmd()
354 ADC_CH_A_CFG1_REG(base) &= ~ADC_CH_A_CFG1_CHA_AVG_EN_MASK; in ADC_SetAverageCmd()
430ADC_CH_A_CFG1_REG(base) = (ADC_CH_A_CFG1_REG(base) & ~ADC_CH_A_CFG1_CHA_SINGLE_MASK) | in ADC_SetConvertCmd()
454 ADC_CH_A_CFG1_REG(base) &= ~ADC_CH_A_CFG1_CHA_EN_MASK; in ADC_SetConvertCmd()
484 ADC_CH_A_CFG1_REG(base) |= ADC_CH_A_CFG1_CHA_SINGLE_MASK | ADC_CH_A_CFG1_CHA_EN_MASK; in ADC_TriggerSingleConvert()
516 ADC_CH_A_CFG1_REG(base) &= ~ADC_CH_A_CFG1_CHA_EN_MASK; in ADC_StopConvert()
/hal_nxp-3.7.0/imx/devices/MCIMX7D/
DMCIMX7D_M4.h362 #define ADC_CH_A_CFG1_REG(base) ((base)->CH_A_CFG1) macro
731 #define ADC1_CH_A_CFG1 ADC_CH_A_CFG1_REG(ADC1_BASE_PTR)
752 #define ADC2_CH_A_CFG1 ADC_CH_A_CFG1_REG(ADC2_BASE_PTR)