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Searched refs:A7CORE0_CTRL (Results 1 – 1 of 1) sorted by relevance

/hal_nxp-3.7.0/imx/devices/MCIMX7D/
DMCIMX7D_M4.h19135 …__IO uint32_t A7CORE0_CTRL; /**< GPC PGC Control Register, offset: 0x80… member
19184 #define GPC_PGC_A7CORE0_CTRL_REG(base) ((base)->A7CORE0_CTRL)