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Searched refs:u32RegVal (Results 1 – 24 of 24) sorted by relevance

/hal_nxp-3.6.0/s32/drivers/s32ze/Port/src/
DSiul2_Port_Ip.c822 uint32 u32RegVal = 0UL; in Siul2_Port_Ip_GetMSCRConfiguration() local
827 u32RegVal = base->MSCR[pin]; in Siul2_Port_Ip_GetMSCRConfiguration()
831 u32TempVal = (u32RegVal & SIUL2_AE_MSCR_SSS_MASK) >> SIUL2_AE_MSCR_SSS_SHIFT; in Siul2_Port_Ip_GetMSCRConfiguration()
836 u32TempVal = (u32RegVal & SIUL2_MSCR_SSS_MASK) >> SIUL2_MSCR_SSS_SHIFT; in Siul2_Port_Ip_GetMSCRConfiguration()
839 u32TempVal = (u32RegVal & SIUL2_MSCR_SMC_MASK) >> SIUL2_MSCR_SMC_SHIFT; in Siul2_Port_Ip_GetMSCRConfiguration()
845 if (0U == ((u32RegVal & SIUL2_AE_MSCR_PUE_MASK) >> SIUL2_AE_MSCR_PUE_SHIFT)) in Siul2_Port_Ip_GetMSCRConfiguration()
851 u32TempVal = (u32RegVal & SIUL2_AE_MSCR_PUS_MASK) >> SIUL2_AE_MSCR_PUS_SHIFT; in Siul2_Port_Ip_GetMSCRConfiguration()
856 u32TempVal = (u32RegVal & SIUL2_AE_MSCR_SRE_MASK) >> SIUL2_AE_MSCR_SRE_SHIFT; in Siul2_Port_Ip_GetMSCRConfiguration()
862 if (0U == ((u32RegVal & SIUL2_MSCR_PUE_MASK) >> SIUL2_MSCR_PUE_SHIFT)) in Siul2_Port_Ip_GetMSCRConfiguration()
868 u32TempVal = (u32RegVal & SIUL2_MSCR_PUS_MASK) >> SIUL2_MSCR_PUS_SHIFT; in Siul2_Port_Ip_GetMSCRConfiguration()
[all …]
/hal_nxp-3.6.0/s32/drivers/s32k3/Port/src/
DSiul2_Port_Ip.c503 uint32 u32RegVal = 0UL; in Siul2_Port_Ip_GetMSCRConfiguration() local
508 u32RegVal = base->MSCR[pin]; in Siul2_Port_Ip_GetMSCRConfiguration()
509 u32TempVal = (u32RegVal & SIUL2_MSCR_SSS_MASK) >> SIUL2_MSCR_SSS_SHIFT; in Siul2_Port_Ip_GetMSCRConfiguration()
511 u32TempVal = (u32RegVal & SIUL2_MSCR_SMC_MASK) >> SIUL2_MSCR_SMC_SHIFT; in Siul2_Port_Ip_GetMSCRConfiguration()
514 if (0U == ((u32RegVal & SIUL2_MSCR_PUE_MASK) >> SIUL2_MSCR_PUE_SHIFT)) in Siul2_Port_Ip_GetMSCRConfiguration()
520 u32TempVal = (u32RegVal & SIUL2_MSCR_PUS_MASK) >> SIUL2_MSCR_PUS_SHIFT; in Siul2_Port_Ip_GetMSCRConfiguration()
525 u32TempVal = (u32RegVal & SIUL2_MSCR_SRE_MASK) >> SIUL2_MSCR_SRE_SHIFT; in Siul2_Port_Ip_GetMSCRConfiguration()
529 u32TempVal = (u32RegVal & SIUL2_MSCR_RCVR_MASK) >> SIUL2_MSCR_RCVR_SHIFT; in Siul2_Port_Ip_GetMSCRConfiguration()
535 u32TempVal = (u32RegVal & SIUL2_MSCR_ODE_MASK) >> SIUL2_MSCR_ODE_SHIFT; in Siul2_Port_Ip_GetMSCRConfiguration()
541 u32TempVal = (u32RegVal & SIUL2_MSCR_DSE_MASK) >> SIUL2_MSCR_DSE_SHIFT; in Siul2_Port_Ip_GetMSCRConfiguration()
[all …]
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC5528/drivers/
Dfsl_power.c1495 uint32_t u32RegVal; in POWER_Xtal16mhzCapabankTrim() local
1536 u32RegVal = ANACTRL->XO32M_CTRL; in POWER_Xtal16mhzCapabankTrim()
1537 u32RegVal &= ~(ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK | ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK); in POWER_Xtal16mhzCapabankTrim()
1540 u32RegVal &= ~(ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK); in POWER_Xtal16mhzCapabankTrim()
1542 u32RegVal |= ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK; in POWER_Xtal16mhzCapabankTrim()
1545 …u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapInCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_S… in POWER_Xtal16mhzCapabankTrim()
1546 …u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapOutCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT… in POWER_Xtal16mhzCapabankTrim()
1548 ANACTRL->XO32M_CTRL = u32RegVal; in POWER_Xtal16mhzCapabankTrim()
1560 uint32_t u32RegVal; in POWER_Xtal32khzCapabankTrim() local
1597 u32RegVal = PMC->XTAL32K; in POWER_Xtal32khzCapabankTrim()
[all …]
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC5526/drivers/
Dfsl_power.c1495 uint32_t u32RegVal; in POWER_Xtal16mhzCapabankTrim() local
1536 u32RegVal = ANACTRL->XO32M_CTRL; in POWER_Xtal16mhzCapabankTrim()
1537 u32RegVal &= ~(ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK | ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK); in POWER_Xtal16mhzCapabankTrim()
1540 u32RegVal &= ~(ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK); in POWER_Xtal16mhzCapabankTrim()
1542 u32RegVal |= ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK; in POWER_Xtal16mhzCapabankTrim()
1545 …u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapInCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_S… in POWER_Xtal16mhzCapabankTrim()
1546 …u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapOutCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT… in POWER_Xtal16mhzCapabankTrim()
1548 ANACTRL->XO32M_CTRL = u32RegVal; in POWER_Xtal16mhzCapabankTrim()
1560 uint32_t u32RegVal; in POWER_Xtal32khzCapabankTrim() local
1597 u32RegVal = PMC->XTAL32K; in POWER_Xtal32khzCapabankTrim()
[all …]
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC55S28/drivers/
Dfsl_power.c1495 uint32_t u32RegVal; in POWER_Xtal16mhzCapabankTrim() local
1536 u32RegVal = ANACTRL->XO32M_CTRL; in POWER_Xtal16mhzCapabankTrim()
1537 u32RegVal &= ~(ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK | ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK); in POWER_Xtal16mhzCapabankTrim()
1540 u32RegVal &= ~(ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK); in POWER_Xtal16mhzCapabankTrim()
1542 u32RegVal |= ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK; in POWER_Xtal16mhzCapabankTrim()
1545 …u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapInCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_S… in POWER_Xtal16mhzCapabankTrim()
1546 …u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapOutCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT… in POWER_Xtal16mhzCapabankTrim()
1548 ANACTRL->XO32M_CTRL = u32RegVal; in POWER_Xtal16mhzCapabankTrim()
1560 uint32_t u32RegVal; in POWER_Xtal32khzCapabankTrim() local
1597 u32RegVal = PMC->XTAL32K; in POWER_Xtal32khzCapabankTrim()
[all …]
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC55S26/drivers/
Dfsl_power.c1495 uint32_t u32RegVal; in POWER_Xtal16mhzCapabankTrim() local
1536 u32RegVal = ANACTRL->XO32M_CTRL; in POWER_Xtal16mhzCapabankTrim()
1537 u32RegVal &= ~(ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK | ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK); in POWER_Xtal16mhzCapabankTrim()
1540 u32RegVal &= ~(ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK); in POWER_Xtal16mhzCapabankTrim()
1542 u32RegVal |= ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK; in POWER_Xtal16mhzCapabankTrim()
1545 …u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapInCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_S… in POWER_Xtal16mhzCapabankTrim()
1546 …u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapOutCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT… in POWER_Xtal16mhzCapabankTrim()
1548 ANACTRL->XO32M_CTRL = u32RegVal; in POWER_Xtal16mhzCapabankTrim()
1560 uint32_t u32RegVal; in POWER_Xtal32khzCapabankTrim() local
1597 u32RegVal = PMC->XTAL32K; in POWER_Xtal32khzCapabankTrim()
[all …]
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC55S66/drivers/
Dfsl_power.c1495 uint32_t u32RegVal; in POWER_Xtal16mhzCapabankTrim() local
1536 u32RegVal = ANACTRL->XO32M_CTRL; in POWER_Xtal16mhzCapabankTrim()
1537 u32RegVal &= ~(ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK | ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK); in POWER_Xtal16mhzCapabankTrim()
1540 u32RegVal &= ~(ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK); in POWER_Xtal16mhzCapabankTrim()
1542 u32RegVal |= ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK; in POWER_Xtal16mhzCapabankTrim()
1545 …u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapInCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_S… in POWER_Xtal16mhzCapabankTrim()
1546 …u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapOutCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT… in POWER_Xtal16mhzCapabankTrim()
1548 ANACTRL->XO32M_CTRL = u32RegVal; in POWER_Xtal16mhzCapabankTrim()
1560 uint32_t u32RegVal; in POWER_Xtal32khzCapabankTrim() local
1597 u32RegVal = PMC->XTAL32K; in POWER_Xtal32khzCapabankTrim()
[all …]
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC55S69/drivers/
Dfsl_power.c1495 uint32_t u32RegVal; in POWER_Xtal16mhzCapabankTrim() local
1536 u32RegVal = ANACTRL->XO32M_CTRL; in POWER_Xtal16mhzCapabankTrim()
1537 u32RegVal &= ~(ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK | ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK); in POWER_Xtal16mhzCapabankTrim()
1540 u32RegVal &= ~(ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK); in POWER_Xtal16mhzCapabankTrim()
1542 u32RegVal |= ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK; in POWER_Xtal16mhzCapabankTrim()
1545 …u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapInCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_S… in POWER_Xtal16mhzCapabankTrim()
1546 …u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapOutCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT… in POWER_Xtal16mhzCapabankTrim()
1548 ANACTRL->XO32M_CTRL = u32RegVal; in POWER_Xtal16mhzCapabankTrim()
1560 uint32_t u32RegVal; in POWER_Xtal32khzCapabankTrim() local
1597 u32RegVal = PMC->XTAL32K; in POWER_Xtal32khzCapabankTrim()
[all …]
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC55S16/drivers/
Dfsl_power.c1586 uint32_t u32RegVal; in POWER_Xtal16mhzCapabankTrim() local
1627 u32RegVal = ANACTRL->XO32M_CTRL; in POWER_Xtal16mhzCapabankTrim()
1628 u32RegVal &= ~(ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK | ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK); in POWER_Xtal16mhzCapabankTrim()
1631 u32RegVal &= ~(ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK); in POWER_Xtal16mhzCapabankTrim()
1633 u32RegVal |= ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK; in POWER_Xtal16mhzCapabankTrim()
1636 …u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapInCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_S… in POWER_Xtal16mhzCapabankTrim()
1637 …u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapOutCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT… in POWER_Xtal16mhzCapabankTrim()
1639 ANACTRL->XO32M_CTRL = u32RegVal; in POWER_Xtal16mhzCapabankTrim()
1651 uint32_t u32RegVal; in POWER_Xtal32khzCapabankTrim() local
1688 u32RegVal = PMC->XTAL32K; in POWER_Xtal32khzCapabankTrim()
[all …]
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC5504CPXXXX/drivers/
Dfsl_power.c1518 uint32_t u32RegVal; in POWER_Xtal16mhzCapabankTrim() local
1559 u32RegVal = ANACTRL->XO32M_CTRL; in POWER_Xtal16mhzCapabankTrim()
1560 u32RegVal &= ~(ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK | ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK); in POWER_Xtal16mhzCapabankTrim()
1563 u32RegVal &= ~(ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK); in POWER_Xtal16mhzCapabankTrim()
1565 u32RegVal |= ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK; in POWER_Xtal16mhzCapabankTrim()
1568 …u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapInCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_S… in POWER_Xtal16mhzCapabankTrim()
1569 …u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapOutCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT… in POWER_Xtal16mhzCapabankTrim()
1571 ANACTRL->XO32M_CTRL = u32RegVal; in POWER_Xtal16mhzCapabankTrim()
1583 uint32_t u32RegVal; in POWER_Xtal32khzCapabankTrim() local
1620 u32RegVal = PMC->XTAL32K; in POWER_Xtal32khzCapabankTrim()
[all …]
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC5506/drivers/
Dfsl_power.c1518 uint32_t u32RegVal; in POWER_Xtal16mhzCapabankTrim() local
1559 u32RegVal = ANACTRL->XO32M_CTRL; in POWER_Xtal16mhzCapabankTrim()
1560 u32RegVal &= ~(ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK | ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK); in POWER_Xtal16mhzCapabankTrim()
1563 u32RegVal &= ~(ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK); in POWER_Xtal16mhzCapabankTrim()
1565 u32RegVal |= ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK; in POWER_Xtal16mhzCapabankTrim()
1568 …u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapInCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_S… in POWER_Xtal16mhzCapabankTrim()
1569 …u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapOutCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT… in POWER_Xtal16mhzCapabankTrim()
1571 ANACTRL->XO32M_CTRL = u32RegVal; in POWER_Xtal16mhzCapabankTrim()
1583 uint32_t u32RegVal; in POWER_Xtal32khzCapabankTrim() local
1620 u32RegVal = PMC->XTAL32K; in POWER_Xtal32khzCapabankTrim()
[all …]
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC5516/drivers/
Dfsl_power.c1586 uint32_t u32RegVal; in POWER_Xtal16mhzCapabankTrim() local
1627 u32RegVal = ANACTRL->XO32M_CTRL; in POWER_Xtal16mhzCapabankTrim()
1628 u32RegVal &= ~(ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK | ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK); in POWER_Xtal16mhzCapabankTrim()
1631 u32RegVal &= ~(ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK); in POWER_Xtal16mhzCapabankTrim()
1633 u32RegVal |= ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK; in POWER_Xtal16mhzCapabankTrim()
1636 …u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapInCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_S… in POWER_Xtal16mhzCapabankTrim()
1637 …u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapOutCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT… in POWER_Xtal16mhzCapabankTrim()
1639 ANACTRL->XO32M_CTRL = u32RegVal; in POWER_Xtal16mhzCapabankTrim()
1651 uint32_t u32RegVal; in POWER_Xtal32khzCapabankTrim() local
1688 u32RegVal = PMC->XTAL32K; in POWER_Xtal32khzCapabankTrim()
[all …]
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC5514/drivers/
Dfsl_power.c1586 uint32_t u32RegVal; in POWER_Xtal16mhzCapabankTrim() local
1627 u32RegVal = ANACTRL->XO32M_CTRL; in POWER_Xtal16mhzCapabankTrim()
1628 u32RegVal &= ~(ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK | ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK); in POWER_Xtal16mhzCapabankTrim()
1631 u32RegVal &= ~(ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK); in POWER_Xtal16mhzCapabankTrim()
1633 u32RegVal |= ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK; in POWER_Xtal16mhzCapabankTrim()
1636 …u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapInCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_S… in POWER_Xtal16mhzCapabankTrim()
1637 …u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapOutCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT… in POWER_Xtal16mhzCapabankTrim()
1639 ANACTRL->XO32M_CTRL = u32RegVal; in POWER_Xtal16mhzCapabankTrim()
1651 uint32_t u32RegVal; in POWER_Xtal32khzCapabankTrim() local
1688 u32RegVal = PMC->XTAL32K; in POWER_Xtal32khzCapabankTrim()
[all …]
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC5502CPXXXX/drivers/
Dfsl_power.c1518 uint32_t u32RegVal; in POWER_Xtal16mhzCapabankTrim() local
1559 u32RegVal = ANACTRL->XO32M_CTRL; in POWER_Xtal16mhzCapabankTrim()
1560 u32RegVal &= ~(ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK | ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK); in POWER_Xtal16mhzCapabankTrim()
1563 u32RegVal &= ~(ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK); in POWER_Xtal16mhzCapabankTrim()
1565 u32RegVal |= ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK; in POWER_Xtal16mhzCapabankTrim()
1568 …u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapInCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_S… in POWER_Xtal16mhzCapabankTrim()
1569 …u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapOutCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT… in POWER_Xtal16mhzCapabankTrim()
1571 ANACTRL->XO32M_CTRL = u32RegVal; in POWER_Xtal16mhzCapabankTrim()
1583 uint32_t u32RegVal; in POWER_Xtal32khzCapabankTrim() local
1620 u32RegVal = PMC->XTAL32K; in POWER_Xtal32khzCapabankTrim()
[all …]
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC5504/drivers/
Dfsl_power.c1518 uint32_t u32RegVal; in POWER_Xtal16mhzCapabankTrim() local
1559 u32RegVal = ANACTRL->XO32M_CTRL; in POWER_Xtal16mhzCapabankTrim()
1560 u32RegVal &= ~(ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK | ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK); in POWER_Xtal16mhzCapabankTrim()
1563 u32RegVal &= ~(ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK); in POWER_Xtal16mhzCapabankTrim()
1565 u32RegVal |= ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK; in POWER_Xtal16mhzCapabankTrim()
1568 …u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapInCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_S… in POWER_Xtal16mhzCapabankTrim()
1569 …u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapOutCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT… in POWER_Xtal16mhzCapabankTrim()
1571 ANACTRL->XO32M_CTRL = u32RegVal; in POWER_Xtal16mhzCapabankTrim()
1583 uint32_t u32RegVal; in POWER_Xtal32khzCapabankTrim() local
1620 u32RegVal = PMC->XTAL32K; in POWER_Xtal32khzCapabankTrim()
[all …]
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC5512/drivers/
Dfsl_power.c1586 uint32_t u32RegVal; in POWER_Xtal16mhzCapabankTrim() local
1627 u32RegVal = ANACTRL->XO32M_CTRL; in POWER_Xtal16mhzCapabankTrim()
1628 u32RegVal &= ~(ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK | ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK); in POWER_Xtal16mhzCapabankTrim()
1631 u32RegVal &= ~(ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK); in POWER_Xtal16mhzCapabankTrim()
1633 u32RegVal |= ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK; in POWER_Xtal16mhzCapabankTrim()
1636 …u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapInCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_S… in POWER_Xtal16mhzCapabankTrim()
1637 …u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapOutCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT… in POWER_Xtal16mhzCapabankTrim()
1639 ANACTRL->XO32M_CTRL = u32RegVal; in POWER_Xtal16mhzCapabankTrim()
1651 uint32_t u32RegVal; in POWER_Xtal32khzCapabankTrim() local
1688 u32RegVal = PMC->XTAL32K; in POWER_Xtal32khzCapabankTrim()
[all …]
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC5506CPXXXX/drivers/
Dfsl_power.c1518 uint32_t u32RegVal; in POWER_Xtal16mhzCapabankTrim() local
1559 u32RegVal = ANACTRL->XO32M_CTRL; in POWER_Xtal16mhzCapabankTrim()
1560 u32RegVal &= ~(ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK | ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK); in POWER_Xtal16mhzCapabankTrim()
1563 u32RegVal &= ~(ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK); in POWER_Xtal16mhzCapabankTrim()
1565 u32RegVal |= ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK; in POWER_Xtal16mhzCapabankTrim()
1568 …u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapInCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_S… in POWER_Xtal16mhzCapabankTrim()
1569 …u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapOutCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT… in POWER_Xtal16mhzCapabankTrim()
1571 ANACTRL->XO32M_CTRL = u32RegVal; in POWER_Xtal16mhzCapabankTrim()
1583 uint32_t u32RegVal; in POWER_Xtal32khzCapabankTrim() local
1620 u32RegVal = PMC->XTAL32K; in POWER_Xtal32khzCapabankTrim()
[all …]
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC55S14/drivers/
Dfsl_power.c1586 uint32_t u32RegVal; in POWER_Xtal16mhzCapabankTrim() local
1627 u32RegVal = ANACTRL->XO32M_CTRL; in POWER_Xtal16mhzCapabankTrim()
1628 u32RegVal &= ~(ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK | ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK); in POWER_Xtal16mhzCapabankTrim()
1631 u32RegVal &= ~(ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK); in POWER_Xtal16mhzCapabankTrim()
1633 u32RegVal |= ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK; in POWER_Xtal16mhzCapabankTrim()
1636 …u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapInCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_S… in POWER_Xtal16mhzCapabankTrim()
1637 …u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapOutCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT… in POWER_Xtal16mhzCapabankTrim()
1639 ANACTRL->XO32M_CTRL = u32RegVal; in POWER_Xtal16mhzCapabankTrim()
1651 uint32_t u32RegVal; in POWER_Xtal32khzCapabankTrim() local
1688 u32RegVal = PMC->XTAL32K; in POWER_Xtal32khzCapabankTrim()
[all …]
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC5502/drivers/
Dfsl_power.c1518 uint32_t u32RegVal; in POWER_Xtal16mhzCapabankTrim() local
1559 u32RegVal = ANACTRL->XO32M_CTRL; in POWER_Xtal16mhzCapabankTrim()
1560 u32RegVal &= ~(ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK | ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK); in POWER_Xtal16mhzCapabankTrim()
1563 u32RegVal &= ~(ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK); in POWER_Xtal16mhzCapabankTrim()
1565 u32RegVal |= ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK; in POWER_Xtal16mhzCapabankTrim()
1568 …u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapInCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_S… in POWER_Xtal16mhzCapabankTrim()
1569 …u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapOutCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT… in POWER_Xtal16mhzCapabankTrim()
1571 ANACTRL->XO32M_CTRL = u32RegVal; in POWER_Xtal16mhzCapabankTrim()
1583 uint32_t u32RegVal; in POWER_Xtal32khzCapabankTrim() local
1620 u32RegVal = PMC->XTAL32K; in POWER_Xtal32khzCapabankTrim()
[all …]
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC55S06/drivers/
Dfsl_power.c1536 uint32_t u32RegVal; in POWER_Xtal16mhzCapabankTrim() local
1577 u32RegVal = ANACTRL->XO32M_CTRL; in POWER_Xtal16mhzCapabankTrim()
1578 u32RegVal &= ~(ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK | ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK); in POWER_Xtal16mhzCapabankTrim()
1581 u32RegVal &= ~(ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK); in POWER_Xtal16mhzCapabankTrim()
1583 u32RegVal |= ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK; in POWER_Xtal16mhzCapabankTrim()
1586 …u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapInCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_S… in POWER_Xtal16mhzCapabankTrim()
1587 …u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapOutCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT… in POWER_Xtal16mhzCapabankTrim()
1589 ANACTRL->XO32M_CTRL = u32RegVal; in POWER_Xtal16mhzCapabankTrim()
1601 uint32_t u32RegVal; in POWER_Xtal32khzCapabankTrim() local
1638 u32RegVal = PMC->XTAL32K; in POWER_Xtal32khzCapabankTrim()
[all …]
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC55S04/drivers/
Dfsl_power.c1536 uint32_t u32RegVal; in POWER_Xtal16mhzCapabankTrim() local
1577 u32RegVal = ANACTRL->XO32M_CTRL; in POWER_Xtal16mhzCapabankTrim()
1578 u32RegVal &= ~(ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK | ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK); in POWER_Xtal16mhzCapabankTrim()
1581 u32RegVal &= ~(ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK); in POWER_Xtal16mhzCapabankTrim()
1583 u32RegVal |= ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK; in POWER_Xtal16mhzCapabankTrim()
1586 …u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapInCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_S… in POWER_Xtal16mhzCapabankTrim()
1587 …u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapOutCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT… in POWER_Xtal16mhzCapabankTrim()
1589 ANACTRL->XO32M_CTRL = u32RegVal; in POWER_Xtal16mhzCapabankTrim()
1601 uint32_t u32RegVal; in POWER_Xtal32khzCapabankTrim() local
1638 u32RegVal = PMC->XTAL32K; in POWER_Xtal32khzCapabankTrim()
[all …]
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC5534/drivers/
Dfsl_clock.c2245 uint32_t u32RegVal; in CLOCK_XtalHfCapabankTrim() local
2283 u32RegVal = ANACTRL->XO32M_CTRL; in CLOCK_XtalHfCapabankTrim()
2284 u32RegVal &= ~(ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK | ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK); in CLOCK_XtalHfCapabankTrim()
2287 u32RegVal &= ~(ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK); in CLOCK_XtalHfCapabankTrim()
2289 u32RegVal |= ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK; in CLOCK_XtalHfCapabankTrim()
2292 u32RegVal |= CLOCK_u8OscCapConvert(u8XOCapInCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT; in CLOCK_XtalHfCapabankTrim()
2293 u32RegVal |= CLOCK_u8OscCapConvert(u8XOCapOutCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT; in CLOCK_XtalHfCapabankTrim()
2295 ANACTRL->XO32M_CTRL = u32RegVal; in CLOCK_XtalHfCapabankTrim()
2321 uint32_t u32RegVal; in CLOCK_Xtal32khzCapabankTrim() local
2355 u32RegVal = PMC->XTAL32K; in CLOCK_Xtal32khzCapabankTrim()
[all …]
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC55S36/drivers/
Dfsl_clock.c2245 uint32_t u32RegVal; in CLOCK_XtalHfCapabankTrim() local
2283 u32RegVal = ANACTRL->XO32M_CTRL; in CLOCK_XtalHfCapabankTrim()
2284 u32RegVal &= ~(ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK | ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK); in CLOCK_XtalHfCapabankTrim()
2287 u32RegVal &= ~(ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK); in CLOCK_XtalHfCapabankTrim()
2289 u32RegVal |= ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK; in CLOCK_XtalHfCapabankTrim()
2292 u32RegVal |= CLOCK_u8OscCapConvert(u8XOCapInCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT; in CLOCK_XtalHfCapabankTrim()
2293 u32RegVal |= CLOCK_u8OscCapConvert(u8XOCapOutCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT; in CLOCK_XtalHfCapabankTrim()
2295 ANACTRL->XO32M_CTRL = u32RegVal; in CLOCK_XtalHfCapabankTrim()
2321 uint32_t u32RegVal; in CLOCK_Xtal32khzCapabankTrim() local
2355 u32RegVal = PMC->XTAL32K; in CLOCK_Xtal32khzCapabankTrim()
[all …]
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC5536/drivers/
Dfsl_clock.c2245 uint32_t u32RegVal; in CLOCK_XtalHfCapabankTrim() local
2283 u32RegVal = ANACTRL->XO32M_CTRL; in CLOCK_XtalHfCapabankTrim()
2284 u32RegVal &= ~(ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK | ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK); in CLOCK_XtalHfCapabankTrim()
2287 u32RegVal &= ~(ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK); in CLOCK_XtalHfCapabankTrim()
2289 u32RegVal |= ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK; in CLOCK_XtalHfCapabankTrim()
2292 u32RegVal |= CLOCK_u8OscCapConvert(u8XOCapInCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT; in CLOCK_XtalHfCapabankTrim()
2293 u32RegVal |= CLOCK_u8OscCapConvert(u8XOCapOutCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT; in CLOCK_XtalHfCapabankTrim()
2295 ANACTRL->XO32M_CTRL = u32RegVal; in CLOCK_XtalHfCapabankTrim()
2321 uint32_t u32RegVal; in CLOCK_Xtal32khzCapabankTrim() local
2355 u32RegVal = PMC->XTAL32K; in CLOCK_Xtal32khzCapabankTrim()
[all …]