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/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1166/drivers/
Dfsl_gpc.c91 gpc_cm_tran_step_t step, in GPC_CM_ConfigCpuModeTransitionStep() argument
94 if (!((step >= kGPC_CM_SleepSP) && (step <= kGPC_CM_WakeupSP))) in GPC_CM_ConfigCpuModeTransitionStep()
96 uint32_t tmp32 = *(uint32_t *)((uint32_t)base + s_cmRegOffset[step]); in GPC_CM_ConfigCpuModeTransitionStep()
113 *(uint32_t *)((uint32_t)base + s_cmRegOffset[step]) = tmp32; in GPC_CM_ConfigCpuModeTransitionStep()
284 gpc_sp_tran_step_t step, in GPC_SP_ConfigSetPointTransitionStep() argument
287 uint32_t tmp32 = *(uint32_t *)((uint32_t)base + s_spRegOffset[step]); in GPC_SP_ConfigSetPointTransitionStep()
304 *(uint32_t *)((uint32_t)base + s_spRegOffset[step]) = tmp32; in GPC_SP_ConfigSetPointTransitionStep()
315 gpc_stby_tran_step_t step, in GPC_STBY_ConfigStandbyTransitionStep() argument
318 uint32_t tmp32 = *(uint32_t *)((uint32_t)base + s_stbyRegOffset[step]); in GPC_STBY_ConfigStandbyTransitionStep()
334 *(uint32_t *)((uint32_t)base + s_stbyRegOffset[step]) = tmp32; in GPC_STBY_ConfigStandbyTransitionStep()
Dfsl_gpc.h438 gpc_cm_tran_step_t step,
590 gpc_sp_tran_step_t step,
645 gpc_stby_tran_step_t step,
Dfsl_clock.c192 ss->step = (uint16_t)((mod << 1UL) * (uint32_t)(ss->stop) / XTAL_FREQ); in CLOCK_CalcPllSpreadSpectrum()
205 ANADIG_PLL_SYS_PLL2_SS_STEP(config->ss->step)) == ANADIG_PLL->SYS_PLL2_SS)) in CLOCK_InitSysPll2()
241 ANADIG_PLL_SYS_PLL2_SS_STEP(config->ss->step)); in CLOCK_InitSysPll2()
606 … AUDIO_PLL_SPREAD_SPECTRUM_STEP(ss->step) | AUDIO_PLL_SPREAD_SPECTRUM_STOP(ss->stop) | in ANATOP_PllConfigure()
734 ANADIG_PLL->PLL_AUDIO_SS = ANADIG_PLL_PLL_AUDIO_SS_STEP(config->ss->step) | in CLOCK_GPC_SetAudioPllOutputFreq()
969 ANADIG_PLL->PLL_VIDEO_SS = ANADIG_PLL_PLL_VIDEO_SS_STEP(config->ss->step) | in CLOCK_GPC_SetVideoPllOutputFreq()
1096 ANADIG_PLL->SYS_PLL1_SS = ANADIG_PLL_SYS_PLL1_SS_STEP(config->ss->step) | in CLOCK_GPC_SetSysPll1OutputFreq()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1171/drivers/
Dfsl_gpc.c91 gpc_cm_tran_step_t step, in GPC_CM_ConfigCpuModeTransitionStep() argument
94 if (!((step >= kGPC_CM_SleepSP) && (step <= kGPC_CM_WakeupSP))) in GPC_CM_ConfigCpuModeTransitionStep()
96 uint32_t tmp32 = *(uint32_t *)((uint32_t)base + s_cmRegOffset[step]); in GPC_CM_ConfigCpuModeTransitionStep()
113 *(uint32_t *)((uint32_t)base + s_cmRegOffset[step]) = tmp32; in GPC_CM_ConfigCpuModeTransitionStep()
284 gpc_sp_tran_step_t step, in GPC_SP_ConfigSetPointTransitionStep() argument
287 uint32_t tmp32 = *(uint32_t *)((uint32_t)base + s_spRegOffset[step]); in GPC_SP_ConfigSetPointTransitionStep()
304 *(uint32_t *)((uint32_t)base + s_spRegOffset[step]) = tmp32; in GPC_SP_ConfigSetPointTransitionStep()
315 gpc_stby_tran_step_t step, in GPC_STBY_ConfigStandbyTransitionStep() argument
318 uint32_t tmp32 = *(uint32_t *)((uint32_t)base + s_stbyRegOffset[step]); in GPC_STBY_ConfigStandbyTransitionStep()
334 *(uint32_t *)((uint32_t)base + s_stbyRegOffset[step]) = tmp32; in GPC_STBY_ConfigStandbyTransitionStep()
Dfsl_gpc.h438 gpc_cm_tran_step_t step,
590 gpc_sp_tran_step_t step,
645 gpc_stby_tran_step_t step,
Dfsl_clock.c192 ss->step = (uint16_t)((mod << 1UL) * (uint32_t)(ss->stop) / XTAL_FREQ); in CLOCK_CalcPllSpreadSpectrum()
205 ANADIG_PLL_SYS_PLL2_SS_STEP(config->ss->step)) == ANADIG_PLL->SYS_PLL2_SS)) in CLOCK_InitSysPll2()
241 ANADIG_PLL_SYS_PLL2_SS_STEP(config->ss->step)); in CLOCK_InitSysPll2()
600 … AUDIO_PLL_SPREAD_SPECTRUM_STEP(ss->step) | AUDIO_PLL_SPREAD_SPECTRUM_STOP(ss->stop) | in ANATOP_PllConfigure()
728 ANADIG_PLL->PLL_AUDIO_SS = ANADIG_PLL_PLL_AUDIO_SS_STEP(config->ss->step) | in CLOCK_GPC_SetAudioPllOutputFreq()
978 ANADIG_PLL->PLL_VIDEO_SS = ANADIG_PLL_PLL_VIDEO_SS_STEP(config->ss->step) | in CLOCK_GPC_SetVideoPllOutputFreq()
1105 ANADIG_PLL->SYS_PLL1_SS = ANADIG_PLL_SYS_PLL1_SS_STEP(config->ss->step) | in CLOCK_GPC_SetSysPll1OutputFreq()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1173/drivers/
Dfsl_gpc.c91 gpc_cm_tran_step_t step, in GPC_CM_ConfigCpuModeTransitionStep() argument
94 if (!((step >= kGPC_CM_SleepSP) && (step <= kGPC_CM_WakeupSP))) in GPC_CM_ConfigCpuModeTransitionStep()
96 uint32_t tmp32 = *(uint32_t *)((uint32_t)base + s_cmRegOffset[step]); in GPC_CM_ConfigCpuModeTransitionStep()
113 *(uint32_t *)((uint32_t)base + s_cmRegOffset[step]) = tmp32; in GPC_CM_ConfigCpuModeTransitionStep()
284 gpc_sp_tran_step_t step, in GPC_SP_ConfigSetPointTransitionStep() argument
287 uint32_t tmp32 = *(uint32_t *)((uint32_t)base + s_spRegOffset[step]); in GPC_SP_ConfigSetPointTransitionStep()
304 *(uint32_t *)((uint32_t)base + s_spRegOffset[step]) = tmp32; in GPC_SP_ConfigSetPointTransitionStep()
315 gpc_stby_tran_step_t step, in GPC_STBY_ConfigStandbyTransitionStep() argument
318 uint32_t tmp32 = *(uint32_t *)((uint32_t)base + s_stbyRegOffset[step]); in GPC_STBY_ConfigStandbyTransitionStep()
334 *(uint32_t *)((uint32_t)base + s_stbyRegOffset[step]) = tmp32; in GPC_STBY_ConfigStandbyTransitionStep()
Dfsl_gpc.h438 gpc_cm_tran_step_t step,
590 gpc_sp_tran_step_t step,
645 gpc_stby_tran_step_t step,
Dfsl_clock.c192 ss->step = (uint16_t)((mod << 1UL) * (uint32_t)(ss->stop) / XTAL_FREQ); in CLOCK_CalcPllSpreadSpectrum()
205 ANADIG_PLL_SYS_PLL2_SS_STEP(config->ss->step)) == ANADIG_PLL->SYS_PLL2_SS)) in CLOCK_InitSysPll2()
241 ANADIG_PLL_SYS_PLL2_SS_STEP(config->ss->step)); in CLOCK_InitSysPll2()
600 … AUDIO_PLL_SPREAD_SPECTRUM_STEP(ss->step) | AUDIO_PLL_SPREAD_SPECTRUM_STOP(ss->stop) | in ANATOP_PllConfigure()
728 ANADIG_PLL->PLL_AUDIO_SS = ANADIG_PLL_PLL_AUDIO_SS_STEP(config->ss->step) | in CLOCK_GPC_SetAudioPllOutputFreq()
978 ANADIG_PLL->PLL_VIDEO_SS = ANADIG_PLL_PLL_VIDEO_SS_STEP(config->ss->step) | in CLOCK_GPC_SetVideoPllOutputFreq()
1105 ANADIG_PLL->SYS_PLL1_SS = ANADIG_PLL_SYS_PLL1_SS_STEP(config->ss->step) | in CLOCK_GPC_SetSysPll1OutputFreq()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1172/drivers/
Dfsl_gpc.c91 gpc_cm_tran_step_t step, in GPC_CM_ConfigCpuModeTransitionStep() argument
94 if (!((step >= kGPC_CM_SleepSP) && (step <= kGPC_CM_WakeupSP))) in GPC_CM_ConfigCpuModeTransitionStep()
96 uint32_t tmp32 = *(uint32_t *)((uint32_t)base + s_cmRegOffset[step]); in GPC_CM_ConfigCpuModeTransitionStep()
113 *(uint32_t *)((uint32_t)base + s_cmRegOffset[step]) = tmp32; in GPC_CM_ConfigCpuModeTransitionStep()
284 gpc_sp_tran_step_t step, in GPC_SP_ConfigSetPointTransitionStep() argument
287 uint32_t tmp32 = *(uint32_t *)((uint32_t)base + s_spRegOffset[step]); in GPC_SP_ConfigSetPointTransitionStep()
304 *(uint32_t *)((uint32_t)base + s_spRegOffset[step]) = tmp32; in GPC_SP_ConfigSetPointTransitionStep()
315 gpc_stby_tran_step_t step, in GPC_STBY_ConfigStandbyTransitionStep() argument
318 uint32_t tmp32 = *(uint32_t *)((uint32_t)base + s_stbyRegOffset[step]); in GPC_STBY_ConfigStandbyTransitionStep()
334 *(uint32_t *)((uint32_t)base + s_stbyRegOffset[step]) = tmp32; in GPC_STBY_ConfigStandbyTransitionStep()
Dfsl_gpc.h438 gpc_cm_tran_step_t step,
590 gpc_sp_tran_step_t step,
645 gpc_stby_tran_step_t step,
Dfsl_clock.c192 ss->step = (uint16_t)((mod << 1UL) * (uint32_t)(ss->stop) / XTAL_FREQ); in CLOCK_CalcPllSpreadSpectrum()
205 ANADIG_PLL_SYS_PLL2_SS_STEP(config->ss->step)) == ANADIG_PLL->SYS_PLL2_SS)) in CLOCK_InitSysPll2()
241 ANADIG_PLL_SYS_PLL2_SS_STEP(config->ss->step)); in CLOCK_InitSysPll2()
600 … AUDIO_PLL_SPREAD_SPECTRUM_STEP(ss->step) | AUDIO_PLL_SPREAD_SPECTRUM_STOP(ss->stop) | in ANATOP_PllConfigure()
728 ANADIG_PLL->PLL_AUDIO_SS = ANADIG_PLL_PLL_AUDIO_SS_STEP(config->ss->step) | in CLOCK_GPC_SetAudioPllOutputFreq()
978 ANADIG_PLL->PLL_VIDEO_SS = ANADIG_PLL_PLL_VIDEO_SS_STEP(config->ss->step) | in CLOCK_GPC_SetVideoPllOutputFreq()
1105 ANADIG_PLL->SYS_PLL1_SS = ANADIG_PLL_SYS_PLL1_SS_STEP(config->ss->step) | in CLOCK_GPC_SetSysPll1OutputFreq()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1165/drivers/
Dfsl_gpc.c91 gpc_cm_tran_step_t step, in GPC_CM_ConfigCpuModeTransitionStep() argument
94 if (!((step >= kGPC_CM_SleepSP) && (step <= kGPC_CM_WakeupSP))) in GPC_CM_ConfigCpuModeTransitionStep()
96 uint32_t tmp32 = *(uint32_t *)((uint32_t)base + s_cmRegOffset[step]); in GPC_CM_ConfigCpuModeTransitionStep()
113 *(uint32_t *)((uint32_t)base + s_cmRegOffset[step]) = tmp32; in GPC_CM_ConfigCpuModeTransitionStep()
284 gpc_sp_tran_step_t step, in GPC_SP_ConfigSetPointTransitionStep() argument
287 uint32_t tmp32 = *(uint32_t *)((uint32_t)base + s_spRegOffset[step]); in GPC_SP_ConfigSetPointTransitionStep()
304 *(uint32_t *)((uint32_t)base + s_spRegOffset[step]) = tmp32; in GPC_SP_ConfigSetPointTransitionStep()
315 gpc_stby_tran_step_t step, in GPC_STBY_ConfigStandbyTransitionStep() argument
318 uint32_t tmp32 = *(uint32_t *)((uint32_t)base + s_stbyRegOffset[step]); in GPC_STBY_ConfigStandbyTransitionStep()
334 *(uint32_t *)((uint32_t)base + s_stbyRegOffset[step]) = tmp32; in GPC_STBY_ConfigStandbyTransitionStep()
Dfsl_gpc.h438 gpc_cm_tran_step_t step,
590 gpc_sp_tran_step_t step,
645 gpc_stby_tran_step_t step,
Dfsl_clock.c192 ss->step = (uint16_t)((mod << 1UL) * (uint32_t)(ss->stop) / XTAL_FREQ); in CLOCK_CalcPllSpreadSpectrum()
205 ANADIG_PLL_SYS_PLL2_SS_STEP(config->ss->step)) == ANADIG_PLL->SYS_PLL2_SS)) in CLOCK_InitSysPll2()
241 ANADIG_PLL_SYS_PLL2_SS_STEP(config->ss->step)); in CLOCK_InitSysPll2()
606 … AUDIO_PLL_SPREAD_SPECTRUM_STEP(ss->step) | AUDIO_PLL_SPREAD_SPECTRUM_STOP(ss->stop) | in ANATOP_PllConfigure()
734 ANADIG_PLL->PLL_AUDIO_SS = ANADIG_PLL_PLL_AUDIO_SS_STEP(config->ss->step) | in CLOCK_GPC_SetAudioPllOutputFreq()
969 ANADIG_PLL->PLL_VIDEO_SS = ANADIG_PLL_PLL_VIDEO_SS_STEP(config->ss->step) | in CLOCK_GPC_SetVideoPllOutputFreq()
1096 ANADIG_PLL->SYS_PLL1_SS = ANADIG_PLL_SYS_PLL1_SS_STEP(config->ss->step) | in CLOCK_GPC_SetSysPll1OutputFreq()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1175/drivers/
Dfsl_gpc.c91 gpc_cm_tran_step_t step, in GPC_CM_ConfigCpuModeTransitionStep() argument
94 if (!((step >= kGPC_CM_SleepSP) && (step <= kGPC_CM_WakeupSP))) in GPC_CM_ConfigCpuModeTransitionStep()
96 uint32_t tmp32 = *(uint32_t *)((uint32_t)base + s_cmRegOffset[step]); in GPC_CM_ConfigCpuModeTransitionStep()
113 *(uint32_t *)((uint32_t)base + s_cmRegOffset[step]) = tmp32; in GPC_CM_ConfigCpuModeTransitionStep()
284 gpc_sp_tran_step_t step, in GPC_SP_ConfigSetPointTransitionStep() argument
287 uint32_t tmp32 = *(uint32_t *)((uint32_t)base + s_spRegOffset[step]); in GPC_SP_ConfigSetPointTransitionStep()
304 *(uint32_t *)((uint32_t)base + s_spRegOffset[step]) = tmp32; in GPC_SP_ConfigSetPointTransitionStep()
315 gpc_stby_tran_step_t step, in GPC_STBY_ConfigStandbyTransitionStep() argument
318 uint32_t tmp32 = *(uint32_t *)((uint32_t)base + s_stbyRegOffset[step]); in GPC_STBY_ConfigStandbyTransitionStep()
334 *(uint32_t *)((uint32_t)base + s_stbyRegOffset[step]) = tmp32; in GPC_STBY_ConfigStandbyTransitionStep()
Dfsl_gpc.h438 gpc_cm_tran_step_t step,
590 gpc_sp_tran_step_t step,
645 gpc_stby_tran_step_t step,
Dfsl_clock.c192 ss->step = (uint16_t)((mod << 1UL) * (uint32_t)(ss->stop) / XTAL_FREQ); in CLOCK_CalcPllSpreadSpectrum()
205 ANADIG_PLL_SYS_PLL2_SS_STEP(config->ss->step)) == ANADIG_PLL->SYS_PLL2_SS)) in CLOCK_InitSysPll2()
241 ANADIG_PLL_SYS_PLL2_SS_STEP(config->ss->step)); in CLOCK_InitSysPll2()
600 … AUDIO_PLL_SPREAD_SPECTRUM_STEP(ss->step) | AUDIO_PLL_SPREAD_SPECTRUM_STOP(ss->stop) | in ANATOP_PllConfigure()
728 ANADIG_PLL->PLL_AUDIO_SS = ANADIG_PLL_PLL_AUDIO_SS_STEP(config->ss->step) | in CLOCK_GPC_SetAudioPllOutputFreq()
978 ANADIG_PLL->PLL_VIDEO_SS = ANADIG_PLL_PLL_VIDEO_SS_STEP(config->ss->step) | in CLOCK_GPC_SetVideoPllOutputFreq()
1105 ANADIG_PLL->SYS_PLL1_SS = ANADIG_PLL_SYS_PLL1_SS_STEP(config->ss->step) | in CLOCK_GPC_SetSysPll1OutputFreq()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1176/drivers/
Dfsl_gpc.c91 gpc_cm_tran_step_t step, in GPC_CM_ConfigCpuModeTransitionStep() argument
94 if (!((step >= kGPC_CM_SleepSP) && (step <= kGPC_CM_WakeupSP))) in GPC_CM_ConfigCpuModeTransitionStep()
96 uint32_t tmp32 = *(uint32_t *)((uint32_t)base + s_cmRegOffset[step]); in GPC_CM_ConfigCpuModeTransitionStep()
113 *(uint32_t *)((uint32_t)base + s_cmRegOffset[step]) = tmp32; in GPC_CM_ConfigCpuModeTransitionStep()
284 gpc_sp_tran_step_t step, in GPC_SP_ConfigSetPointTransitionStep() argument
287 uint32_t tmp32 = *(uint32_t *)((uint32_t)base + s_spRegOffset[step]); in GPC_SP_ConfigSetPointTransitionStep()
304 *(uint32_t *)((uint32_t)base + s_spRegOffset[step]) = tmp32; in GPC_SP_ConfigSetPointTransitionStep()
315 gpc_stby_tran_step_t step, in GPC_STBY_ConfigStandbyTransitionStep() argument
318 uint32_t tmp32 = *(uint32_t *)((uint32_t)base + s_stbyRegOffset[step]); in GPC_STBY_ConfigStandbyTransitionStep()
334 *(uint32_t *)((uint32_t)base + s_stbyRegOffset[step]) = tmp32; in GPC_STBY_ConfigStandbyTransitionStep()
Dfsl_gpc.h438 gpc_cm_tran_step_t step,
590 gpc_sp_tran_step_t step,
645 gpc_stby_tran_step_t step,
Dfsl_clock.c192 ss->step = (uint16_t)((mod << 1UL) * (uint32_t)(ss->stop) / XTAL_FREQ); in CLOCK_CalcPllSpreadSpectrum()
205 ANADIG_PLL_SYS_PLL2_SS_STEP(config->ss->step)) == ANADIG_PLL->SYS_PLL2_SS)) in CLOCK_InitSysPll2()
241 ANADIG_PLL_SYS_PLL2_SS_STEP(config->ss->step)); in CLOCK_InitSysPll2()
600 … AUDIO_PLL_SPREAD_SPECTRUM_STEP(ss->step) | AUDIO_PLL_SPREAD_SPECTRUM_STOP(ss->stop) | in ANATOP_PllConfigure()
728 ANADIG_PLL->PLL_AUDIO_SS = ANADIG_PLL_PLL_AUDIO_SS_STEP(config->ss->step) | in CLOCK_GPC_SetAudioPllOutputFreq()
978 ANADIG_PLL->PLL_VIDEO_SS = ANADIG_PLL_PLL_VIDEO_SS_STEP(config->ss->step) | in CLOCK_GPC_SetVideoPllOutputFreq()
1105 ANADIG_PLL->SYS_PLL1_SS = ANADIG_PLL_SYS_PLL1_SS_STEP(config->ss->step) | in CLOCK_GPC_SetSysPll1OutputFreq()
/hal_nxp-3.6.0/mcux/mcux-sdk/CMSIS/DSP/Source/SupportFunctions/
Darm_bitonic_sort_f32.c37 uint32_t step; in arm_bitonic_sort_core_f32() local
42 step = n>>1; in arm_bitonic_sort_core_f32()
46 for(k=0; k<step; k++) in arm_bitonic_sort_core_f32()
61 for(step=(n>>2); step>0; step/=2) in arm_bitonic_sort_core_f32()
63 for(j=0; j<n; j=j+step*2) in arm_bitonic_sort_core_f32()
66 rightPtr = pSrc+j+step; in arm_bitonic_sort_core_f32()
68 for(k=0; k<step; k++) in arm_bitonic_sort_core_f32()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MCIMX7U3/drivers/
Dfsl_clock.h1695 static inline void CLOCK_EnableAuxPllSpectrumModulation(uint16_t step, uint16_t stop) in CLOCK_EnableAuxPllSpectrumModulation() argument
1698 (SCG_APLLSS_STEP(step) | SCG_APLLSS_STOP(stop) | SCG_APLLSS_ENABLE_MASK); in CLOCK_EnableAuxPllSpectrumModulation()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MCIMX7U5/drivers/
Dfsl_clock.h1695 static inline void CLOCK_EnableAuxPllSpectrumModulation(uint16_t step, uint16_t stop) in CLOCK_EnableAuxPllSpectrumModulation() argument
1698 (SCG_APLLSS_STEP(step) | SCG_APLLSS_STOP(stop) | SCG_APLLSS_ENABLE_MASK); in CLOCK_EnableAuxPllSpectrumModulation()
/hal_nxp-3.6.0/mcux/mcux-sdk/drivers/usdhc/
Dfsl_usdhc.h1454 void USDHC_EnableStandardTuning(USDHC_Type *base, uint32_t tuningStartTap, uint32_t step, bool enab…

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