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/hal_nxp-3.6.0/mcux/mcux-sdk/components/css_pkc/src/comps/mcuxClMemory/inc/
DmcuxClMemory_Endianness.h77 #define mcuxClMemory_LoadLittleEndian32( source ) \ argument
78 ( (((uint32_t) (source)[0]) << 0u) | \
79 (((uint32_t) (source)[1]) << 8u) | \
80 (((uint32_t) (source)[2]) << 16u) | \
81 (((uint32_t) (source)[3]) << 24u) )
91 #define mcuxClMemory_LoadBigEndian32( source ) \ argument
92 ( (((uint32_t) (source)[0]) << 24u) | \
93 (((uint32_t) (source)[1]) << 16u) | \
94 (((uint32_t) (source)[2]) << 8u) | \
95 (((uint32_t) (source)[3]) << 0u) )
/hal_nxp-3.6.0/mcux/mcux-sdk/
DSW-Content-Register.txt9 Format: source code, binary, project files, linker
23 Format: source code
54 Format: source code, header files, firmware
65 Format: source code
76 Format: source code, linker files
86 Format: source code
96 Format: source code
109 Format: source code
139 Approved open source license: Yes
141 Format: source code
[all …]
DCONTRIBUTING.md21 …rces using BSD-3-Clause license, you may see similar copyright as below in the head of source file.
34 …ution, and you allow our project to use your contribution under the open source license. The full …
51 have the right to submit it under the open source license
55 of my knowledge, is covered under an appropriate open source
58 by me, under the same open source license (unless I am
70 this project or the open source license(s) involved.
/hal_nxp-3.6.0/mcux/mcux-sdk/components/pf1550/
Dfsl_pf1550.c429 …50_EnableInterrupts(pf1550_handle_t *handle, pf1550_interrupt_category_t category, uint32_t source) in PF1550_EnableInterrupts() argument
437 (void)PF1550_ModifyReg(handle, PF1550_CHG_INT_MASK, (uint8_t)(source & 0xFFU), 0x0U); in PF1550_EnableInterrupts()
442 (void)PF1550_ModifyReg(handle, PF1550_SW_INT_MASK0, (uint8_t)(source & 0xFFU), 0x0U); in PF1550_EnableInterrupts()
444 … (void)PF1550_ModifyReg(handle, PF1550_SW_INT_MASK1, (uint8_t)((source & 0xFF00U) >> 8U), 0x0U); in PF1550_EnableInterrupts()
446 … (void)PF1550_ModifyReg(handle, PF1550_SW_INT_MASK2, (uint8_t)((source & 0xFF0000U) >> 16U), 0x0U); in PF1550_EnableInterrupts()
451 (void)PF1550_ModifyReg(handle, PF1550_LDO_INT_MASK0, (uint8_t)(source & 0xFFU), 0x0U); in PF1550_EnableInterrupts()
456 (void)PF1550_ModifyReg(handle, PF1550_ONKEY_INT_MASK0, (uint8_t)(source & 0xFFU), 0x0U); in PF1550_EnableInterrupts()
461 (void)PF1550_ModifyReg(handle, PF1550_TEMP_INT_MASK0, (uint8_t)(source & 0xFFU), 0x0U); in PF1550_EnableInterrupts()
466 (void)PF1550_ModifyReg(handle, PF1550_MISC_INT_MASK0, (uint8_t)(source & 0xFFU), 0x0U); in PF1550_EnableInterrupts()
475 …0_DisableInterrupts(pf1550_handle_t *handle, pf1550_interrupt_category_t category, uint32_t source) in PF1550_DisableInterrupts() argument
[all …]
Dfsl_pf1550.h572 …0_EnableInterrupts(pf1550_handle_t *handle, pf1550_interrupt_category_t category, uint32_t source);
591 …_DisableInterrupts(pf1550_handle_t *handle, pf1550_interrupt_category_t category, uint32_t source);
640 …earInterruptStatus(pf1550_handle_t *handle, pf1550_interrupt_category_t category, uint32_t source);
/hal_nxp-3.6.0/imx/drivers/
Dgpt.c65 void GPT_SetClockSource(GPT_Type* base, uint32_t source) in GPT_SetClockSource() argument
67 assert(source <= gptClockSourceOsc); in GPT_SetClockSource()
69 if (source == gptClockSourceOsc) in GPT_SetClockSource()
70 base->CR = (base->CR & ~GPT_CR_CLKSRC_MASK) | GPT_CR_EN_24M_MASK | GPT_CR_CLKSRC(source); in GPT_SetClockSource()
72 base->CR = (base->CR & ~(GPT_CR_CLKSRC_MASK | GPT_CR_EN_24M_MASK)) | GPT_CR_CLKSRC(source); in GPT_SetClockSource()
Decspi.c81 void ECSPI_SetSampClockSource(ECSPI_Type* base, uint32_t source) in ECSPI_SetSampClockSource() argument
84 if(source == ecspiSclk) in ECSPI_SetSampClockSource()
159 void ECSPI_SetDMACmd(ECSPI_Type* base, uint32_t source, bool enable) in ECSPI_SetDMACmd() argument
163 ECSPI_DMAREG_REG(base) |= ((uint32_t)(1 << source)); in ECSPI_SetDMACmd()
165 ECSPI_DMAREG_REG(base) &= ~((uint32_t)(1 << source)); in ECSPI_SetDMACmd()
Depit.h116 static inline void EPIT_SetClockSource(EPIT_Type* base, uint32_t source) in EPIT_SetClockSource() argument
118 EPIT_CR_REG(base) = (EPIT_CR_REG(base) & ~EPIT_CR_CLKSRC_MASK) | EPIT_CR_CLKSRC(source); in EPIT_SetClockSource()
/hal_nxp-3.6.0/mcux/mcux-sdk/CMSIS/NN/Source/NNSupportFunctions/
Darm_q7_to_q15_with_offset.c48 int16x8_t source; in arm_q7_to_q15_with_offset() local
54 source = vldrbq_s16(src); in arm_q7_to_q15_with_offset()
55 source = vaddq_s16(source, source_offset); in arm_q7_to_q15_with_offset()
56 vstrhq_s16(dst, source); in arm_q7_to_q15_with_offset()
/hal_nxp-3.6.0/mcux/mcux-sdk/CMSIS/NN/Source/PoolingFunctions/
Darm_max_pool_s8.c97 static void clamp_output(q7_t *source, int32_t length, const int32_t act_min, const int32_t act_max) in clamp_output() argument
105 const int8x16_t src = vldrbq_z_s8(source, p); in clamp_output()
110 vstrbq_p_s8(source, res, p); in clamp_output()
111 source += 16; in clamp_output()
119 in.word = arm_nn_read_q7x4(source); in clamp_output()
130 write_q7x4_ia(&source, in.word); in clamp_output()
137 int32_t comp = *source; in clamp_output()
140 *source++ = (int8_t)comp; in clamp_output()
/hal_nxp-3.6.0/mcux/mcux-sdk/components/pca9420/
Dfsl_pca9420.c445 void PCA9420_EnableInterrupts(pca9420_handle_t *handle, uint32_t source) in PCA9420_EnableInterrupts() argument
461 regValues[1] &= (uint8_t)(~(source & 0xFFU)); /* SUB_INT0_MASK */ in PCA9420_EnableInterrupts()
462 regValues[3] &= (uint8_t)(~((source >> 8) & 0xFFU)); /* SUB_INT1_MASK */ in PCA9420_EnableInterrupts()
463 regValues[5] &= (uint8_t)(~((source >> 16) & 0xFFU)); /* SUB_INT2_MASK */ in PCA9420_EnableInterrupts()
472 void PCA9420_DisableInterrupts(pca9420_handle_t *handle, uint32_t source) in PCA9420_DisableInterrupts() argument
488 regValues[1] |= (uint8_t)(source & 0xFFU); /* SUB_INT0_MASK */ in PCA9420_DisableInterrupts()
489 regValues[3] |= (uint8_t)((source >> 8) & 0xFFU); /* SUB_INT1_MASK */ in PCA9420_DisableInterrupts()
490 regValues[5] |= (uint8_t)((source >> 16) & 0xFFU); /* SUB_INT2_MASK */ in PCA9420_DisableInterrupts()
516 void PCA9420_ClearInterruptStatus(pca9420_handle_t *handle, uint32_t source) in PCA9420_ClearInterruptStatus() argument
530 regValues[0] = (uint8_t)(source & 0xFFU); /* SUB_INT1 */ in PCA9420_ClearInterruptStatus()
[all …]
Dfsl_pca9420.h819 void PCA9420_EnableInterrupts(pca9420_handle_t *handle, uint32_t source);
831 void PCA9420_DisableInterrupts(pca9420_handle_t *handle, uint32_t source);
855 void PCA9420_ClearInterruptStatus(pca9420_handle_t *handle, uint32_t source);
/hal_nxp-3.6.0/mcux/mcux-sdk/components/pf3000/
Dfsl_pf3000.c642 void PF3000_EnableInterrupts(pf3000_handle_t *handle, uint32_t source) in PF3000_EnableInterrupts() argument
647 PF3000_ModifyReg(handle, PF3000_SW_INT_MASK0, (source & 0xFFU), 0x0U); in PF3000_EnableInterrupts()
649 PF3000_ModifyReg(handle, PF3000_SW_INT_MASK1, ((source & 0xFF00U) >> 8U), 0x0U); in PF3000_EnableInterrupts()
651 PF3000_ModifyReg(handle, PF3000_SW_INT_MASK3, ((source & 0xFF0000U) >> 16U), 0x0U); in PF3000_EnableInterrupts()
653 PF3000_ModifyReg(handle, PF3000_SW_INT_MASK4, ((source & 0xFF000000U) >> 24), 0x0U); in PF3000_EnableInterrupts()
656 void PF3000_DisableInterrupts(pf3000_handle_t *handle, uint32_t source) in PF3000_DisableInterrupts() argument
661 PF3000_ModifyReg(handle, PF3000_SW_INT_MASK0, 0x0U, (source & 0xFFU)); in PF3000_DisableInterrupts()
663 PF3000_ModifyReg(handle, PF3000_SW_INT_MASK1, 0x0U, ((source & 0xFF00U) >> 8U)); in PF3000_DisableInterrupts()
665 PF3000_ModifyReg(handle, PF3000_SW_INT_MASK3, 0x0U, ((source & 0xFF0000U) >> 16U)); in PF3000_DisableInterrupts()
667 PF3000_ModifyReg(handle, PF3000_SW_INT_MASK4, 0x0U, ((source & 0xFF000000U) >> 24)); in PF3000_DisableInterrupts()
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Dfsl_pf3000.h464 void PF3000_EnableInterrupts(pf3000_handle_t *handle, uint32_t source);
476 void PF3000_DisableInterrupts(pf3000_handle_t *handle, uint32_t source);
500 void PF3000_ClearInterruptStatus(pf3000_handle_t *handle, uint32_t source);
/hal_nxp-3.6.0/mcux/mcux-sdk/components/power_manager/
DREADME.md57 - The wakeup-source manager module: configures the wakeup sources and processes registered wakeup-s…
74 - **PM_InitWakeupSource** --> OPTIONAL ; Initialize the wakeup source.
76 - **PM_RegisterTimerController** --> OPTIONAL ; Register a timer as a wakeup source, to be called w…
139 …en by declaring the wakeup-source parameter in the application. In this example, the button SW2 wi…
152 `/* Configure the Input Mux block and connect the trigger source to PinInt channel. */`
285 If low power timer is the wakeup source, please remember to register it into power manager by using…
289 …nction, this parameter can be NULL, and it means low power timer is not set as the wakeup source.
342 Initialize the wakeup source object.
346 wsId : Used to select the wakeup source, the wsId of each wakeup source can be found in fsl_pm_devi…
347 service : The function to be invoked when wake up source asserted.
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/hal_nxp-3.6.0/mcux/mcux-sdk/CMSIS/NN/Include/
Darm_nnsupportfunctions.h571 __STATIC_FORCEINLINE const q7_t *read_and_pad(const q7_t *source, q31_t *out1, q31_t *out2) in read_and_pad() argument
573 q31_t inA = arm_nn_read_q7x4_ia(&source); in read_and_pad()
585 return source; in read_and_pad()
592 __STATIC_FORCEINLINE const q7_t *read_and_pad_reordered(const q7_t *source, q31_t *out1, q31_t *out… in read_and_pad_reordered() argument
594 q31_t inA = arm_nn_read_q7x4_ia(&source); in read_and_pad_reordered()
603 return source; in read_and_pad_reordered()
610 read_and_pad_reordered_with_offset(const q7_t *source, q31_t *out1, q31_t *out2, q31_t offset) in read_and_pad_reordered_with_offset() argument
612 q31_t inA = arm_nn_read_q7x4_ia(&source); in read_and_pad_reordered_with_offset()
624 return source; in read_and_pad_reordered_with_offset()
/hal_nxp-3.6.0/mcux/mcux-sdk/drivers/dmamux/
Dfsl_dmamux.h110 static inline void DMAMUX_SetSource(DMAMUX_Type *base, uint32_t channel, int32_t source) in DMAMUX_SetSource() argument
115 …HCFG[channel] = ((base->CHCFG[channel] & ~DMAMUX_CHCFG_SOURCE_MASK) | DMAMUX_CHCFG_SOURCE(source)); in DMAMUX_SetSource()
117 …nel] = (uint8_t)((base->CHCFG[channel] & ~DMAMUX_CHCFG_SOURCE_MASK) | DMAMUX_CHCFG_SOURCE(source)); in DMAMUX_SetSource()
/hal_nxp-3.6.0/mcux/middleware/mcux-sdk-middleware-usb/
Dset_middleware_usb.cmake248 ${CMAKE_CURRENT_LIST_DIR}/./output/source/device/class/usb_device_class.c
249 ${CMAKE_CURRENT_LIST_DIR}/./output/source/device/usb_device_ch9.c
253 ${CMAKE_CURRENT_LIST_DIR}/./output/source/device/class
254 ${CMAKE_CURRENT_LIST_DIR}/./output/source/device
274 ${CMAKE_CURRENT_LIST_DIR}/./output/source/device/class/usb_device_audio.c
278 ${CMAKE_CURRENT_LIST_DIR}/./output/source/device/class
298 ${CMAKE_CURRENT_LIST_DIR}/./output/source/device/class/usb_device_cdc_acm.c
302 ${CMAKE_CURRENT_LIST_DIR}/./output/source/device/class
322 ${CMAKE_CURRENT_LIST_DIR}/./output/source/device/class/usb_device_cdc_rndis.c
326 ${CMAKE_CURRENT_LIST_DIR}/./output/source/device/class
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Dmiddleware_usb_device_stack_external.cmake6 ${CMAKE_CURRENT_LIST_DIR}/output/source/device/class/usb_device_class.c
7 ${CMAKE_CURRENT_LIST_DIR}/output/source/device/usb_device_ch9.c
11 ${CMAKE_CURRENT_LIST_DIR}/output/source/device
12 ${CMAKE_CURRENT_LIST_DIR}/output/source/device/class
Dmiddleware_usb_device_cdc_external.cmake6 ${CMAKE_CURRENT_LIST_DIR}/output/source/device/class/usb_device_cdc_acm.c
10 ${CMAKE_CURRENT_LIST_DIR}/output/source/device/class
/hal_nxp-3.6.0/mcux/mcux-sdk/components/rtt/
DLicense.txt8 to or modify the source code of this software in order to stay
11 Redistribution and use in source and binary forms, with or
15 o Redistributions of source code must retain the above copyright
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX9352/drivers/
Dfsl_edma_soc.h188 #define EDMA_CHANNEL_HAS_REQUEST_SOURCE(base, source) ((base) == DMA3 ? ((source)&0x100U) : ((sourc… argument
/hal_nxp-3.6.0/mcux/mcux-sdk/drivers/smartdma/
Dfsl_smartdma_prv.h281 #define E_MOV(dest, source) DCD 0x0 + (source << 14) + (dest << 10) + (EU << 5) argument
282 #define E_MOVS(dest, source) DCD 0x0 + (source << 14) + (dest << 10) + (1 << 9) + (EU <<… argument
283 #define E_COND_MOV(cond, dest, source) DCD 0x0 + (source << 14) + (dest << 10) + (cond << 5) argument
284 #define E_COND_MOVS(cond, dest, source) DCD 0x0 + (source << 14) + (dest << 10) + (1 << 9) + (cond … argument
287 #define E_MVN(dest, source) DCD 0x0 + (source << 14) + (dest << 10) + (EU << 5) + (1 <<… argument
288 #define E_MVNS(dest, source) DCD 0x0 + (source << 14) + (dest << 10) + (1 << 9) + (EU <<… argument
289 #define E_COND_MVN(cond, dest, source) DCD 0x0 + (source << 14) + (dest << 10) + (cond << 5) + (1 … argument
290 #define E_COND_MVNS(cond, dest, source) DCD 0x0 + (source << 14) + (dest << 10) + (1 << 9) + (cond … argument
345 #define E_LDR(dest, source, offset8s) … argument
346 …DCD 0x1 + (0 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (0 << 20) + (1 << 18) + (…
[all …]
/hal_nxp-3.6.0/mcux/mcux-sdk/drivers/sdma/
Dfsl_sdma.c534 bool SDMA_GetRequestSourceStatus(SDMAARM_Type *base, uint32_t source) in SDMA_GetRequestSourceStatus() argument
536 if (source < 32U) in SDMA_GetRequestSourceStatus()
538 return ((base->EVT_MIRROR & (1UL << source)) >> source) != 0UL; in SDMA_GetRequestSourceStatus()
542 source -= 32U; in SDMA_GetRequestSourceStatus()
543 return ((base->EVT_MIRROR2 & (1UL << source)) >> source) != 0UL; in SDMA_GetRequestSourceStatus()
/hal_nxp-3.6.0/mcux/mcux-sdk/drivers/asrc/
Dfsl_asrc.h57 #define ASRC_ASRCSR_INPUT_CLOCK_SOURCE(source, index) \ argument
58 ((uint32_t)((uint32_t)(source) << (ASRC_ASRCSR_AICSA_SHIFT + (uint32_t)(index)*4U)) & \
61 #define ASRC_ASRCSR_OUTPUT_CLOCK_SOURCE(source, index) \ argument
62 ((uint32_t)((uint32_t)(source) << (ASRC_ASRCSR_AOCSA_SHIFT + (uint32_t)(index)*4U)) & \

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