Home
last modified time | relevance | path

Searched refs:refClkFreq (Results 1 – 25 of 70) sorted by relevance

123

/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MD6/
Dsystem_MIMX8MD6_cm4.c76 uint32_t refClkFreq = 0U; in GetFracPllFreq() local
92 refClkFreq = CPU_XTAL_SOSC_CLK_25MHZ; in GetFracPllFreq()
97 refClkFreq = CPU_XTAL_SOSC_CLK_27MHZ; in GetFracPllFreq()
101 …refClkFreq = CLK_P_N_FREQ; /* CLK_P_N Clock, please note that the value is 0hz by default, it coul… in GetFracPllFreq()
104 refClkFreq /= (uint32_t)refDiv + 1U; in GetFracPllFreq()
105 …fracClk = (uint64_t)refClkFreq * 8U * (1U + intDiv) + (((uint64_t)refClkFreq * 8U * fracDiv) >> 24… in GetFracPllFreq()
115 uint32_t refClkFreq = 0U; in GetSSCGPllFreq() local
140 refClkFreq = CPU_XTAL_SOSC_CLK_25MHZ; in GetSSCGPllFreq()
145 refClkFreq = CPU_XTAL_SOSC_CLK_27MHZ; in GetSSCGPllFreq()
149 …refClkFreq = CLK_P_N_FREQ; /* CLK_P_N Clock, please note that the value is 0hz by default, it coul… in GetSSCGPllFreq()
[all …]
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MD7/
Dsystem_MIMX8MD7_cm4.c76 uint32_t refClkFreq = 0U; in GetFracPllFreq() local
92 refClkFreq = CPU_XTAL_SOSC_CLK_25MHZ; in GetFracPllFreq()
97 refClkFreq = CPU_XTAL_SOSC_CLK_27MHZ; in GetFracPllFreq()
101 …refClkFreq = CLK_P_N_FREQ; /* CLK_P_N Clock, please note that the value is 0hz by default, it coul… in GetFracPllFreq()
104 refClkFreq /= (uint32_t)refDiv + 1U; in GetFracPllFreq()
105 …fracClk = (uint64_t)refClkFreq * 8U * (1U + intDiv) + (((uint64_t)refClkFreq * 8U * fracDiv) >> 24… in GetFracPllFreq()
115 uint32_t refClkFreq = 0U; in GetSSCGPllFreq() local
140 refClkFreq = CPU_XTAL_SOSC_CLK_25MHZ; in GetSSCGPllFreq()
145 refClkFreq = CPU_XTAL_SOSC_CLK_27MHZ; in GetSSCGPllFreq()
149 …refClkFreq = CLK_P_N_FREQ; /* CLK_P_N Clock, please note that the value is 0hz by default, it coul… in GetSSCGPllFreq()
[all …]
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MQ7/
Dsystem_MIMX8MQ7_cm4.c76 uint32_t refClkFreq = 0U; in GetFracPllFreq() local
92 refClkFreq = CPU_XTAL_SOSC_CLK_25MHZ; in GetFracPllFreq()
97 refClkFreq = CPU_XTAL_SOSC_CLK_27MHZ; in GetFracPllFreq()
101 …refClkFreq = CLK_P_N_FREQ; /* CLK_P_N Clock, please note that the value is 0hz by default, it coul… in GetFracPllFreq()
104 refClkFreq /= (uint32_t)refDiv + 1U; in GetFracPllFreq()
105 …fracClk = (uint64_t)refClkFreq * 8U * (1U + intDiv) + (((uint64_t)refClkFreq * 8U * fracDiv) >> 24… in GetFracPllFreq()
115 uint32_t refClkFreq = 0U; in GetSSCGPllFreq() local
140 refClkFreq = CPU_XTAL_SOSC_CLK_25MHZ; in GetSSCGPllFreq()
145 refClkFreq = CPU_XTAL_SOSC_CLK_27MHZ; in GetSSCGPllFreq()
149 …refClkFreq = CLK_P_N_FREQ; /* CLK_P_N Clock, please note that the value is 0hz by default, it coul… in GetSSCGPllFreq()
[all …]
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MQ6/
Dsystem_MIMX8MQ6_cm4.c76 uint32_t refClkFreq = 0U; in GetFracPllFreq() local
92 refClkFreq = CPU_XTAL_SOSC_CLK_25MHZ; in GetFracPllFreq()
97 refClkFreq = CPU_XTAL_SOSC_CLK_27MHZ; in GetFracPllFreq()
101 …refClkFreq = CLK_P_N_FREQ; /* CLK_P_N Clock, please note that the value is 0hz by default, it coul… in GetFracPllFreq()
104 refClkFreq /= (uint32_t)refDiv + 1U; in GetFracPllFreq()
105 …fracClk = (uint64_t)refClkFreq * 8U * (1U + intDiv) + (((uint64_t)refClkFreq * 8U * fracDiv) >> 24… in GetFracPllFreq()
115 uint32_t refClkFreq = 0U; in GetSSCGPllFreq() local
140 refClkFreq = CPU_XTAL_SOSC_CLK_25MHZ; in GetSSCGPllFreq()
145 refClkFreq = CPU_XTAL_SOSC_CLK_27MHZ; in GetSSCGPllFreq()
149 …refClkFreq = CLK_P_N_FREQ; /* CLK_P_N Clock, please note that the value is 0hz by default, it coul… in GetSSCGPllFreq()
[all …]
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MQ5/
Dsystem_MIMX8MQ5_cm4.c76 uint32_t refClkFreq = 0U; in GetFracPllFreq() local
92 refClkFreq = CPU_XTAL_SOSC_CLK_25MHZ; in GetFracPllFreq()
97 refClkFreq = CPU_XTAL_SOSC_CLK_27MHZ; in GetFracPllFreq()
101 …refClkFreq = CLK_P_N_FREQ; /* CLK_P_N Clock, please note that the value is 0hz by default, it coul… in GetFracPllFreq()
104 refClkFreq /= (uint32_t)refDiv + 1U; in GetFracPllFreq()
105 …fracClk = (uint64_t)refClkFreq * 8U * (1U + intDiv) + (((uint64_t)refClkFreq * 8U * fracDiv) >> 24… in GetFracPllFreq()
115 uint32_t refClkFreq = 0U; in GetSSCGPllFreq() local
140 refClkFreq = CPU_XTAL_SOSC_CLK_25MHZ; in GetSSCGPllFreq()
145 refClkFreq = CPU_XTAL_SOSC_CLK_27MHZ; in GetSSCGPllFreq()
149 …refClkFreq = CLK_P_N_FREQ; /* CLK_P_N Clock, please note that the value is 0hz by default, it coul… in GetSSCGPllFreq()
[all …]
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MN4/
Dsystem_MIMX8MN4_cm7.c72 uint32_t refClkFreq = 0U; in GetFracPllFreq() local
88 refClkFreq = CPU_XTAL_SOSC_CLK_24MHZ; in GetFracPllFreq()
92 …refClkFreq = CLK_PAD_CLK; /* CLK_PAD_CLK Clock, please note that the value is 0hz by default, it c… in GetFracPllFreq()
95 fracClk = (uint64_t)refClkFreq * ((uint64_t)mainDiv * 65536UL + (uint64_t)dsm) / in GetFracPllFreq()
105 uint32_t refClkFreq = 0U; in GetIntegerPllFreq() local
121 refClkFreq = CPU_XTAL_SOSC_CLK_24MHZ; in GetIntegerPllFreq()
125 …refClkFreq = CLK_PAD_CLK; /* CLK_PAD_CLK Clock, please note that the value is 0hz by default, it c… in GetIntegerPllFreq()
131 pllOutClock = refClkFreq; in GetIntegerPllFreq()
136 pllOutClock = (uint64_t)refClkFreq * mainDiv / (((uint64_t)(1U) << postDiv) * preDiv); in GetIntegerPllFreq()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MN1/
Dsystem_MIMX8MN1_cm7.c74 uint32_t refClkFreq = 0U; in GetFracPllFreq() local
90 refClkFreq = CPU_XTAL_SOSC_CLK_24MHZ; in GetFracPllFreq()
94 …refClkFreq = CLK_PAD_CLK; /* CLK_PAD_CLK Clock, please note that the value is 0hz by default, it c… in GetFracPllFreq()
97 fracClk = (uint64_t)refClkFreq * ((uint64_t)mainDiv * 65536UL + (uint64_t)dsm) / in GetFracPllFreq()
107 uint32_t refClkFreq = 0U; in GetIntegerPllFreq() local
123 refClkFreq = CPU_XTAL_SOSC_CLK_24MHZ; in GetIntegerPllFreq()
127 …refClkFreq = CLK_PAD_CLK; /* CLK_PAD_CLK Clock, please note that the value is 0hz by default, it c… in GetIntegerPllFreq()
133 pllOutClock = refClkFreq; in GetIntegerPllFreq()
138 pllOutClock = (uint64_t)refClkFreq * mainDiv / (((uint64_t)(1U) << postDiv) * preDiv); in GetIntegerPllFreq()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MN2/
Dsystem_MIMX8MN2_cm7.c72 uint32_t refClkFreq = 0U; in GetFracPllFreq() local
88 refClkFreq = CPU_XTAL_SOSC_CLK_24MHZ; in GetFracPllFreq()
92 …refClkFreq = CLK_PAD_CLK; /* CLK_PAD_CLK Clock, please note that the value is 0hz by default, it c… in GetFracPllFreq()
95 fracClk = (uint64_t)refClkFreq * ((uint64_t)mainDiv * 65536UL + (uint64_t)dsm) / in GetFracPllFreq()
105 uint32_t refClkFreq = 0U; in GetIntegerPllFreq() local
121 refClkFreq = CPU_XTAL_SOSC_CLK_24MHZ; in GetIntegerPllFreq()
125 …refClkFreq = CLK_PAD_CLK; /* CLK_PAD_CLK Clock, please note that the value is 0hz by default, it c… in GetIntegerPllFreq()
131 pllOutClock = refClkFreq; in GetIntegerPllFreq()
136 pllOutClock = (uint64_t)refClkFreq * mainDiv / (((uint64_t)(1U) << postDiv) * preDiv); in GetIntegerPllFreq()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MN3/
Dsystem_MIMX8MN3_cm7.c74 uint32_t refClkFreq = 0U; in GetFracPllFreq() local
90 refClkFreq = CPU_XTAL_SOSC_CLK_24MHZ; in GetFracPllFreq()
94 …refClkFreq = CLK_PAD_CLK; /* CLK_PAD_CLK Clock, please note that the value is 0hz by default, it c… in GetFracPllFreq()
97 fracClk = (uint64_t)refClkFreq * ((uint64_t)mainDiv * 65536UL + (uint64_t)dsm) / in GetFracPllFreq()
107 uint32_t refClkFreq = 0U; in GetIntegerPllFreq() local
123 refClkFreq = CPU_XTAL_SOSC_CLK_24MHZ; in GetIntegerPllFreq()
127 …refClkFreq = CLK_PAD_CLK; /* CLK_PAD_CLK Clock, please note that the value is 0hz by default, it c… in GetIntegerPllFreq()
133 pllOutClock = refClkFreq; in GetIntegerPllFreq()
138 pllOutClock = (uint64_t)refClkFreq * mainDiv / (((uint64_t)(1U) << postDiv) * preDiv); in GetIntegerPllFreq()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8ML3/
Dsystem_MIMX8ML3_cm7.c79 uint32_t refClkFreq = 0U; in GetFracPllFreq() local
95 refClkFreq = CPU_XTAL_SOSC_CLK_24MHZ; in GetFracPllFreq()
99 …refClkFreq = CLK_PAD_CLK; /* CLK_PAD_CLK Clock, please note that the value is 0hz by default, it c… in GetFracPllFreq()
102 fracClk = (uint64_t)refClkFreq * ((uint64_t)mainDiv * 65536UL + (uint64_t)dsm) / in GetFracPllFreq()
112 uint32_t refClkFreq = 0U; in GetIntegerPllFreq() local
128 refClkFreq = CPU_XTAL_SOSC_CLK_24MHZ; in GetIntegerPllFreq()
132 …refClkFreq = CLK_PAD_CLK; /* CLK_PAD_CLK Clock, please note that the value is 0hz by default, it c… in GetIntegerPllFreq()
138 pllOutClock = refClkFreq; in GetIntegerPllFreq()
143 pllOutClock = (uint64_t)refClkFreq * mainDiv / (((uint64_t)(1U) << postDiv) * preDiv); in GetIntegerPllFreq()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8ML4/
Dsystem_MIMX8ML4_cm7.c79 uint32_t refClkFreq = 0U; in GetFracPllFreq() local
95 refClkFreq = CPU_XTAL_SOSC_CLK_24MHZ; in GetFracPllFreq()
99 …refClkFreq = CLK_PAD_CLK; /* CLK_PAD_CLK Clock, please note that the value is 0hz by default, it c… in GetFracPllFreq()
102 fracClk = (uint64_t)refClkFreq * ((uint64_t)mainDiv * 65536UL + (uint64_t)dsm) / in GetFracPllFreq()
112 uint32_t refClkFreq = 0U; in GetIntegerPllFreq() local
128 refClkFreq = CPU_XTAL_SOSC_CLK_24MHZ; in GetIntegerPllFreq()
132 …refClkFreq = CLK_PAD_CLK; /* CLK_PAD_CLK Clock, please note that the value is 0hz by default, it c… in GetIntegerPllFreq()
138 pllOutClock = refClkFreq; in GetIntegerPllFreq()
143 pllOutClock = (uint64_t)refClkFreq * mainDiv / (((uint64_t)(1U) << postDiv) * preDiv); in GetIntegerPllFreq()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8ML8/
Dsystem_MIMX8ML8_cm7.c79 uint32_t refClkFreq = 0U; in GetFracPllFreq() local
95 refClkFreq = CPU_XTAL_SOSC_CLK_24MHZ; in GetFracPllFreq()
99 …refClkFreq = CLK_PAD_CLK; /* CLK_PAD_CLK Clock, please note that the value is 0hz by default, it c… in GetFracPllFreq()
102 fracClk = (uint64_t)refClkFreq * ((uint64_t)mainDiv * 65536UL + (uint64_t)dsm) / in GetFracPllFreq()
112 uint32_t refClkFreq = 0U; in GetIntegerPllFreq() local
128 refClkFreq = CPU_XTAL_SOSC_CLK_24MHZ; in GetIntegerPllFreq()
132 …refClkFreq = CLK_PAD_CLK; /* CLK_PAD_CLK Clock, please note that the value is 0hz by default, it c… in GetIntegerPllFreq()
138 pllOutClock = refClkFreq; in GetIntegerPllFreq()
143 pllOutClock = (uint64_t)refClkFreq * mainDiv / (((uint64_t)(1U) << postDiv) * preDiv); in GetIntegerPllFreq()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8ML6/
Dsystem_MIMX8ML6_cm7.c79 uint32_t refClkFreq = 0U; in GetFracPllFreq() local
95 refClkFreq = CPU_XTAL_SOSC_CLK_24MHZ; in GetFracPllFreq()
99 …refClkFreq = CLK_PAD_CLK; /* CLK_PAD_CLK Clock, please note that the value is 0hz by default, it c… in GetFracPllFreq()
102 fracClk = (uint64_t)refClkFreq * ((uint64_t)mainDiv * 65536UL + (uint64_t)dsm) / in GetFracPllFreq()
112 uint32_t refClkFreq = 0U; in GetIntegerPllFreq() local
128 refClkFreq = CPU_XTAL_SOSC_CLK_24MHZ; in GetIntegerPllFreq()
132 …refClkFreq = CLK_PAD_CLK; /* CLK_PAD_CLK Clock, please note that the value is 0hz by default, it c… in GetIntegerPllFreq()
138 pllOutClock = refClkFreq; in GetIntegerPllFreq()
143 pllOutClock = (uint64_t)refClkFreq * mainDiv / (((uint64_t)(1U) << postDiv) * preDiv); in GetIntegerPllFreq()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MN5/
Dsystem_MIMX8MN5_cm7.c74 uint32_t refClkFreq = 0U; in GetFracPllFreq() local
90 refClkFreq = CPU_XTAL_SOSC_CLK_24MHZ; in GetFracPllFreq()
94 …refClkFreq = CLK_PAD_CLK; /* CLK_PAD_CLK Clock, please note that the value is 0hz by default, it c… in GetFracPllFreq()
97 fracClk = (uint64_t)refClkFreq * ((uint64_t)mainDiv * 65536UL + (uint64_t)dsm) / in GetFracPllFreq()
107 uint32_t refClkFreq = 0U; in GetIntegerPllFreq() local
123 refClkFreq = CPU_XTAL_SOSC_CLK_24MHZ; in GetIntegerPllFreq()
127 …refClkFreq = CLK_PAD_CLK; /* CLK_PAD_CLK Clock, please note that the value is 0hz by default, it c… in GetIntegerPllFreq()
133 pllOutClock = refClkFreq; in GetIntegerPllFreq()
138 pllOutClock = (uint64_t)refClkFreq * mainDiv / (((uint64_t)(1U) << postDiv) * preDiv); in GetIntegerPllFreq()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MN6/
Dsystem_MIMX8MN6_cm7.c72 uint32_t refClkFreq = 0U; in GetFracPllFreq() local
88 refClkFreq = CPU_XTAL_SOSC_CLK_24MHZ; in GetFracPllFreq()
92 …refClkFreq = CLK_PAD_CLK; /* CLK_PAD_CLK Clock, please note that the value is 0hz by default, it c… in GetFracPllFreq()
95 fracClk = (uint64_t)refClkFreq * ((uint64_t)mainDiv * 65536UL + (uint64_t)dsm) / in GetFracPllFreq()
105 uint32_t refClkFreq = 0U; in GetIntegerPllFreq() local
121 refClkFreq = CPU_XTAL_SOSC_CLK_24MHZ; in GetIntegerPllFreq()
125 …refClkFreq = CLK_PAD_CLK; /* CLK_PAD_CLK Clock, please note that the value is 0hz by default, it c… in GetIntegerPllFreq()
131 pllOutClock = refClkFreq; in GetIntegerPllFreq()
136 pllOutClock = (uint64_t)refClkFreq * mainDiv / (((uint64_t)(1U) << postDiv) * preDiv); in GetIntegerPllFreq()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MM5/
Dsystem_MIMX8MM5_cm4.c77 uint32_t refClkFreq = 0U; in GetFracPllFreq() local
93 refClkFreq = CPU_XTAL_SOSC_CLK_24MHZ; in GetFracPllFreq()
97 …refClkFreq = CLK_PAD_CLK; /* CLK_PAD_CLK Clock, please note that the value is 0hz by default, it c… in GetFracPllFreq()
100 fracClk = (uint64_t)refClkFreq * ((uint64_t)mainDiv * 65536UL + (uint64_t)dsm) / in GetFracPllFreq()
110 uint32_t refClkFreq = 0U; in GetIntegerPllFreq() local
126 refClkFreq = CPU_XTAL_SOSC_CLK_24MHZ; in GetIntegerPllFreq()
130 …refClkFreq = CLK_PAD_CLK; /* CLK_PAD_CLK Clock, please note that the value is 0hz by default, it c… in GetIntegerPllFreq()
136 pllOutClock = refClkFreq; in GetIntegerPllFreq()
141 pllOutClock = (uint64_t)refClkFreq * mainDiv / (((uint64_t)(1U) << postDiv) * preDiv); in GetIntegerPllFreq()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MM6/
Dsystem_MIMX8MM6_cm4.c77 uint32_t refClkFreq = 0U; in GetFracPllFreq() local
93 refClkFreq = CPU_XTAL_SOSC_CLK_24MHZ; in GetFracPllFreq()
97 …refClkFreq = CLK_PAD_CLK; /* CLK_PAD_CLK Clock, please note that the value is 0hz by default, it c… in GetFracPllFreq()
100 fracClk = (uint64_t)refClkFreq * ((uint64_t)mainDiv * 65536UL + (uint64_t)dsm) / in GetFracPllFreq()
110 uint32_t refClkFreq = 0U; in GetIntegerPllFreq() local
126 refClkFreq = CPU_XTAL_SOSC_CLK_24MHZ; in GetIntegerPllFreq()
130 …refClkFreq = CLK_PAD_CLK; /* CLK_PAD_CLK Clock, please note that the value is 0hz by default, it c… in GetIntegerPllFreq()
136 pllOutClock = refClkFreq; in GetIntegerPllFreq()
141 pllOutClock = (uint64_t)refClkFreq * mainDiv / (((uint64_t)(1U) << postDiv) * preDiv); in GetIntegerPllFreq()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MM1/
Dsystem_MIMX8MM1_cm4.c77 uint32_t refClkFreq = 0U; in GetFracPllFreq() local
93 refClkFreq = CPU_XTAL_SOSC_CLK_24MHZ; in GetFracPllFreq()
97 …refClkFreq = CLK_PAD_CLK; /* CLK_PAD_CLK Clock, please note that the value is 0hz by default, it c… in GetFracPllFreq()
100 fracClk = (uint64_t)refClkFreq * ((uint64_t)mainDiv * 65536UL + (uint64_t)dsm) / in GetFracPllFreq()
110 uint32_t refClkFreq = 0U; in GetIntegerPllFreq() local
126 refClkFreq = CPU_XTAL_SOSC_CLK_24MHZ; in GetIntegerPllFreq()
130 …refClkFreq = CLK_PAD_CLK; /* CLK_PAD_CLK Clock, please note that the value is 0hz by default, it c… in GetIntegerPllFreq()
136 pllOutClock = refClkFreq; in GetIntegerPllFreq()
141 pllOutClock = (uint64_t)refClkFreq * mainDiv / (((uint64_t)(1U) << postDiv) * preDiv); in GetIntegerPllFreq()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MM3/
Dsystem_MIMX8MM3_cm4.c77 uint32_t refClkFreq = 0U; in GetFracPllFreq() local
93 refClkFreq = CPU_XTAL_SOSC_CLK_24MHZ; in GetFracPllFreq()
97 …refClkFreq = CLK_PAD_CLK; /* CLK_PAD_CLK Clock, please note that the value is 0hz by default, it c… in GetFracPllFreq()
100 fracClk = (uint64_t)refClkFreq * ((uint64_t)mainDiv * 65536UL + (uint64_t)dsm) / in GetFracPllFreq()
110 uint32_t refClkFreq = 0U; in GetIntegerPllFreq() local
126 refClkFreq = CPU_XTAL_SOSC_CLK_24MHZ; in GetIntegerPllFreq()
130 …refClkFreq = CLK_PAD_CLK; /* CLK_PAD_CLK Clock, please note that the value is 0hz by default, it c… in GetIntegerPllFreq()
136 pllOutClock = refClkFreq; in GetIntegerPllFreq()
141 pllOutClock = (uint64_t)refClkFreq * mainDiv / (((uint64_t)(1U) << postDiv) * preDiv); in GetIntegerPllFreq()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MM2/
Dsystem_MIMX8MM2_cm4.c77 uint32_t refClkFreq = 0U; in GetFracPllFreq() local
93 refClkFreq = CPU_XTAL_SOSC_CLK_24MHZ; in GetFracPllFreq()
97 …refClkFreq = CLK_PAD_CLK; /* CLK_PAD_CLK Clock, please note that the value is 0hz by default, it c… in GetFracPllFreq()
100 fracClk = (uint64_t)refClkFreq * ((uint64_t)mainDiv * 65536UL + (uint64_t)dsm) / in GetFracPllFreq()
110 uint32_t refClkFreq = 0U; in GetIntegerPllFreq() local
126 refClkFreq = CPU_XTAL_SOSC_CLK_24MHZ; in GetIntegerPllFreq()
130 …refClkFreq = CLK_PAD_CLK; /* CLK_PAD_CLK Clock, please note that the value is 0hz by default, it c… in GetIntegerPllFreq()
136 pllOutClock = refClkFreq; in GetIntegerPllFreq()
141 pllOutClock = (uint64_t)refClkFreq * mainDiv / (((uint64_t)(1U) << postDiv) * preDiv); in GetIntegerPllFreq()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MM4/
Dsystem_MIMX8MM4_cm4.c77 uint32_t refClkFreq = 0U; in GetFracPllFreq() local
93 refClkFreq = CPU_XTAL_SOSC_CLK_24MHZ; in GetFracPllFreq()
97 …refClkFreq = CLK_PAD_CLK; /* CLK_PAD_CLK Clock, please note that the value is 0hz by default, it c… in GetFracPllFreq()
100 fracClk = (uint64_t)refClkFreq * ((uint64_t)mainDiv * 65536UL + (uint64_t)dsm) / in GetFracPllFreq()
110 uint32_t refClkFreq = 0U; in GetIntegerPllFreq() local
126 refClkFreq = CPU_XTAL_SOSC_CLK_24MHZ; in GetIntegerPllFreq()
130 …refClkFreq = CLK_PAD_CLK; /* CLK_PAD_CLK Clock, please note that the value is 0hz by default, it c… in GetIntegerPllFreq()
136 pllOutClock = refClkFreq; in GetIntegerPllFreq()
141 pllOutClock = (uint64_t)refClkFreq * mainDiv / (((uint64_t)(1U) << postDiv) * preDiv); in GetIntegerPllFreq()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MD6/drivers/
Dfsl_clock.c329 uint32_t refClkFreq = 0U; in CLOCK_GetPllRefClkFreq() local
346 refClkFreq = OSC25M_CLK_FREQ / in CLOCK_GetPllRefClkFreq()
353 refClkFreq = OSC27M_CLK_FREQ / in CLOCK_GetPllRefClkFreq()
360 refClkFreq = HDMI_PHY_27M_FREQ; in CLOCK_GetPllRefClkFreq()
364 refClkFreq = CLKPN_FREQ; in CLOCK_GetPllRefClkFreq()
367 refClkFreq = 0U; in CLOCK_GetPllRefClkFreq()
371 return refClkFreq; in CLOCK_GetPllRefClkFreq()
828 uint32_t CLOCK_GetFracPllFreq(CCM_ANALOG_Type *base, clock_pll_ctrl_t type, uint32_t refClkFreq) in CLOCK_GetFracPllFreq() argument
845 refClkFreq /= (uint32_t)refDiv + 1UL; in CLOCK_GetFracPllFreq()
846 …fracClk = (uint64_t)refClkFreq * 8U * (1U + intDiv) + (((uint64_t)refClkFreq * 8U * fracDiv) >> 24… in CLOCK_GetFracPllFreq()
[all …]
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MD7/drivers/
Dfsl_clock.c329 uint32_t refClkFreq = 0U; in CLOCK_GetPllRefClkFreq() local
346 refClkFreq = OSC25M_CLK_FREQ / in CLOCK_GetPllRefClkFreq()
353 refClkFreq = OSC27M_CLK_FREQ / in CLOCK_GetPllRefClkFreq()
360 refClkFreq = HDMI_PHY_27M_FREQ; in CLOCK_GetPllRefClkFreq()
364 refClkFreq = CLKPN_FREQ; in CLOCK_GetPllRefClkFreq()
367 refClkFreq = 0U; in CLOCK_GetPllRefClkFreq()
371 return refClkFreq; in CLOCK_GetPllRefClkFreq()
828 uint32_t CLOCK_GetFracPllFreq(CCM_ANALOG_Type *base, clock_pll_ctrl_t type, uint32_t refClkFreq) in CLOCK_GetFracPllFreq() argument
845 refClkFreq /= (uint32_t)refDiv + 1UL; in CLOCK_GetFracPllFreq()
846 …fracClk = (uint64_t)refClkFreq * 8U * (1U + intDiv) + (((uint64_t)refClkFreq * 8U * fracDiv) >> 24… in CLOCK_GetFracPllFreq()
[all …]
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MQ5/drivers/
Dfsl_clock.c329 uint32_t refClkFreq = 0U; in CLOCK_GetPllRefClkFreq() local
346 refClkFreq = OSC25M_CLK_FREQ / in CLOCK_GetPllRefClkFreq()
353 refClkFreq = OSC27M_CLK_FREQ / in CLOCK_GetPllRefClkFreq()
360 refClkFreq = HDMI_PHY_27M_FREQ; in CLOCK_GetPllRefClkFreq()
364 refClkFreq = CLKPN_FREQ; in CLOCK_GetPllRefClkFreq()
367 refClkFreq = 0U; in CLOCK_GetPllRefClkFreq()
371 return refClkFreq; in CLOCK_GetPllRefClkFreq()
828 uint32_t CLOCK_GetFracPllFreq(CCM_ANALOG_Type *base, clock_pll_ctrl_t type, uint32_t refClkFreq) in CLOCK_GetFracPllFreq() argument
845 refClkFreq /= (uint32_t)refDiv + 1UL; in CLOCK_GetFracPllFreq()
846 …fracClk = (uint64_t)refClkFreq * 8U * (1U + intDiv) + (((uint64_t)refClkFreq * 8U * fracDiv) >> 24… in CLOCK_GetFracPllFreq()
[all …]
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MQ6/drivers/
Dfsl_clock.c329 uint32_t refClkFreq = 0U; in CLOCK_GetPllRefClkFreq() local
346 refClkFreq = OSC25M_CLK_FREQ / in CLOCK_GetPllRefClkFreq()
353 refClkFreq = OSC27M_CLK_FREQ / in CLOCK_GetPllRefClkFreq()
360 refClkFreq = HDMI_PHY_27M_FREQ; in CLOCK_GetPllRefClkFreq()
364 refClkFreq = CLKPN_FREQ; in CLOCK_GetPllRefClkFreq()
367 refClkFreq = 0U; in CLOCK_GetPllRefClkFreq()
371 return refClkFreq; in CLOCK_GetPllRefClkFreq()
828 uint32_t CLOCK_GetFracPllFreq(CCM_ANALOG_Type *base, clock_pll_ctrl_t type, uint32_t refClkFreq) in CLOCK_GetFracPllFreq() argument
845 refClkFreq /= (uint32_t)refDiv + 1UL; in CLOCK_GetFracPllFreq()
846 …fracClk = (uint64_t)refClkFreq * 8U * (1U + intDiv) + (((uint64_t)refClkFreq * 8U * fracDiv) >> 24… in CLOCK_GetFracPllFreq()
[all …]

123