1 /*! 2 * Copyright (c) 2015, Freescale Semiconductor, Inc. 3 * All rights reserved. 4 * 5 * \file overwrites.h 6 * 7 * Redistribution and use in source and binary forms, with or without modification, 8 * are permitted provided that the following conditions are met: 9 * 10 * o Redistributions of source code must retain the above copyright notice, this list 11 * of conditions and the following disclaimer. 12 * 13 * o Redistributions in binary form must reproduce the above copyright notice, this 14 * list of conditions and the following disclaimer in the documentation and/or 15 * other materials provided with the distribution. 16 * 17 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its 18 * contributors may be used to endorse or promote products derived from this 19 * software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR 25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /*! ********************************************************************************* 34 ************************************************************************************* 35 * Use: This file is created exclusively for use with MKW40Z4 1.0 silicon 36 * and is provided for the world to use. It contains a list of all 37 * known overwrite values. Overwrite values are non-default register 38 * values that configure the MKW40Z4 device to a more optimally performing 39 * posture. It is expected that low level software (i.e. PHY) will 40 * consume this file as a #include, and transfer the contents to the 41 * the indicated addresses in the MKW40Z4 memory space. This file has 42 * at least one required entry, that being its own version current version 43 * number, to be stored at MKW40Z4 location 0x290 the 44 * OVERWRITES_VER register. The RAM register is provided in 45 * the MKW40Z4 address space to assist in future debug efforts. The 46 * analyst may read this location (once device has been booted with 47 * mysterious software) and have a good indication of what register 48 * overwrites were performed (with all versions of the overwrites.h file 49 * being archived forever at the Compass location shown above. 50 * 51 ************************************************************************************* 52 ********************************************************************************** */ 53 54 #ifndef OVERWRITES_H_ 55 #define OVERWRITES_H_ 56 57 /*! ********************************************************************************* 58 ************************************************************************************* 59 * Public type definitions 60 ************************************************************************************* 61 ********************************************************************************** */ 62 typedef struct overwrites_tag 63 { 64 unsigned int address; 65 unsigned int data; 66 }overwrites_t; 67 68 /* The following definition of overwrites are specific to radio trim values coming from IFR. */ 69 typedef struct 70 { 71 uint8_t src_address; /* Address of desired data in IFR */ 72 uint8_t src_bp; /* Bit position of desired trim values in IFR */ 73 uint8_t field_size; /* Number of bits of data */ 74 uint32_t dest_address; /* Address to place IFR data to. */ 75 uint8_t dest_shift; /* Number of shift to be shifted in the destination */ 76 uint8_t reg_access; /* How the destination reg to be accessed (i.e. 8, 16, 32 bit) */ 77 } overwrites_ifr; 78 79 /*! ********************************************************************************* 80 ************************************************************************************* 81 * Public memory declarations 82 ************************************************************************************* 83 ********************************************************************************** */ 84 /* These are the recommended overwrites regardless of BLE vs. 802.15.4 posture */ 85 overwrites_t const overwrites_common[] = 86 { 87 {0x4005C000,0x0}, /* RX_DIG_CTRL */ 88 {0x4005C004,0x0}, /* AGC_CTRL_0 */ 89 {0x4005C008,0x0}, /* AGC_CTRL_1 */ 90 {0x4005C00C,0x0}, /* AGC_CTRL_2 */ 91 {0x4005C010,0x0}, /* AGC_CTRL_3 */ 92 {0x4005C018,0x0}, /* RSSI_CTRL_0 */ 93 {0x4005C01C,0x0}, /* RSSI_CTRL_1 */ 94 {0x4005C020,0x0}, /* DCOC_CTRL_0 */ 95 {0x4005C024,0x0}, /* DCOC_CTRL_1 */ 96 {0x4005C028,0x0}, /* DCOC_CTRL_2 */ 97 {0x4005C02C,0x0}, /* DCOC_CTRL_3 */ 98 {0x4005C030,0x0}, /* DCOC_CTRL_4 */ 99 {0x4005C034,0x0}, /* DCOC_CAL_GAIN */ 100 {0x4005C040,0x0}, /* DCOC_CAL_RCP */ 101 {0x4005C04C,0x8000}, /* IQMC_CTRL */ 102 {0x4005C050,0x400}, /* IQMC_CAL */ 103 {0x4005C054,0x3C242C14}, /* TCA_AGC_VAL_3_0 */ 104 {0x4005C058,0x9C846C54}, /* TCA_AGC_VAL_7_4 */ 105 {0x4005C05C,0xB4}, /* TCA_AGC_VAL_8 */ 106 {0x4005C060,0x0}, /* BBF_RES_TUNE_VAL_7_0 */ 107 {0x4005C064,0x0}, /* BBF_RES_TUNE_VAL_10_8 */ 108 {0x4005C068,0x0}, /* TCA_AGC_LIN_VAL_2_0 */ 109 {0x4005C06C,0x0}, /* TCA_AGC_LIN_VAL_5_3 */ 110 {0x4005C070,0x0}, /* TCA_AGC_LIN_VAL_8_6 */ 111 {0x4005C074,0x0}, /* BBF_RES_TUNE_LIN_VAL_3_0 */ 112 {0x4005C078,0x0}, /* BBF_RES_TUNE_LIN_VAL_7_4 */ 113 {0x4005C07C,0x0}, /* BBF_RES_TUNE_LIN_VAL_10_8 */ 114 {0x4005C080,0x0}, /* AGC_GAIN_TBL_03_00 */ 115 {0x4005C084,0x0}, /* AGC_GAIN_TBL_07_04 */ 116 {0x4005C088,0x0}, /* AGC_GAIN_TBL_11_08 */ 117 {0x4005C08C,0x0}, /* AGC_GAIN_TBL_15_12 */ 118 {0x4005C090,0x0}, /* AGC_GAIN_TBL_19_16 */ 119 {0x4005C094,0x0}, /* AGC_GAIN_TBL_23_20 */ 120 {0x4005C098,0x0}, /* AGC_GAIN_TBL_26_24 */ 121 {0x4005C0A0,0x0}, /* DCOC_OFFSET_0 */ 122 {0x4005C0A4,0x0}, /* DCOC_OFFSET_1 */ 123 {0x4005C0A8,0x0}, /* DCOC_OFFSET_2 */ 124 {0x4005C0AC,0x0}, /* DCOC_OFFSET_3 */ 125 {0x4005C0B0,0x0}, /* DCOC_OFFSET_4 */ 126 {0x4005C0B4,0x0}, /* DCOC_OFFSET_5 */ 127 {0x4005C0B8,0x0}, /* DCOC_OFFSET_6 */ 128 {0x4005C0BC,0x0}, /* DCOC_OFFSET_7 */ 129 {0x4005C0C0,0x0}, /* DCOC_OFFSET_8 */ 130 {0x4005C0C4,0x0}, /* DCOC_OFFSET_9 */ 131 {0x4005C0C8,0x0}, /* DCOC_OFFSET_10 */ 132 {0x4005C0CC,0x0}, /* DCOC_OFFSET_11 */ 133 {0x4005C0D0,0x0}, /* DCOC_OFFSET_12 */ 134 {0x4005C0D4,0x0}, /* DCOC_OFFSET_13 */ 135 {0x4005C0D8,0x0}, /* DCOC_OFFSET_14 */ 136 {0x4005C0DC,0x0}, /* DCOC_OFFSET_15 */ 137 {0x4005C0E0,0x0}, /* DCOC_OFFSET_16 */ 138 {0x4005C0E4,0x0}, /* DCOC_OFFSET_17 */ 139 {0x4005C0E8,0x0}, /* DCOC_OFFSET_18 */ 140 {0x4005C0EC,0x0}, /* DCOC_OFFSET_19 */ 141 {0x4005C0F0,0x0}, /* DCOC_OFFSET_20 */ 142 {0x4005C0F4,0x0}, /* DCOC_OFFSET_21 */ 143 {0x4005C0F8,0x0}, /* DCOC_OFFSET_22 */ 144 {0x4005C0FC,0x0}, /* DCOC_OFFSET_23 */ 145 {0x4005C100,0x0}, /* DCOC_OFFSET_24 */ 146 {0x4005C104,0x0}, /* DCOC_OFFSET_25 */ 147 {0x4005C108,0x0}, /* DCOC_OFFSET_26 */ 148 {0x4005C110,0x0}, /* DCOC_TZA_STEP_0 */ 149 {0x4005C114,0x0}, /* DCOC_TZA_STEP_1 */ 150 {0x4005C118,0x0}, /* DCOC_TZA_STEP_2 */ 151 {0x4005C11C,0x0}, /* DCOC_TZA_STEP_3 */ 152 {0x4005C120,0x0}, /* DCOC_TZA_STEP_4 */ 153 {0x4005C124,0x0}, /* DCOC_TZA_STEP_5 */ 154 {0x4005C128,0x0}, /* DCOC_TZA_STEP_6 */ 155 {0x4005C12C,0x0}, /* DCOC_TZA_STEP_7 */ 156 {0x4005C130,0x0}, /* DCOC_TZA_STEP_8 */ 157 {0x4005C134,0x0}, /* DCOC_TZA_STEP_9 */ 158 {0x4005C138,0x0}, /* DCOC_TZA_STEP_10 */ 159 {0x4005C178,0x0}, /* DCOC_CAL_IIR */ 160 {0x4005C1A0,0x0}, /* RX_CHF_COEF0 */ 161 {0x4005C1A4,0x0}, /* RX_CHF_COEF1 */ 162 {0x4005C1A8,0x0}, /* RX_CHF_COEF2 */ 163 {0x4005C1AC,0x0}, /* RX_CHF_COEF3 */ 164 {0x4005C1B0,0x0}, /* RX_CHF_COEF4 */ 165 {0x4005C1B4,0x0}, /* RX_CHF_COEF5 */ 166 {0x4005C1B8,0x0}, /* RX_CHF_COEF6 */ 167 {0x4005C1BC,0x0}, /* RX_CHF_COEF7 */ 168 {0x4005C200,0x140}, /* TX_DIG_CTRL */ 169 {0x4005C204,0x7FFF55AA}, /* TX_DATA_PAD_PAT */ 170 {0x4005C208,0x3014000}, /* TX_GFSK_MOD_CTRL */ 171 {0x4005C20C,0xC0630401}, /* TX_GFSK_COEFF2 */ 172 {0x4005C210,0xBB29960D}, /* TX_GFSK_COEFF1 */ 173 {0x4005C214,0x7FF1800}, /* TX_FSK_MOD_SCALE */ 174 {0x4005C218,0x0}, /* TX_DFT_MOD_PAT */ 175 {0x4005C21C,0x10000FFF}, /* TX_DFT_TONE_0_1 */ 176 {0x4005C220,0x1E0001FF}, /* TX_DFT_TONE_2_3 */ 177 {0x4005C228,0x0}, /* PLL_MOD_OVRD */ 178 {0x4005C22C,0x200}, /* PLL_CHAN_MAP */ 179 {0x4005C230,0x202600}, /* PLL_LOCK_DETECT */ 180 {0x4005C234,0x840000}, /* PLL_HP_MOD_CTRL */ 181 {0x4005C244,0x1FF0000}, /* PLL_HPM_SDM_FRACTION */ 182 {0x4005C248,0x8080000}, /* PLL_LP_MOD_CTRL */ 183 {0x4005C24C,0x260026}, /* PLL_LP_SDM_CTRL1 */ 184 {0x4005C250,0x2000000}, /* PLL_LP_SDM_CTRL2 */ 185 {0x4005C254,0x4000000}, /* PLL_LP_SDM_CTRL3 */ 186 {0x4005C260,0x201}, /* PLL_DELAY_MATCH */ 187 {0x4005C288,0x0}, /* SOFT_RESET */ 188 {0x4005C290,0x0}, /* OVERWRITE_VER */ 189 {0x4005C294,0x0}, /* DMA_CTRL */ 190 {0x4005C29C,0x0}, /* DTEST_CTRL */ 191 {0x4005C2A0,0x0}, /* PB_CTRL */ 192 {0x4005C2C0,0xFF000000}, /* TSM_CTRL */ 193 {0x4005C2C4,0x65646A67}, /* END_OF_SEQ */ 194 {0x4005C2C8,0x0}, /* TSM_OVRD0 */ 195 {0x4005C2CC,0x0}, /* TSM_OVRD1 */ 196 {0x4005C2D0,0x0}, /* TSM_OVRD2 */ 197 {0x4005C2D4,0x0}, /* TSM_OVRD3 */ 198 {0x4005C2D8,0x0}, /* PA_POWER */ 199 {0x4005C2DC,0x0}, /* PA_BIAS_TBL0 */ 200 {0x4005C2E0,0x0}, /* PA_BIAS_TBL1 */ 201 {0x4005C2E4,0x826}, /* RECYCLE_COUNT */ 202 {0x4005C2E8,0x65006A00}, /* TSM_TIMING00 */ 203 {0x4005C2EC,0x65006A00}, /* TSM_TIMING01 */ 204 {0x4005C2F0,0x65006A00}, /* TSM_TIMING02 */ 205 {0x4005C2F4,0x65006A00}, /* TSM_TIMING03 */ 206 {0x4005C2F8,0x6500FFFF}, /* TSM_TIMING04 */ 207 {0x4005C2FC,0x650B6A3F}, /* TSM_TIMING05 */ 208 {0x4005C300,0x651AFFFF}, /* TSM_TIMING06 */ 209 {0x4005C304,0x1A004E00}, /* TSM_TIMING07 */ 210 {0x4005C308,0x65336867}, /* TSM_TIMING08 */ 211 {0x4005C30C,0x65056A05}, /* TSM_TIMING09 */ 212 {0x4005C310,0x6509FFFF}, /* TSM_TIMING10 */ 213 {0x4005C314,0xFFFF6A09}, /* TSM_TIMING11 */ 214 {0x4005C318,0xFFFF6A64}, /* TSM_TIMING12 */ 215 {0x4005C31C,0x651A6A4E}, /* TSM_TIMING13 */ 216 {0x4005C320,0x650AFFFF}, /* TSM_TIMING14 */ 217 {0x4005C324,0xFFFF6A0A}, /* TSM_TIMING15 */ 218 {0x4005C328,0x1A104E44}, /* TSM_TIMING16 */ 219 {0x4005C32C,0x65106A44}, /* TSM_TIMING17 */ 220 {0x4005C330,0x6505FFFF}, /* TSM_TIMING18 */ 221 {0x4005C334,0xFFFF6864}, /* TSM_TIMING19 */ 222 {0x4005C338,0x651AFFFF}, /* TSM_TIMING20 */ 223 {0x4005C33C,0x651AFFFF}, /* TSM_TIMING21 */ 224 {0x4005C340,0x651AFFFF}, /* TSM_TIMING22 */ 225 {0x4005C344,0x651AFFFF}, /* TSM_TIMING23 */ 226 {0x4005C348,0x6518FFFF}, /* TSM_TIMING24 */ 227 {0x4005C34C,0x6518FFFF}, /* TSM_TIMING25 */ 228 {0x4005C350,0x65096A09}, /* TSM_TIMING26 */ 229 {0x4005C354,0xFFFF6A67}, /* TSM_TIMING27 */ 230 {0x4005C358,0x6562FFFF}, /* TSM_TIMING28 */ 231 {0x4005C35C,0x6362FFFF}, /* TSM_TIMING29 */ 232 {0x4005C360,0x65106A44}, /* TSM_TIMING30 */ 233 {0x4005C364,0x6562FFFF}, /* TSM_TIMING31 */ 234 {0x4005C368,0x6526FFFF}, /* TSM_TIMING32 */ 235 {0x4005C36C,0x2726FFFF}, /* TSM_TIMING33 */ 236 {0x4005C370,0x65336865}, /* TSM_TIMING34 */ 237 {0x4005C374,0xFFFFFFFF}, /* TSM_TIMING35 */ 238 {0x4005C378,0xFFFFFFFF}, /* TSM_TIMING36 */ 239 {0x4005C37C,0xFFFFFFFF}, /* TSM_TIMING37 */ 240 {0x4005C380,0xFFFFFFFF}, /* TSM_TIMING38 */ 241 {0x4005C384,0xFFFFFFFF}, /* TSM_TIMING39 */ 242 {0x4005C388,0xFFFFFFFF}, /* TSM_TIMING40 */ 243 {0x4005C38C,0xFFFFFFFF}, /* TSM_TIMING41 */ 244 {0x4005C390,0xFFFFFFFF}, /* TSM_TIMING42 */ 245 {0x4005C394,0xFFFFFFFF}, /* TSM_TIMING43 */ 246 {0x4005C3C0,0x482}, /* CORR_CTRL */ 247 {0x4005C3C4,0x1}, /* PN_TYPE */ 248 {0x4005C3C8,0x744AC39B}, /* PN_CODE */ 249 {0x4005C3CC,0x8}, /* SYNC_CTRL */ 250 {0x4005C3D0,0x0}, /* SNF_THR */ 251 {0x4005C3D4,0x82}, /* FAD_THR */ 252 {0x4005C3D8,0x1}, /* ZBDEM_AFC */ 253 {0x4005C3DC,0x0}, /* LPPS_CTRL */ 254 {0x4005C400,0xFFFF0001}, /* ADC_CTRL */ 255 {0x4005C404,0x880033}, /* ADC_TUNE */ 256 {0x4005C408,0x43033033}, /* ADC_ADJ */ 257 {0x4005C40C,0x0}, /* ADC_REGS */ 258 {0x4005C410,0x444}, /* ADC_TRIMS */ 259 {0x4005C414,0x0}, /* ADC_TEST_CTRL */ 260 {0x4005C420,0x173}, /* BBF_CTRL */ 261 {0x4005C42C,0x0}, /* RX_ANA_CTRL */ 262 {0x4005C434,0xACAC177}, /* XTAL_CTRL */ 263 {0x4005C438,0x1000}, /* XTAL_CTRL2 */ 264 {0x4005C43C,0x87}, /* BGAP_CTRL */ 265 {0x4005C444,0x24}, /* PLL_CTRL */ 266 {0x4005C448,0x24}, /* PLL_CTRL2 */ 267 {0x4005C44C,0x0}, /* PLL_TEST_CTRL */ 268 {0x4005C458,0x0}, /* QGEN_CTRL */ 269 {0x4005C464,0x0}, /* TCA_CTRL */ 270 {0x4005C468,0x44}, /* TZA_CTRL */ 271 {0x4005C474,0x0}, /* TX_ANA_CTRL */ 272 {0x4005C47C,0x0}, /* ANA_SPARE */ 273 }; 274 275 /* These are the recommended overwrites that are specific to the 802.15.4 radio posture */ 276 overwrites_t const overwrites_802p15p4[] = 277 { 278 /* Default Values */ 279 {0x4005C000,0x220}, /* RX_DIG_CTRL */ 280 {0x4005C1A0,0x0}, /* RX_CHF_COEF0 */ 281 {0x4005C1A4,0x0}, /* RX_CHF_COEF1 */ 282 {0x4005C1A8,0xFF}, /* RX_CHF_COEF2 */ 283 {0x4005C1AC,0x05}, /* RX_CHF_COEF3 */ 284 {0x4005C1B0,0xFF}, /* RX_CHF_COEF4 */ 285 {0x4005C1B4,0xEB}, /* RX_CHF_COEF5 */ 286 {0x4005C1B8,0x06}, /* RX_CHF_COEF6 */ 287 {0x4005C1BC,0x4C}, /* RX_CHF_COEF7 */ 288 }; 289 290 /* These are the recommended overwrites that are specific to BLE */ 291 overwrites_t const overwrites_ble[] = 292 { 293 /* Default Values */ 294 {0x4005C000,0x110}, /* RX_DIG_CTRL */ 295 {0x4005C1A0,0x0}, /* RX_CHF_COEF0 */ 296 {0x4005C1A4,0xFF}, /* RX_CHF_COEF1 */ 297 {0x4005C1A8,0xFD}, /* RX_CHF_COEF2 */ 298 {0x4005C1AC,0xFB}, /* RX_CHF_COEF3 */ 299 {0x4005C1B0,0xFE}, /* RX_CHF_COEF4 */ 300 {0x4005C1B4,0x0A}, /* RX_CHF_COEF5 */ 301 {0x4005C1B8,0x1B}, /* RX_CHF_COEF6 */ 302 {0x4005C1BC,0x27}, /* RX_CHF_COEF7 */ 303 }; 304 305 /* These are the overwrites values from IFR to be placed in Radio Address Space */ 306 const overwrites_ifr radio_trim_ifr[] = 307 { 308 {0x84,12,4,0x4005C468,0,2}, /* TZA_CTRL[TZA_CAP_TUNE] */ 309 {0x84,8,4,0x4005C420,0,2}, /* BBF_CTRL[BBF_CAP_TUNE] */ 310 {0x84,4,4,0x4005C420,4,2}, /* BBF_CTRL[BBF_RES_TUNE2] */ 311 {0x98,20,11,0x4005C050,0,2}, /* IQMC_CAL[IQMC_GAIN_ADJ] */ 312 {0x98,8,12,0x4005C050,16,2}, /* IQMC_CAL[IQMC_PHASE_ADJ] */ 313 {0x9C,28,4,0x4005C43C,4,2}, /* BGAP_CTRL[BGAP_VOLTAGE] */ 314 {0x9C,24,4,0x4005C43C,0,2}, /* BGAP_CTRL[BGAP_CURRENT] */ 315 {0x9C,20,4,0x4005C438,0,2}, /* XTAL_CTRL2[XTAL_REG_SUPPLY] */ 316 {0x9C,16,4,0x4005C444,8,2}, /* PLL_CTRL[PLL_REG_SUPPLY] */ 317 {0x9C,12,4,0x4005C458,0,2}, /* QGEN_CTRL[QGEN_REG_SUPPLY] */ 318 {0x9C,8,4,0x4005C464,4,2}, /* TCA_CTRL[TCA_TX_REG_SUPPLY] */ 319 {0x9C,4,4,0x4005C48C,4,2}, /* ADC_REGS[ADC_REG_DIG_SUPPLY] */ 320 {0x9C,0,4,0x4005C48C,0,2}, /* ADC_REGS[ADC_ANA_REG_SUPPLY] */ 321 }; 322 323 #endif /* OVERWRITES_H_ */
