1 /*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016-2017 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8 #ifndef _FSL_LPTMR_H_
9 #define _FSL_LPTMR_H_
10
11 #include "fsl_common.h"
12
13 /*!
14 * @addtogroup lptmr
15 * @{
16 */
17
18 /*******************************************************************************
19 * Definitions
20 ******************************************************************************/
21
22 /*! @name Driver version */
23 /*@{*/
24 #define FSL_LPTMR_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) /*!< Version 2.1.1 */
25 /*@}*/
26
27 /*! @brief LPTMR pin selection used in pulse counter mode.*/
28 typedef enum _lptmr_pin_select
29 {
30 kLPTMR_PinSelectInput_0 = 0x0U, /*!< Pulse counter input 0 is selected */
31 kLPTMR_PinSelectInput_1 = 0x1U, /*!< Pulse counter input 1 is selected */
32 kLPTMR_PinSelectInput_2 = 0x2U, /*!< Pulse counter input 2 is selected */
33 kLPTMR_PinSelectInput_3 = 0x3U /*!< Pulse counter input 3 is selected */
34 } lptmr_pin_select_t;
35
36 /*! @brief LPTMR pin polarity used in pulse counter mode.*/
37 typedef enum _lptmr_pin_polarity
38 {
39 kLPTMR_PinPolarityActiveHigh = 0x0U, /*!< Pulse Counter input source is active-high */
40 kLPTMR_PinPolarityActiveLow = 0x1U /*!< Pulse Counter input source is active-low */
41 } lptmr_pin_polarity_t;
42
43 /*! @brief LPTMR timer mode selection.*/
44 typedef enum _lptmr_timer_mode
45 {
46 kLPTMR_TimerModeTimeCounter = 0x0U, /*!< Time Counter mode */
47 kLPTMR_TimerModePulseCounter = 0x1U /*!< Pulse Counter mode */
48 } lptmr_timer_mode_t;
49
50 /*! @brief LPTMR prescaler/glitch filter values*/
51 typedef enum _lptmr_prescaler_glitch_value
52 {
53 kLPTMR_Prescale_Glitch_0 = 0x0U, /*!< Prescaler divide 2, glitch filter does not support this setting */
54 kLPTMR_Prescale_Glitch_1 = 0x1U, /*!< Prescaler divide 4, glitch filter 2 */
55 kLPTMR_Prescale_Glitch_2 = 0x2U, /*!< Prescaler divide 8, glitch filter 4 */
56 kLPTMR_Prescale_Glitch_3 = 0x3U, /*!< Prescaler divide 16, glitch filter 8 */
57 kLPTMR_Prescale_Glitch_4 = 0x4U, /*!< Prescaler divide 32, glitch filter 16 */
58 kLPTMR_Prescale_Glitch_5 = 0x5U, /*!< Prescaler divide 64, glitch filter 32 */
59 kLPTMR_Prescale_Glitch_6 = 0x6U, /*!< Prescaler divide 128, glitch filter 64 */
60 kLPTMR_Prescale_Glitch_7 = 0x7U, /*!< Prescaler divide 256, glitch filter 128 */
61 kLPTMR_Prescale_Glitch_8 = 0x8U, /*!< Prescaler divide 512, glitch filter 256 */
62 kLPTMR_Prescale_Glitch_9 = 0x9U, /*!< Prescaler divide 1024, glitch filter 512*/
63 kLPTMR_Prescale_Glitch_10 = 0xAU, /*!< Prescaler divide 2048 glitch filter 1024 */
64 kLPTMR_Prescale_Glitch_11 = 0xBU, /*!< Prescaler divide 4096, glitch filter 2048 */
65 kLPTMR_Prescale_Glitch_12 = 0xCU, /*!< Prescaler divide 8192, glitch filter 4096 */
66 kLPTMR_Prescale_Glitch_13 = 0xDU, /*!< Prescaler divide 16384, glitch filter 8192 */
67 kLPTMR_Prescale_Glitch_14 = 0xEU, /*!< Prescaler divide 32768, glitch filter 16384 */
68 kLPTMR_Prescale_Glitch_15 = 0xFU /*!< Prescaler divide 65536, glitch filter 32768 */
69 } lptmr_prescaler_glitch_value_t;
70
71 /*!
72 * @brief LPTMR prescaler/glitch filter clock select.
73 * @note Clock connections are SoC-specific
74 */
75 typedef enum _lptmr_prescaler_clock_select
76 {
77 kLPTMR_PrescalerClock_0 = 0x0U, /*!< Prescaler/glitch filter clock 0 selected. */
78 #if !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT) && \
79 FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT)
80 kLPTMR_PrescalerClock_1 = 0x1U, /*!< Prescaler/glitch filter clock 1 selected. */
81 #endif /* FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT */
82 kLPTMR_PrescalerClock_2 = 0x2U, /*!< Prescaler/glitch filter clock 2 selected. */
83 #if !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT) && \
84 FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT)
85 kLPTMR_PrescalerClock_3 = 0x3U, /*!< Prescaler/glitch filter clock 3 selected. */
86 #endif /* FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT */
87 } lptmr_prescaler_clock_select_t;
88
89 /*! @brief List of the LPTMR interrupts */
90 typedef enum _lptmr_interrupt_enable
91 {
92 kLPTMR_TimerInterruptEnable = LPTMR_CSR_TIE_MASK, /*!< Timer interrupt enable */
93 } lptmr_interrupt_enable_t;
94
95 /*! @brief List of the LPTMR status flags */
96 typedef enum _lptmr_status_flags
97 {
98 kLPTMR_TimerCompareFlag = LPTMR_CSR_TCF_MASK, /*!< Timer compare flag */
99 } lptmr_status_flags_t;
100
101 /*!
102 * @brief LPTMR config structure
103 *
104 * This structure holds the configuration settings for the LPTMR peripheral. To initialize this
105 * structure to reasonable defaults, call the LPTMR_GetDefaultConfig() function and pass a
106 * pointer to your configuration structure instance.
107 *
108 * The configuration struct can be made constant so it resides in flash.
109 */
110 typedef struct _lptmr_config
111 {
112 lptmr_timer_mode_t timerMode; /*!< Time counter mode or pulse counter mode */
113 lptmr_pin_select_t pinSelect; /*!< LPTMR pulse input pin select; used only in pulse counter mode */
114 lptmr_pin_polarity_t pinPolarity; /*!< LPTMR pulse input pin polarity; used only in pulse counter mode */
115 bool enableFreeRunning; /*!< True: enable free running, counter is reset on overflow
116 False: counter is reset when the compare flag is set */
117 bool bypassPrescaler; /*!< True: bypass prescaler; false: use clock from prescaler */
118 lptmr_prescaler_clock_select_t prescalerClockSource; /*!< LPTMR clock source */
119 lptmr_prescaler_glitch_value_t value; /*!< Prescaler or glitch filter value */
120 } lptmr_config_t;
121
122 /*******************************************************************************
123 * API
124 ******************************************************************************/
125
126 #if defined(__cplusplus)
127 extern "C" {
128 #endif
129
130 /*!
131 * @name Initialization and deinitialization
132 * @{
133 */
134
135 /*!
136 * @brief Ungates the LPTMR clock and configures the peripheral for a basic operation.
137 *
138 * @note This API should be called at the beginning of the application using the LPTMR driver.
139 *
140 * @param base LPTMR peripheral base address
141 * @param config A pointer to the LPTMR configuration structure.
142 */
143 void LPTMR_Init(LPTMR_Type *base, const lptmr_config_t *config);
144
145 /*!
146 * @brief Gates the LPTMR clock.
147 *
148 * @param base LPTMR peripheral base address
149 */
150 void LPTMR_Deinit(LPTMR_Type *base);
151
152 /*!
153 * @brief Fills in the LPTMR configuration structure with default settings.
154 *
155 * The default values are as follows.
156 * @code
157 * config->timerMode = kLPTMR_TimerModeTimeCounter;
158 * config->pinSelect = kLPTMR_PinSelectInput_0;
159 * config->pinPolarity = kLPTMR_PinPolarityActiveHigh;
160 * config->enableFreeRunning = false;
161 * config->bypassPrescaler = true;
162 * config->prescalerClockSource = kLPTMR_PrescalerClock_1;
163 * config->value = kLPTMR_Prescale_Glitch_0;
164 * @endcode
165 * @param config A pointer to the LPTMR configuration structure.
166 */
167 void LPTMR_GetDefaultConfig(lptmr_config_t *config);
168
169 /*! @}*/
170
171 /*!
172 * @name Interrupt Interface
173 * @{
174 */
175
176 /*!
177 * @brief Enables the selected LPTMR interrupts.
178 *
179 * @param base LPTMR peripheral base address
180 * @param mask The interrupts to enable. This is a logical OR of members of the
181 * enumeration ::lptmr_interrupt_enable_t
182 */
LPTMR_EnableInterrupts(LPTMR_Type * base,uint32_t mask)183 static inline void LPTMR_EnableInterrupts(LPTMR_Type *base, uint32_t mask)
184 {
185 uint32_t reg = base->CSR;
186
187 /* Clear the TCF bit so that we don't clear this w1c bit when writing back */
188 reg &= ~(LPTMR_CSR_TCF_MASK);
189 reg |= mask;
190 base->CSR = reg;
191 }
192
193 /*!
194 * @brief Disables the selected LPTMR interrupts.
195 *
196 * @param base LPTMR peripheral base address
197 * @param mask The interrupts to disable. This is a logical OR of members of the
198 * enumeration ::lptmr_interrupt_enable_t.
199 */
LPTMR_DisableInterrupts(LPTMR_Type * base,uint32_t mask)200 static inline void LPTMR_DisableInterrupts(LPTMR_Type *base, uint32_t mask)
201 {
202 uint32_t reg = base->CSR;
203
204 /* Clear the TCF bit so that we don't clear this w1c bit when writing back */
205 reg &= ~(LPTMR_CSR_TCF_MASK);
206 reg &= ~mask;
207 base->CSR = reg;
208 }
209
210 /*!
211 * @brief Gets the enabled LPTMR interrupts.
212 *
213 * @param base LPTMR peripheral base address
214 *
215 * @return The enabled interrupts. This is the logical OR of members of the
216 * enumeration ::lptmr_interrupt_enable_t
217 */
LPTMR_GetEnabledInterrupts(LPTMR_Type * base)218 static inline uint32_t LPTMR_GetEnabledInterrupts(LPTMR_Type *base)
219 {
220 return (base->CSR & LPTMR_CSR_TIE_MASK);
221 }
222
223 /*! @}*/
224
225 #if defined(FSL_FEATURE_LPTMR_HAS_CSR_TDRE) && (FSL_FEATURE_LPTMR_HAS_CSR_TDRE)
226 /*!
227 * @brief Enable or disable timer DMA request
228 *
229 * @param base base LPTMR peripheral base address
230 * @param enable Switcher of timer DMA feature. "true" means to enable, "false" means to disable.
231 */
LPTMR_EnableTimerDMA(LPTMR_Type * base,bool enable)232 static inline void LPTMR_EnableTimerDMA(LPTMR_Type *base, bool enable)
233 {
234 if (enable)
235 {
236 base->CSR |= LPTMR_CSR_TDRE_MASK;
237 }
238 else
239 {
240 base->CSR &= ~(LPTMR_CSR_TDRE_MASK);
241 }
242 }
243 #endif /* FSL_FEATURE_LPTMR_HAS_CSR_TDRE */
244
245 /*!
246 * @name Status Interface
247 * @{
248 */
249
250 /*!
251 * @brief Gets the LPTMR status flags.
252 *
253 * @param base LPTMR peripheral base address
254 *
255 * @return The status flags. This is the logical OR of members of the
256 * enumeration ::lptmr_status_flags_t
257 */
LPTMR_GetStatusFlags(LPTMR_Type * base)258 static inline uint32_t LPTMR_GetStatusFlags(LPTMR_Type *base)
259 {
260 return (base->CSR & LPTMR_CSR_TCF_MASK);
261 }
262
263 /*!
264 * @brief Clears the LPTMR status flags.
265 *
266 * @param base LPTMR peripheral base address
267 * @param mask The status flags to clear. This is a logical OR of members of the
268 * enumeration ::lptmr_status_flags_t.
269 */
LPTMR_ClearStatusFlags(LPTMR_Type * base,uint32_t mask)270 static inline void LPTMR_ClearStatusFlags(LPTMR_Type *base, uint32_t mask)
271 {
272 base->CSR |= mask;
273 }
274
275 /*! @}*/
276
277 /*!
278 * @name Read and write the timer period
279 * @{
280 */
281
282 /*!
283 * @brief Sets the timer period in units of count.
284 *
285 * Timers counts from 0 until it equals the count value set here. The count value is written to
286 * the CMR register.
287 *
288 * @note
289 * 1. The TCF flag is set with the CNR equals the count provided here and then increments.
290 * 2. Call the utility macros provided in the fsl_common.h to convert to ticks.
291 *
292 * @param base LPTMR peripheral base address
293 * @param ticks A timer period in units of ticks, which should be equal or greater than 1.
294 */
LPTMR_SetTimerPeriod(LPTMR_Type * base,uint32_t ticks)295 static inline void LPTMR_SetTimerPeriod(LPTMR_Type *base, uint32_t ticks)
296 {
297 assert(ticks > 0U);
298 base->CMR = LPTMR_CMR_COMPARE(ticks - 1U);
299 }
300
301 /*!
302 * @brief Reads the current timer counting value.
303 *
304 * This function returns the real-time timer counting value in a range from 0 to a
305 * timer period.
306 *
307 * @note Call the utility macros provided in the fsl_common.h to convert ticks to usec or msec.
308 *
309 * @param base LPTMR peripheral base address
310 *
311 * @return The current counter value in ticks
312 */
LPTMR_GetCurrentTimerCount(LPTMR_Type * base)313 static inline uint32_t LPTMR_GetCurrentTimerCount(LPTMR_Type *base)
314 {
315 /* Must first write any value to the CNR. This synchronizes and registers the current value
316 * of the CNR into a temporary register which can then be read
317 */
318 base->CNR = 0U;
319 return (uint32_t)((base->CNR & LPTMR_CNR_COUNTER_MASK) >> LPTMR_CNR_COUNTER_SHIFT);
320 }
321
322 /*! @}*/
323
324 /*!
325 * @name Timer Start and Stop
326 * @{
327 */
328
329 /*!
330 * @brief Starts the timer.
331 *
332 * After calling this function, the timer counts up to the CMR register value.
333 * Each time the timer reaches the CMR value and then increments, it generates a
334 * trigger pulse and sets the timeout interrupt flag. An interrupt is also
335 * triggered if the timer interrupt is enabled.
336 *
337 * @param base LPTMR peripheral base address
338 */
LPTMR_StartTimer(LPTMR_Type * base)339 static inline void LPTMR_StartTimer(LPTMR_Type *base)
340 {
341 uint32_t reg = base->CSR;
342
343 /* Clear the TCF bit to avoid clearing the w1c bit when writing back. */
344 reg &= ~(LPTMR_CSR_TCF_MASK);
345 reg |= LPTMR_CSR_TEN_MASK;
346 base->CSR = reg;
347 }
348
349 /*!
350 * @brief Stops the timer.
351 *
352 * This function stops the timer and resets the timer's counter register.
353 *
354 * @param base LPTMR peripheral base address
355 */
LPTMR_StopTimer(LPTMR_Type * base)356 static inline void LPTMR_StopTimer(LPTMR_Type *base)
357 {
358 uint32_t reg = base->CSR;
359
360 /* Clear the TCF bit to avoid clearing the w1c bit when writing back. */
361 reg &= ~(LPTMR_CSR_TCF_MASK);
362 reg &= ~LPTMR_CSR_TEN_MASK;
363 base->CSR = reg;
364 }
365
366 /*! @}*/
367
368 #if defined(__cplusplus)
369 }
370 #endif
371
372 /*! @}*/
373
374 #endif /* _FSL_LPTMR_H_ */
375
