1 /*
2 * Copyright (c) 2021 Vestas Wind Systems A/S
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <zephyr/devicetree.h>
8 #if DT_HAS_COMPAT_STATUS_OKAY(nxp_kinetis_lptmr)
9 #define DT_DRV_COMPAT nxp_kinetis_lptmr
10 #else
11 #define DT_DRV_COMPAT nxp_lptmr
12 #endif
13
14 #include <zephyr/init.h>
15 #include <zephyr/drivers/timer/system_timer.h>
16 #include <zephyr/kernel.h>
17 #include <zephyr/sys/time_units.h>
18 #include <fsl_lptmr.h>
19 #include <zephyr/irq.h>
20
21 BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1,
22 "No LPTMR instance enabled in devicetree");
23
24 /* Prescaler mapping */
25 #define LPTMR_PRESCALER_2 kLPTMR_Prescale_Glitch_0
26 #define LPTMR_PRESCALER_4 kLPTMR_Prescale_Glitch_1
27 #define LPTMR_PRESCALER_8 kLPTMR_Prescale_Glitch_2
28 #define LPTMR_PRESCALER_16 kLPTMR_Prescale_Glitch_3
29 #define LPTMR_PRESCALER_32 kLPTMR_Prescale_Glitch_4
30 #define LPTMR_PRESCALER_64 kLPTMR_Prescale_Glitch_5
31 #define LPTMR_PRESCALER_128 kLPTMR_Prescale_Glitch_6
32 #define LPTMR_PRESCALER_256 kLPTMR_Prescale_Glitch_7
33 #define LPTMR_PRESCALER_512 kLPTMR_Prescale_Glitch_8
34 #define LPTMR_PRESCALER_1024 kLPTMR_Prescale_Glitch_9
35 #define LPTMR_PRESCALER_2048 kLPTMR_Prescale_Glitch_10
36 #define LPTMR_PRESCALER_4096 kLPTMR_Prescale_Glitch_11
37 #define LPTMR_PRESCALER_8192 kLPTMR_Prescale_Glitch_12
38 #define LPTMR_PRESCALER_16384 kLPTMR_Prescale_Glitch_13
39 #define LPTMR_PRESCALER_32768 kLPTMR_Prescale_Glitch_14
40 #define LPTMR_PRESCALER_65536 kLPTMR_Prescale_Glitch_15
41 #define TO_LPTMR_PRESCALER(val) _DO_CONCAT(LPTMR_PRESCALER_, val)
42
43 /* Prescaler clock mapping */
44 #define TO_LPTMR_CLK_SEL(val) _DO_CONCAT(kLPTMR_PrescalerClock_, val)
45
46 /* Devicetree properties */
47 #define LPTMR_BASE ((LPTMR_Type *)(DT_INST_REG_ADDR(0)))
48 #define LPTMR_CLK_SOURCE TO_LPTMR_CLK_SEL(DT_INST_PROP(0, clk_source));
49 #define LPTMR_PRESCALER TO_LPTMR_PRESCALER(DT_INST_PROP(0, prescaler));
50 #define LPTMR_BYPASS_PRESCALER DT_INST_PROP(0, prescaler) == 1
51 #define LPTMR_IRQN DT_INST_IRQN(0)
52 #define LPTMR_IRQ_PRIORITY DT_INST_IRQ(0, priority)
53
54 /* Timer cycles per tick */
55 #define CYCLES_PER_TICK ((uint32_t)((uint64_t)sys_clock_hw_cycles_per_sec() \
56 / (uint64_t)CONFIG_SYS_CLOCK_TICKS_PER_SEC))
57
58 /* 32 bit cycle counter */
59 static volatile uint32_t cycles;
60
sys_clock_set_timeout(int32_t ticks,bool idle)61 void sys_clock_set_timeout(int32_t ticks, bool idle)
62 {
63 ARG_UNUSED(idle);
64
65 if (idle && (ticks == K_TICKS_FOREVER)) {
66 LPTMR_DisableInterrupts(LPTMR_BASE, kLPTMR_TimerInterruptEnable);
67 }
68 }
69
sys_clock_idle_exit(void)70 void sys_clock_idle_exit(void)
71 {
72 if (LPTMR_GetEnabledInterrupts(LPTMR_BASE) != kLPTMR_TimerInterruptEnable) {
73 LPTMR_EnableInterrupts(LPTMR_BASE, kLPTMR_TimerInterruptEnable);
74 }
75 }
76
sys_clock_disable(void)77 void sys_clock_disable(void)
78 {
79 LPTMR_DisableInterrupts(LPTMR_BASE, kLPTMR_TimerInterruptEnable);
80 LPTMR_StopTimer(LPTMR_BASE);
81 }
82
sys_clock_elapsed(void)83 uint32_t sys_clock_elapsed(void)
84 {
85 return 0;
86 }
87
sys_clock_cycle_get_32(void)88 uint32_t sys_clock_cycle_get_32(void)
89 {
90 return LPTMR_GetCurrentTimerCount(LPTMR_BASE) + cycles;
91 }
92
mcux_lptmr_timer_isr(const void * arg)93 static void mcux_lptmr_timer_isr(const void *arg)
94 {
95 ARG_UNUSED(arg);
96
97 cycles += CYCLES_PER_TICK;
98
99 sys_clock_announce(1);
100 LPTMR_ClearStatusFlags(LPTMR_BASE, kLPTMR_TimerCompareFlag);
101 }
102
sys_clock_driver_init(void)103 static int sys_clock_driver_init(void)
104 {
105 lptmr_config_t config;
106
107
108 LPTMR_GetDefaultConfig(&config);
109 config.timerMode = kLPTMR_TimerModeTimeCounter;
110 config.enableFreeRunning = false;
111 config.prescalerClockSource = LPTMR_CLK_SOURCE;
112
113 #if LPTMR_BYPASS_PRESCALER
114 config.bypassPrescaler = true;
115 #else /* LPTMR_BYPASS_PRESCALER */
116 config.bypassPrescaler = false;
117 config.value = LPTMR_PRESCALER;
118 #endif /* !LPTMR_BYPASS_PRESCALER */
119
120 LPTMR_Init(LPTMR_BASE, &config);
121
122 IRQ_CONNECT(LPTMR_IRQN, LPTMR_IRQ_PRIORITY, mcux_lptmr_timer_isr, NULL, 0);
123 irq_enable(LPTMR_IRQN);
124
125 LPTMR_EnableInterrupts(LPTMR_BASE, kLPTMR_TimerInterruptEnable);
126 LPTMR_SetTimerPeriod(LPTMR_BASE, CYCLES_PER_TICK);
127 LPTMR_StartTimer(LPTMR_BASE);
128
129 return 0;
130 }
131
132 SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2,
133 CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);
134
