1 /* 2 * Copyright 2021-2023 NXP 3 * All rights reserved. 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 */ 7 8 #ifndef __FLASH_CONFIG__ 9 #define __FLASH_CONFIG__ 10 11 #include <stdint.h> 12 #include <stdbool.h> 13 #include "fsl_common.h" 14 15 16 #define FC_BLOCK_TAG (0x42464346) 17 #define FC_BLOCK_VERSION (0x00000000) 18 19 #define FC_CMD_SDR 0x01 20 #define FC_CMD_DDR 0x21 21 #define FC_RADDR_SDR 0x02 22 #define FC_RADDR_DDR 0x22 23 #define FC_CADDR_SDR 0x03 24 #define FC_CADDR_DDR 0x23 25 #define FC_MODE1_SDR 0x04 26 #define FC_MODE1_DDR 0x24 27 #define FC_MODE2_SDR 0x05 28 #define FC_MODE2_DDR 0x25 29 #define FC_MODE4_SDR 0x06 30 #define FC_MODE4_DDR 0x26 31 #define FC_MODE8_SDR 0x07 32 #define FC_MODE8_DDR 0x27 33 #define FC_WRITE_SDR 0x08 34 #define FC_WRITE_DDR 0x28 35 #define FC_READ_SDR 0x09 36 #define FC_READ_DDR 0x29 37 #define FC_LEARN_SDR 0x0A 38 #define FC_LEARN_DDR 0x2A 39 #define FC_DATSZ_SDR 0x0B 40 #define FC_DATSZ_DDR 0x2B 41 #define FC_DUMMY_SDR 0x0C 42 #define FC_DUMMY_DDR 0x2C 43 #define FC_DUMMY_RWDS_SDR 0x0D 44 #define FC_DUMMY_RWDS_DDR 0x2D 45 #define FC_JMP_ON_CS 0x1F 46 #define FC_STOP_EXE 0 47 48 #define FC_FLEXSPI_1PAD 0 49 #define FC_FLEXSPI_2PAD 1 50 #define FC_FLEXSPI_4PAD 2 51 #define FC_FLEXSPI_8PAD 3 52 53 #define FC_FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ 54 (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | \ 55 FLEXSPI_LUT_OPERAND1(op1) | FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) 56 57 58 enum { 59 kSerialFlash_1Pads = 1, 60 kSerialFlash_2Pads = 2, 61 kSerialFlash_4Pads = 4, 62 kSerialFlash_8Pads = 8, 63 }; 64 65 66 enum { 67 kFlexSpiSerialClk_30MHz = 1, 68 kFlexSpiSerialClk_50MHz = 2, 69 kFlexSpiSerialClk_60MHz = 3, 70 kFlexSpiSerialClk_80MHz = 4, 71 kFlexSpiSerialClk_100MHz = 5, 72 kFlexSpiSerialClk_120MHz = 6, 73 kFlexSpiSerialClk_133MHz = 7, 74 kFlexSpiSerialClk_166MHz = 8, 75 kFlexSpiSerialClk_200MHz = 9, 76 }; 77 78 79 enum { 80 kFlexSpiSerialClk_SDR_24MHz = 1, 81 kFlexSpiSerialClk_SDR_48MHz = 2, 82 }; 83 84 85 enum { 86 kFlexSpiSerialClk_DDR_48MHz = 1, 87 }; 88 89 90 enum { 91 kFlexSpiMiscOffset_DiffClkEnable = 0, 92 kFlexSpiMiscOffset_WordAddressableEnable = 3, 93 kFlexSpiMiscOffset_SafeConfigFreqEnable = 94 4, 95 kFlexSpiMiscOffset_DdrModeEnable = 6, 96 }; 97 98 99 enum { 100 kDeviceConfigCmdType_Generic, 101 kDeviceConfigCmdType_QuadEnable, 102 kDeviceConfigCmdType_Spi2Xpi, 103 kDeviceConfigCmdType_Xpi2Spi, 104 kDeviceConfigCmdType_Spi2NoCmd, 105 kDeviceConfigCmdType_Reset, 106 }; 107 108 typedef struct _fc_flexspi_dll_time { 109 uint8_t time_100ps; 110 uint8_t delay_cells; 111 } fc_flexspi_dll_time_t; 112 113 114 typedef struct _fc_flexspi_lut_seq { 115 uint8_t seqNum; 116 uint8_t seqId; 117 uint16_t reserved; 118 } fc_flexspi_lut_seq_t; 119 120 121 typedef struct _fc_flexspi_mem_config { 122 uint32_t tag; 123 uint32_t version; 124 uint32_t reserved0; 125 uint8_t readSampleClkSrc; 126 uint8_t csHoldTime; 127 uint8_t csSetupTime; 128 uint8_t columnAddressWidth; 129 uint8_t deviceModeCfgEnable; 130 uint8_t deviceModeType; 131 uint16_t waitTimeCfgCommands; 132 fc_flexspi_lut_seq_t deviceModeSeq; 133 uint32_t deviceModeArg; 134 uint8_t configCmdEnable; 135 uint8_t configModeType[3]; 136 fc_flexspi_lut_seq_t configCmdSeqs[3]; 137 uint32_t reserved1; 138 uint32_t configCmdArgs[3]; 139 uint32_t reserved2; 140 uint32_t controllerMiscOption; 141 uint8_t deviceType; 142 uint8_t sflashPadType; 143 uint8_t serialClkFreq; 144 uint8_t lutCustomSeqEnable; 145 uint32_t reserved3[2]; 146 uint32_t sflashA1Size; 147 uint32_t sflashA2Size; 148 uint32_t sflashB1Size; 149 uint32_t sflashB2Size; 150 uint32_t csPadSettingOverride; 151 uint32_t sclkPadSettingOverride; 152 uint32_t dataPadSettingOverride; 153 uint32_t dqsPadSettingOverride; 154 uint32_t timeoutInMs; 155 uint32_t commandInterval; 156 fc_flexspi_dll_time_t dataValidTime[2]; 157 uint16_t busyOffset; 158 uint16_t busyBitPolarity; 159 uint32_t lookupTable[64]; 160 fc_flexspi_lut_seq_t lutCustomSeq[12]; 161 uint32_t reserved4[4]; 162 } fc_flexspi_mem_config_t; 163 164 typedef struct _fc_flexspi_nor_config { 165 #if defined(__ARMCC_VERSION) || defined(__ICCARM__) 166 uint8_t padding[0x400]; 167 #endif 168 fc_flexspi_mem_config_t memConfig; 169 uint32_t pageSize; 170 uint32_t sectorSize; 171 uint8_t ipcmdSerialClkFreq; 172 uint8_t isUniformBlockSize; 173 uint8_t isDataOrderSwapped; 174 uint8_t reserved0[1]; 175 uint8_t serialNorType; 176 uint8_t needExitNoCmdMode; 177 uint8_t halfClkForNonReadCmd; 178 uint8_t needRestoreNoCmdMode; 179 uint32_t blockSize; 180 uint32_t flashStateCtx; 181 uint32_t reserve2[10]; 182 uint32_t fcb_fill[0x280]; 183 } fc_flexspi_nor_config_t; 184 #ifdef __cplusplus 185 extern "C" { 186 #endif 187 188 #ifdef __cplusplus 189 } 190 #endif 191 #endif 192
