1 /* 2 * Copyright (c) 2015, Freescale Semiconductor, Inc. 3 * Copyright 2016-2017 NXP 4 * 5 * Redistribution and use in source and binary forms, with or without modification, 6 * are permitted provided that the following conditions are met: 7 * 8 * o Redistributions of source code must retain the above copyright notice, this list 9 * of conditions and the following disclaimer. 10 * 11 * o Redistributions in binary form must reproduce the above copyright notice, this 12 * list of conditions and the following disclaimer in the documentation and/or 13 * other materials provided with the distribution. 14 * 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its 16 * contributors may be used to endorse or promote products derived from this 17 * software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include "fsl_xcvr.h" 32 33 /******************************************************************************* 34 * Definitions 35 ******************************************************************************/ 36 37 /******************************************************************************* 38 * Prototypes 39 ******************************************************************************/ 40 41 /******************************************************************************* 42 * Variables 43 ******************************************************************************/ 44 45 /******************************************************************************* 46 * Code 47 ******************************************************************************/ 48 const xcvr_common_config_t xcvr_common_config = 49 { 50 /* XCVR_ANA configs */ 51 .ana_sy_ctrl1.mask = XCVR_ANALOG_SY_CTRL_1_SY_LPF_FILT_CTRL_MASK, 52 .ana_sy_ctrl1.init = XCVR_ANALOG_SY_CTRL_1_SY_LPF_FILT_CTRL(3), /* PLL Analog Loop Filter */ 53 54 #define hpm_vcm_tx 0 55 #define hpm_vcm_cal 1 56 #define hpm_fdb_res_tx 0 57 #define hpm_fdb_res_cal 1 58 #define modulation_word_manual 0 59 #define mod_disable 0 60 #define hpm_mod_manual 0 61 #define hpm_mod_disable 0 62 #define hpm_sdm_out_manual 0 63 #define hpm_sdm_out_disable 0 64 #define channel_num 0 65 #define boc 0 66 #define bmr 1 67 #define zoc 0 68 #define ctune_ldf_lev 8 69 #define ftf_rx_thrsh 33 70 #define ftw_rx 0 71 #define ftf_tx_thrsh 6 72 #define ftw_tx 0 73 #define freq_count_go 0 74 #define freq_count_time 0 75 #define hpm_sdm_in_manual 0 76 #define hpm_sdm_out_invert 0 77 #define hpm_sdm_in_disable 0 78 #define hpm_lfsr_size 4 79 #define hpm_dth_scl 0 80 #define hpm_dth_en 1 81 #define hpm_integer_scale 0 82 #define hpm_integer_invert 0 83 #define hpm_cal_invert 1 84 #define hpm_mod_in_invert 1 85 #define hpm_cal_not_bumped 0 86 #define hpm_cal_count_scale 0 87 #define hp_cal_disable 0 88 #define hpm_cal_factor_manual 0 89 #define hpm_cal_array_size 1 90 #define hpm_cal_time 0 91 #define hpm_sdm_denom 256 92 #define hpm_count_adjust 0 93 #define pll_ld_manual 0 94 #define pll_ld_disable 0 95 #define lpm_sdm_inv 0 96 #define lpm_disable 0 97 #define lpm_dth_scl 8 98 #define lpm_d_ctrl 1 99 #define lpm_d_ovrd 1 100 #define lpm_scale 8 101 #define lpm_sdm_use_neg 0 102 #define hpm_array_bias 0 103 #define lpm_intg 38 104 #define sdm_map_disable 0 105 #define lpm_sdm_delay 4 106 #define hpm_sdm_delay 0 107 #define hpm_integer_delay 0 108 #define ctune_target_manual 0 109 #define ctune_target_disable 0 110 #define ctune_adjust 0 111 #define ctune_manual 0 112 #define ctune_disable 0 113 114 /*-------------------------------------------------------------------------------------------------*/ 115 116 .pll_hpm_bump = XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_CAL(hpm_fdb_res_cal) | 117 XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_TX(hpm_fdb_res_tx) | 118 XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_CAL(hpm_vcm_cal) | 119 XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_TX(hpm_vcm_tx), 120 121 /*-------------------------------------------------------------------------------------------------*/ 122 123 .pll_mod_ctrl = XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_DISABLE(hpm_mod_disable) | 124 XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_MANUAL(hpm_mod_manual) | 125 XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_DISABLE(hpm_sdm_out_disable) | 126 XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_MANUAL(hpm_sdm_out_manual) | 127 XCVR_PLL_DIG_MOD_CTRL_MOD_DISABLE(mod_disable) | 128 XCVR_PLL_DIG_MOD_CTRL_MODULATION_WORD_MANUAL(modulation_word_manual), 129 130 /*-------------------------------------------------------------------------------------------------*/ 131 132 .pll_chan_map = XCVR_PLL_DIG_CHAN_MAP_BMR(bmr) | 133 XCVR_PLL_DIG_CHAN_MAP_BOC(boc) | 134 XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM(channel_num) 135 #if !RADIO_IS_GEN_2P1 136 | XCVR_PLL_DIG_CHAN_MAP_ZOC(zoc) 137 #endif /* !RADIO_IS_GEN_2P1 */ 138 , 139 140 /*-------------------------------------------------------------------------------------------------*/ 141 142 .pll_lock_detect = XCVR_PLL_DIG_LOCK_DETECT_CTUNE_LDF_LEV(ctune_ldf_lev) | 143 XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_GO(freq_count_go) | 144 XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_TIME(freq_count_time) | 145 XCVR_PLL_DIG_LOCK_DETECT_FTF_RX_THRSH(ftf_rx_thrsh) | 146 XCVR_PLL_DIG_LOCK_DETECT_FTF_TX_THRSH(ftf_tx_thrsh) | 147 XCVR_PLL_DIG_LOCK_DETECT_FTW_RX(ftw_rx) | 148 XCVR_PLL_DIG_LOCK_DETECT_FTW_TX(ftw_tx), 149 150 /*-------------------------------------------------------------------------------------------------*/ 151 152 .pll_hpm_ctrl = XCVR_PLL_DIG_HPM_CTRL_HPM_CAL_INVERT(hpm_cal_invert) | 153 XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_EN(hpm_dth_en) | 154 XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_SCL(hpm_dth_scl) | 155 XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_INVERT(hpm_integer_invert) | 156 XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_SCALE(hpm_integer_scale) | 157 XCVR_PLL_DIG_HPM_CTRL_HPM_LFSR_SIZE(hpm_lfsr_size) | 158 XCVR_PLL_DIG_HPM_CTRL_HPM_MOD_IN_INVERT(hpm_mod_in_invert) | 159 XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_DISABLE(hpm_sdm_in_disable) | 160 XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_MANUAL(hpm_sdm_in_manual) | 161 XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_OUT_INVERT(hpm_sdm_out_invert), 162 /*-------------------------------------------------------------------------------------------------*/ 163 #if !RADIO_IS_GEN_2P1 164 .pll_hpmcal_ctrl = XCVR_PLL_DIG_HPMCAL_CTRL_HP_CAL_DISABLE(hp_cal_disable) | 165 XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_ARRAY_SIZE(hpm_cal_array_size) | 166 XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_COUNT_SCALE(hpm_cal_count_scale) | 167 XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_FACTOR_MANUAL(hpm_cal_factor_manual) | 168 XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_NOT_BUMPED(hpm_cal_not_bumped) | 169 XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_TIME(hpm_cal_time), 170 #endif /* !RADIO_IS_GEN_2P1 */ 171 /*-------------------------------------------------------------------------------------------------*/ 172 .pll_hpm_sdm_res = XCVR_PLL_DIG_HPM_SDM_RES_HPM_COUNT_ADJUST(hpm_count_adjust) | 173 XCVR_PLL_DIG_HPM_SDM_RES_HPM_DENOM(hpm_sdm_denom), 174 /*-------------------------------------------------------------------------------------------------*/ 175 .pll_lpm_ctrl = XCVR_PLL_DIG_LPM_CTRL_LPM_D_CTRL(lpm_d_ctrl) | 176 XCVR_PLL_DIG_LPM_CTRL_LPM_D_OVRD(lpm_d_ovrd) | 177 XCVR_PLL_DIG_LPM_CTRL_LPM_DISABLE(lpm_disable) | 178 XCVR_PLL_DIG_LPM_CTRL_LPM_DTH_SCL(lpm_dth_scl) | 179 XCVR_PLL_DIG_LPM_CTRL_LPM_SCALE(lpm_scale) | 180 XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_INV(lpm_sdm_inv) | 181 XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_USE_NEG(lpm_sdm_use_neg) | 182 XCVR_PLL_DIG_LPM_CTRL_PLL_LD_DISABLE(pll_ld_disable) | 183 XCVR_PLL_DIG_LPM_CTRL_PLL_LD_MANUAL(pll_ld_manual), 184 /*-------------------------------------------------------------------------------------------------*/ 185 .pll_lpm_sdm_ctrl1 = XCVR_PLL_DIG_LPM_SDM_CTRL1_HPM_ARRAY_BIAS(hpm_array_bias) | 186 XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG(lpm_intg) | 187 XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE(sdm_map_disable), 188 /*-------------------------------------------------------------------------------------------------*/ 189 .pll_delay_match = XCVR_PLL_DIG_DELAY_MATCH_HPM_INTEGER_DELAY(hpm_integer_delay) | 190 XCVR_PLL_DIG_DELAY_MATCH_HPM_SDM_DELAY(hpm_sdm_delay) | 191 XCVR_PLL_DIG_DELAY_MATCH_LPM_SDM_DELAY(lpm_sdm_delay), 192 /*-------------------------------------------------------------------------------------------------*/ 193 .pll_ctune_ctrl = XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_ADJUST(ctune_adjust) | 194 XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_DISABLE(ctune_disable) | 195 XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_MANUAL(ctune_manual) | 196 XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_DISABLE(ctune_target_disable) | 197 XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL(ctune_target_manual), 198 /*-------------------------------------------------------------------------------------------------*/ 199 200 /* XCVR_RX_DIG configs */ 201 /* NOTE: Clock specific settings are embedded in the mode dependent configs */ 202 .rx_dig_ctrl_init = XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_NEGEDGE(0) | 203 XCVR_RX_DIG_RX_DIG_CTRL_RX_CH_FILT_BYPASS(0) | 204 #if !RADIO_IS_GEN_2P1 205 XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_RAW_EN(0) | 206 #endif /* !RADIO_IS_GEN_2P1 */ 207 XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_POL(0) | 208 XCVR_RX_DIG_RX_DIG_CTRL_RX_NORM_EN(1) | 209 XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_EN(1) | 210 XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN(1) | 211 XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_EN(1) | 212 XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN(1) | 213 XCVR_RX_DIG_RX_DIG_CTRL_RX_IQ_SWAP(0) | 214 XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN(0) | 215 XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HZD_CORR_DIS(1), 216 217 .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | 218 XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2) | 219 XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_EN(1) | 220 XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_PRE_OR_AA(0) | 221 XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_EN(1) | 222 XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_SRC(0) | 223 XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_BBA_STEP_SZ(2) | 224 XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_LNA_STEP_SZ(2) | 225 XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_RSSI_THRESH(0xe7), 226 227 .agc_ctrl_3_init = XCVR_RX_DIG_AGC_CTRL_3_AGC_UNFREEZE_TIME(21) | 228 XCVR_RX_DIG_AGC_CTRL_3_AGC_PDET_LO_DLY(2) | 229 XCVR_RX_DIG_AGC_CTRL_3_AGC_RSSI_DELT_H2S(20) | 230 XCVR_RX_DIG_AGC_CTRL_3_AGC_H2S_STEP_SZ(6) | 231 XCVR_RX_DIG_AGC_CTRL_3_AGC_UP_STEP_SZ(2), 232 233 /* DCOC configs */ 234 .dcoc_ctrl_0_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_DURATION(16) | /* Only the duration changes between 26MHz and 32MHz ref osc settings */ 235 #if (RADIO_IS_GEN_2P1) 236 XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_CHECK_EN(0) | 237 #endif /* (RADIO_IS_GEN_2P1) */ 238 XCVR_RX_DIG_DCOC_CTRL_0_TRACK_FROM_ZERO(0) | 239 XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN(1) | 240 XCVR_RX_DIG_DCOC_CTRL_0_TZA_CORR_POL(0) | 241 XCVR_RX_DIG_DCOC_CTRL_0_BBA_CORR_POL(0) | 242 XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC(1), 243 .dcoc_ctrl_0_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_DURATION(20) | /* Only the duration changes between 26MHz and 32MHz ref osc settings */ 244 #if (RADIO_IS_GEN_2P1) 245 XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_CHECK_EN(0) | 246 #endif /* (RADIO_IS_GEN_2P1) */ 247 XCVR_RX_DIG_DCOC_CTRL_0_TRACK_FROM_ZERO(0) | 248 XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN(1) | 249 XCVR_RX_DIG_DCOC_CTRL_0_TZA_CORR_POL(0) | 250 XCVR_RX_DIG_DCOC_CTRL_0_BBA_CORR_POL(0) | 251 XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC(1), 252 253 .dcoc_ctrl_1_init = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_MIN_AGC_IDX(26), 254 255 .dc_resid_ctrl_init = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ITER_FREEZE(4) | 256 XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ALPHA(1) | 257 XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_EXT_DC_EN(1) | 258 XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_MIN_AGC_IDX(26), 259 260 .dcoc_cal_gain_init = XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN1(1) | 261 XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN1(1) | 262 XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN2(1) | 263 XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN2(2) | 264 XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN3(3) | 265 XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN3(1) , 266 267 .dcoc_cal_rcp_init = XCVR_RX_DIG_DCOC_CAL_RCP_ALPHA_CALC_RECIP(1) | 268 XCVR_RX_DIG_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP(711), 269 270 .lna_gain_val_3_0 = XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_0(0x1DU) | 271 XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_1(0x32U) | 272 XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_2(0x09U) | 273 XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_3(0x38U), 274 275 .lna_gain_val_7_4 = XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_4(0x4FU) | 276 XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_5(0x5BU) | 277 XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_6(0x72U) | 278 XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_7(0x8AU), 279 .lna_gain_val_8 = XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_8(0xA0U) | 280 XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_9(0xB6U), 281 282 .bba_res_tune_val_7_0 = XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_0(0x0) | 283 XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_1(0x0) | 284 XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_2(0x0) | 285 XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_3(0x0) | 286 XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_4(0x0) | 287 XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_5(0x0) | 288 XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_6(0x0) | 289 XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_7(0xF), 290 .bba_res_tune_val_10_8 = XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_8(0x0) | 291 XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_9(0x1) | 292 XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_10(0x2), 293 294 .lna_gain_lin_val_2_0_init = XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_0(0) | 295 XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_1(0) | 296 XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_2(1), 297 298 .lna_gain_lin_val_5_3_init = XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_3(3) | 299 XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_4(5) | 300 XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_5(7), 301 302 .lna_gain_lin_val_8_6_init = XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_6(14) | 303 XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_7(27) | 304 XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_8(50), 305 306 .lna_gain_lin_val_9_init = XCVR_RX_DIG_LNA_GAIN_LIN_VAL_9_LNA_GAIN_LIN_VAL_9(91), 307 308 .bba_res_tune_lin_val_3_0_init = XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_0(8) | 309 XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_1(11) | 310 XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_2(16) | 311 XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_3(22), 312 313 .bba_res_tune_lin_val_7_4_init = XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_4(31) | 314 XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_5(44) | 315 XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_6(62) | 316 XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_7(42), /* Has 2 fractional bits unlike other BBA_RES_TUNE_LIN_VALs */ 317 318 .bba_res_tune_lin_val_10_8_init = XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_8(128) | 319 XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_9(188) | 320 XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_10(288), 321 322 .dcoc_bba_step_init = XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP(939) | 323 XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP(279), 324 325 .dcoc_tza_step_00_init = XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0(77) | 326 XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0(3404), 327 .dcoc_tza_step_01_init = XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_GAIN_1(108) | 328 XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_RCP_1(2439), 329 .dcoc_tza_step_02_init = XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_GAIN_2(155) | 330 XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_RCP_2(1691), 331 .dcoc_tza_step_03_init = XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_GAIN_3(220) | 332 XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_RCP_3(1192), 333 .dcoc_tza_step_04_init = XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_GAIN_4(314) | 334 XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_RCP_4(835), 335 .dcoc_tza_step_05_init = XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_GAIN_5(436) | 336 XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_RCP_5(601), 337 .dcoc_tza_step_06_init = XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_GAIN_6(614) | 338 XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_RCP_6(427), 339 .dcoc_tza_step_07_init = XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_GAIN_7(845) | 340 XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_RCP_7(310), 341 .dcoc_tza_step_08_init = XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_GAIN_8(1256) | 342 XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_RCP_8(209), 343 .dcoc_tza_step_09_init = XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_GAIN_9(1805) | 344 XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_RCP_9(145), 345 .dcoc_tza_step_10_init = XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_GAIN_10(2653) | 346 XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_RCP_10(99), 347 #if (RADIO_IS_GEN_2P1) 348 .dcoc_cal_fail_th_init = XCVR_RX_DIG_DCOC_CAL_FAIL_TH_DCOC_CAL_BETA_F_TH(20) | 349 XCVR_RX_DIG_DCOC_CAL_FAIL_TH_DCOC_CAL_ALPHA_F_TH(10), 350 .dcoc_cal_pass_th_init = XCVR_RX_DIG_DCOC_CAL_PASS_TH_DCOC_CAL_BETA_P_TH(16) | 351 XCVR_RX_DIG_DCOC_CAL_PASS_TH_DCOC_CAL_ALPHA_P_TH(2), 352 #endif /* (RADIO_IS_GEN_2P1) */ 353 /* AGC Configs */ 354 .agc_gain_tbl_03_00_init = XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_00(0) | 355 XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_00(0) | 356 XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_01(1) | 357 XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_01(1) | 358 XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_02(2) | 359 XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_02(1) | 360 XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_03(2) | 361 XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_03(2), 362 363 .agc_gain_tbl_07_04_init = XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_04(2) | 364 XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_04(3) | 365 XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_05(3) | 366 XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_05(0) | 367 XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_06(3) | 368 XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_06(1) | 369 XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_07(3) | 370 XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_07(2), 371 372 .agc_gain_tbl_11_08_init = XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_08(3) | 373 XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_08(3) | 374 XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_09(4) | 375 XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_09(2) | 376 XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_10(4) | 377 XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_10(3) | 378 XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_11(4) | 379 XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_11(4), 380 381 .agc_gain_tbl_15_12_init = XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_12(5) | 382 XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_12(4) | 383 XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_13(5) | 384 XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_13(5) | 385 XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_14(6) | 386 XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_14(4) | 387 XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_15(6) | 388 XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_15(5), 389 390 .agc_gain_tbl_19_16_init = XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_16(6) | 391 XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_16(6) | 392 XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_17(6) | 393 XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_17(7) | 394 XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_18(7) | 395 XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_18(6) | 396 XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_19(7) | 397 XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_19(7), 398 399 .agc_gain_tbl_23_20_init = XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_20(8) | 400 XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_20(6) | 401 XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_21(8) | 402 XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_21(7) | 403 XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_22(9) | 404 XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_22(6) | 405 XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_23(9) | 406 XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_23(7), 407 408 .agc_gain_tbl_26_24_init = XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_24(9) | 409 XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_24(8) | 410 XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_25(9) | 411 XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_25(9) | 412 XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_26(9) | 413 XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_26(10), 414 415 .rssi_ctrl_0_init = XCVR_RX_DIG_RSSI_CTRL_0_RSSI_USE_VALS(1) | 416 XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_SRC(0) | 417 XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_EN(1) | 418 XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT(0) | 419 #if !RADIO_IS_GEN_2P1 420 XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_AVG(1) | 421 #else 422 XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_NB(1) | 423 #endif /* !RADIO_IS_GEN_2P1 */ 424 XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_DELAY(4) | 425 XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_WEIGHT(3) | 426 XCVR_RX_DIG_RSSI_CTRL_0_RSSI_VLD_SETTLE(3) | 427 XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ(0xE8) , 428 429 .cca_ed_lqi_ctrl_0_init = XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CORR_THRESH(0) | 430 XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_CORR_CNTR_THRESH(0) | 431 XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CNTR(0x1A) | 432 XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_SNR_ADJ(0), 433 434 .cca_ed_lqi_ctrl_1_init = XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_DELAY(0) | 435 XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_FACTOR(0) | 436 XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_WEIGHT(0x4) | 437 XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_SENS(0x7) | 438 XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_DIS(0) | 439 #if !RADIO_IS_GEN_2P1 440 XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SEL_SNR_MODE(0) | 441 #endif /* !RADIO_IS_GEN_2P1 */ 442 XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MEAS_TRANS_TO_IDLE(0) | 443 XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_CCA1_ED_EN_DIS(0) | 444 XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_MEAS_COMPLETE(0) | 445 XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_AA_MATCH(0) | 446 XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_WEIGHT(0x5) | 447 XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_BIAS(0x2), 448 449 /* XCVR_TSM configs */ 450 .tsm_ctrl = XCVR_TSM_CTRL_PA_RAMP_SEL(PA_RAMP_SEL) | 451 XCVR_TSM_CTRL_DATA_PADDING_EN(DATA_PADDING_EN) | 452 XCVR_TSM_CTRL_TSM_IRQ0_EN(0) | 453 XCVR_TSM_CTRL_TSM_IRQ1_EN(0) | 454 XCVR_TSM_CTRL_RAMP_DN_DELAY(0x4) | 455 XCVR_TSM_CTRL_TX_ABORT_DIS(0) | 456 XCVR_TSM_CTRL_RX_ABORT_DIS(0) | 457 XCVR_TSM_CTRL_ABORT_ON_CTUNE(0) | 458 XCVR_TSM_CTRL_ABORT_ON_CYCLE_SLIP(0) | 459 XCVR_TSM_CTRL_ABORT_ON_FREQ_TARG(0) | 460 XCVR_TSM_CTRL_BKPT(0xFF) , 461 462 .tsm_ovrd2_init = XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD(0) | XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_EN_MASK, 463 .end_of_seq_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(END_OF_RX_WU_26MHZ) | B1(END_OF_TX_WD) | B0(END_OF_TX_WU), 464 .end_of_seq_init_32mhz = B3(END_OF_RX_WD) | B2(END_OF_RX_WU) | B1(END_OF_TX_WD) | B0(END_OF_TX_WU), 465 466 #if !RADIO_IS_GEN_2P1 467 .lpps_ctrl_init = B3(102) | B2(40) | B1(0) | B0(0), 468 #endif /* !RADIO_IS_GEN_2P1 */ 469 470 .tsm_fast_ctrl2_init_26mhz = B3(102 + ADD_FOR_26MHZ) | B2(40 + ADD_FOR_26MHZ) | B1(66) | B0(8), 471 .tsm_fast_ctrl2_init_32mhz = B3(102) | B2(40) | B1(66) | B0(8), 472 473 .pa_ramp_tbl_0_init = XCVR_TSM_PA_RAMP_TBL0_PA_RAMP0(PA_RAMP_0) | XCVR_TSM_PA_RAMP_TBL0_PA_RAMP1(PA_RAMP_1) | 474 XCVR_TSM_PA_RAMP_TBL0_PA_RAMP2(PA_RAMP_2) | XCVR_TSM_PA_RAMP_TBL0_PA_RAMP3(PA_RAMP_3), 475 .pa_ramp_tbl_1_init = XCVR_TSM_PA_RAMP_TBL1_PA_RAMP4(PA_RAMP_4) | XCVR_TSM_PA_RAMP_TBL1_PA_RAMP5(PA_RAMP_5) | 476 XCVR_TSM_PA_RAMP_TBL1_PA_RAMP6(PA_RAMP_6) | XCVR_TSM_PA_RAMP_TBL1_PA_RAMP7(PA_RAMP_7), 477 478 .recycle_count_init_26mhz = B3(0) | B2(0x1C + ADD_FOR_26MHZ) | B1(0x06) | B0(0x66 + ADD_FOR_26MHZ), 479 .recycle_count_init_26mhz = B3(0) | B2(0x1C) | B1(0x06) | B0(0x66), 480 481 .tsm_timing_00_init = B3(END_OF_RX_WD) | B2(0x00) | B1(END_OF_TX_WD) | B0(0x00), /* bb_ldo_hf_en */ 482 .tsm_timing_01_init = B3(END_OF_RX_WD) | B2(0x00) | B1(END_OF_TX_WD) | B0(0x00), /* bb_ldo_adcdac_en */ 483 .tsm_timing_02_init = B3(END_OF_RX_WD) | B2(0x00) | B1(0xFF) | B0(0xFF), /* bb_ldo_bba_en */ 484 .tsm_timing_03_init = B3(END_OF_RX_WD) | B2(0x00) | B1(END_OF_TX_WD) | B0(0x00), /* bb_ldo_pd_en */ 485 .tsm_timing_04_init = B3(END_OF_RX_WD) | B2(0x00) | B1(END_OF_TX_WD) | B0(0x00), /* bb_ldo_fdbk_en */ 486 .tsm_timing_05_init = B3(END_OF_RX_WD) | B2(0x00) | B1(END_OF_TX_WD) | B0(0x00), /* bb_ldo_vcolo_en */ 487 .tsm_timing_06_init = B3(END_OF_RX_WD) | B2(0x00) | B1(END_OF_TX_WD) | B0(0x00), /* bb_ldo_vtref_en */ 488 .tsm_timing_07_init = B3(0x05) | B2(0x00) | B1(0x05) | B0(0x00), /* bb_ldo_fdbk_bleed_en */ 489 .tsm_timing_08_init = B3(0x03) | B2(0x00) | B1(0x03) | B0(0x00), /* bb_ldo_vcolo_bleed_en */ 490 .tsm_timing_09_init = B3(0x03) | B2(0x00) | B1(0x03) | B0(0x00), /* bb_ldo_vcolo_fastcharge_en */ 491 492 .tsm_timing_10_init = B3(END_OF_RX_WD) | B2(0x03 + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x03), /* bb_xtal_pll_ref_clk_en */ 493 .tsm_timing_11_init = B3(0xFF) | B2(0xFF) | B1(END_OF_TX_WD) | B0(0x03), /* bb_xtal_dac_ref_clk_en */ 494 .tsm_timing_12_init = B3(END_OF_RX_WD) | B2(0x03 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_vco_ref_clk_en */ 495 .tsm_timing_13_init = B3(0x18) | B2(0x00) | B1(0x4C) | B0(0x00), /* sy_vco_autotune_en */ 496 .tsm_timing_14_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x31+ADD_FOR_26MHZ) | B1(END_OF_TX_WU + PD_CYCLE_SLIP_TX_LO_ADJ) | B0(0x63 + PD_CYCLE_SLIP_TX_HI_ADJ), /* sy_pd_cycle_slip_ld_ft_en */ 497 .tsm_timing_14_init_32mhz = B3(END_OF_RX_WD) | B2(0x31 + AUX_PLL_DELAY) | B1(END_OF_TX_WU + PD_CYCLE_SLIP_TX_LO_ADJ) | B0(0x63 + PD_CYCLE_SLIP_TX_HI_ADJ), 498 .tsm_timing_15_init = B3(END_OF_RX_WD) | B2(0x03 + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x03), /* sy_vco_en */ 499 .tsm_timing_16_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x1C + ADD_FOR_26MHZ) | B1(0xFF) | B0(0xFF), /* sy_lo_rx_buf_en */ 500 .tsm_timing_16_init_32mhz = B3(END_OF_RX_WD) | B2(0x1C + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), 501 .tsm_timing_17_init = B3(0xFF) | B2(0xFF) | B1(END_OF_TX_WD) | B0(0x55), /* sy_lo_tx_buf_en */ 502 .tsm_timing_18_init = B3(END_OF_RX_WD) | B2(0x05 + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x05), /* sy_divn_en */ 503 .tsm_timing_19_init = B3(0x18+AUX_PLL_DELAY) | B2(0x03 + AUX_PLL_DELAY) | B1(0x4C) | B0(0x03), /* sy_pd_filter_charge_en */ 504 505 .tsm_timing_20_init = B3(END_OF_RX_WD) | B2(0x03 + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x03), /* sy_pd_en */ 506 .tsm_timing_21_init = B3(END_OF_RX_WD) | B2(0x04 + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x04), /* sy_lo_divn_en */ 507 .tsm_timing_22_init = B3(END_OF_RX_WD) | B2(0x04 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* sy_lo_rx_en */ 508 .tsm_timing_23_init = B3(0xFF) | B2(0xFF) | B1(END_OF_TX_WD) | B0(0x04), /*sy_lo_tx_en */ 509 .tsm_timing_24_init = B3(0x18) | B2(0x00) | B1(0x4C) | B0(0x00), /* sy_divn_cal_en */ 510 .tsm_timing_25_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x1D + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_lna_mixer_en */ 511 .tsm_timing_25_init_32mhz = B3(END_OF_RX_WD) | B2(0x1D + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), 512 .tsm_timing_26_init = B3(0xFF) | B2(0xFF) | B1(END_OF_TX_WD) | B0(0x58), /* tx_pa_en */ 513 .tsm_timing_27_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x20 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_adc_i_q_en */ 514 .tsm_timing_27_init_32mhz = B3(END_OF_RX_WD) | B2(0x20 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), 515 .tsm_timing_28_init_26mhz = B3(0x21 + ADD_FOR_26MHZ) | B2(0x20 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_adc_reset_en */ 516 .tsm_timing_28_init_32mhz = B3(0x21 + AUX_PLL_DELAY) | B2(0x20 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), 517 .tsm_timing_29_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x1E + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_bba_i_q_en */ 518 .tsm_timing_29_init_32mhz = B3(END_OF_RX_WD) | B2(0x1E + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), 519 520 .tsm_timing_30_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x20 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_bba_pdet_en */ 521 .tsm_timing_30_init_32mhz = B3(END_OF_RX_WD) | B2(0x20 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), 522 .tsm_timing_31_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x1F + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_bba_tza_dcoc_en */ 523 .tsm_timing_31_init_32mhz = B3(END_OF_RX_WD) | B2(0x1F + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), 524 .tsm_timing_32_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x1D + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_tza_i_q_en */ 525 .tsm_timing_32_init_32mhz = B3(END_OF_RX_WD) | B2(0x1D + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), 526 .tsm_timing_33_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x20 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_tza_pdet_en */ 527 .tsm_timing_33_init_32mhz = B3(END_OF_RX_WD) | B2(0x20 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), 528 .tsm_timing_34_init = B3(END_OF_RX_WD) | B2(0x07 + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x07), /* pll_dig_en */ 529 .tsm_timing_35_init = B3(0xFF) | B2(0xFF) | B1(END_OF_TX_WD), /* tx_dig_en - Byte 0 comes from mode specific settings */ 530 .tsm_timing_36_init_26mhz = B3(END_OF_RX_WD) | B2(0x66 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_dig_en */ 531 .tsm_timing_36_init_32mhz = B3(END_OF_RX_WD) | B2(0x66 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), 532 .tsm_timing_37_init_26mhz = B3(0x67 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B2(0x66 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_init */ 533 .tsm_timing_37_init_32mhz = B3(0x67 + AUX_PLL_DELAY) | B2(0x66 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), 534 .tsm_timing_38_init = B3(END_OF_RX_WD) | B2(0x0E + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x42), /* sigma_delta_en */ 535 .tsm_timing_39_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x66 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_phy_en */ 536 .tsm_timing_39_init_32mhz = B3(END_OF_RX_WD) | B2(0x66 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), 537 538 .tsm_timing_40_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x26 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* dcoc_en */ 539 .tsm_timing_40_init_32mhz = B3(END_OF_RX_WD) | B2(0x26 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), 540 .tsm_timing_41_init_26mhz = B3(0x27 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B2(0x26 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* dcoc_init */ 541 .tsm_timing_41_init_32mhz = B3(0x27 + AUX_PLL_DELAY) | B2(0x26 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), 542 .tsm_timing_51_init = B3(END_OF_RX_WD) | B2(0x03 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_bias_en */ 543 .tsm_timing_52_init_26mhz = B3(0x17 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B2(0x06 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_fcal_en */ 544 .tsm_timing_52_init_32mhz = B3(0x17 + AUX_PLL_DELAY) | B2(0x06 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), 545 .tsm_timing_53_init = B3(END_OF_RX_WD) | B2(0x03 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_lf_pd_en */ 546 .tsm_timing_54_init_26mhz = B3(0x17 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B2(0x03 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_pd_lf_filter_charge_en */ 547 .tsm_timing_54_init_32mhz = B3(0x17 + AUX_PLL_DELAY) | B2(0x03 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), 548 .tsm_timing_55_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x20 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_adc_buf_en */ 549 .tsm_timing_55_init_32mhz = B3(END_OF_RX_WD) | B2(0x20 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), 550 .tsm_timing_56_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x20 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_dig_buf_en */ 551 .tsm_timing_56_init_32mhz = B3(END_OF_RX_WD) | B2(0x20 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), 552 .tsm_timing_57_init = B3(0x1A + AUX_PLL_DELAY) | B2(0x03 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /*rxtx_rccal_en */ 553 .tsm_timing_58_init = B3(0xFF) | B2(0xFF) | B1(END_OF_TX_WD) | B0(0x03), /* tx_hpm_dac_en */ 554 555 /* XCVR_TX_DIG configs */ 556 #define radio_dft_mode 0 557 #define lfsr_length 4 558 #define lfsr_en 0 559 #define dft_clk_sel 4 560 #define tx_dft_en 0 561 #define soc_test_sel 0 562 #define tx_capture_pol 0 563 #define freq_word_adj 0 564 #define lrm 0 565 #define data_padding_pat_1 0x55 566 #define data_padding_pat_0 0xAA 567 #define gfsk_multiply_table_manual 0 568 #define gfsk_mi 1 569 #define gfsk_mld 0 570 #define gfsk_fld 0 571 #define gfsk_mod_index_scaling 0 572 #define tx_image_filter_ovrd_en 0 573 #define tx_image_filter_0_ovrd 0 574 #define tx_image_filter_1_ovrd 0 575 #define tx_image_filter_2_ovrd 0 576 #define gfsk_filter_coeff_manual2 0xC0630401 577 #define gfsk_filter_coeff_manual1 0xBB29960D 578 #define fsk_modulation_scale_0 0x1800 579 #define fsk_modulation_scale_1 0x0800 580 #define dft_mod_patternval 0 581 #define ctune_bist_go 0 582 #define ctune_bist_thrshld 0 583 #define pa_am_mod_freq 0 584 #define pa_am_mod_entries 0 585 #define pa_am_mod_en 0 586 #define syn_bist_go 0 587 #define syn_bist_all_channels 0 588 #define freq_count_threshold 0 589 #define hpm_inl_bist_go 0 590 #define hpm_dnl_bist_go 0 591 #define dft_max_ram_size 0 592 593 .tx_ctrl = XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(radio_dft_mode) | 594 XCVR_TX_DIG_CTRL_LFSR_LENGTH(lfsr_length) | 595 XCVR_TX_DIG_CTRL_LFSR_EN(lfsr_en) | 596 XCVR_TX_DIG_CTRL_DFT_CLK_SEL(dft_clk_sel) | 597 XCVR_TX_DIG_CTRL_TX_DFT_EN(tx_dft_en) | 598 XCVR_TX_DIG_CTRL_SOC_TEST_SEL(soc_test_sel) | 599 XCVR_TX_DIG_CTRL_TX_CAPTURE_POL(tx_capture_pol) | 600 XCVR_TX_DIG_CTRL_FREQ_WORD_ADJ(freq_word_adj), 601 /*-------------------------------------------------------------------------------------------------*/ 602 .tx_data_padding = XCVR_TX_DIG_DATA_PADDING_LRM(lrm) | 603 XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_1(data_padding_pat_1) | 604 XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_0(data_padding_pat_0), 605 /*-------------------------------------------------------------------------------------------------*/ 606 .tx_dft_pattern = XCVR_TX_DIG_DFT_PATTERN_DFT_MOD_PATTERN(dft_mod_patternval), 607 #if !RADIO_IS_GEN_2P1 608 /*-------------------------------------------------------------------------------------------------*/ 609 .rf_dft_bist_1 = XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_GO(ctune_bist_go) | 610 XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_THRSHLD(ctune_bist_thrshld) | 611 XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_FREQ(pa_am_mod_freq) | 612 XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_ENTRIES(pa_am_mod_entries) | 613 XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_EN(pa_am_mod_en), 614 /*-------------------------------------------------------------------------------------------------*/ 615 .rf_dft_bist_2 = XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_GO(syn_bist_go) | 616 XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_ALL_CHANNELS(syn_bist_all_channels) | 617 XCVR_TX_DIG_RF_DFT_BIST_2_FREQ_COUNT_THRESHOLD(freq_count_threshold) | 618 XCVR_TX_DIG_RF_DFT_BIST_2_HPM_INL_BIST_GO(hpm_inl_bist_go) | 619 XCVR_TX_DIG_RF_DFT_BIST_2_HPM_DNL_BIST_GO(hpm_dnl_bist_go) | 620 XCVR_TX_DIG_RF_DFT_BIST_2_DFT_MAX_RAM_SIZE(dft_max_ram_size), 621 #endif /* !RADIO_IS_GEN_2P1 */ 622 }; 623 624
