Searched refs:buffConfig (Results 1 – 4 of 4) sorted by relevance
871 enet_buffer_config_t *buffConfig = bufferConfig; in ENET_CreateHandler() local888 handle->rxBdRing[count].rxBdBase = buffConfig->rxDescStartAddrAlign; in ENET_CreateHandler()890 handle->rxBdRing[count].rxRingLen = buffConfig->rxRingLen; in ENET_CreateHandler()891 handle->rxBdRing[count].rxBuffSizeAlign = buffConfig->rxBuffSizeAlign; in ENET_CreateHandler()893 handle->txBdRing[count].txBdBase = buffConfig->txDescStartAddrAlign; in ENET_CreateHandler()894 handle->txBdRing[count].txRingLen = buffConfig->txRingLen; in ENET_CreateHandler()899 handle->txDirtyRing[count].txDirtyBase = buffConfig->txDirtyStartAddr; in ENET_CreateHandler()900 handle->txDirtyRing[count].txRingLen = buffConfig->txRingLen; in ENET_CreateHandler()904 handle->rxBufferStartAddr[count] = buffConfig->rxBufferStartAddr; in ENET_CreateHandler()921 buffConfig++; in ENET_CreateHandler()
1475 enet_qos_buffer_config_t *buffConfig = bufferConfig; in ENET_QOS_CreateHandler() local1499 handle->txBdRing[count].txBdBase = buffConfig->txDescStartAddrAlign; in ENET_QOS_CreateHandler()1500 handle->txBdRing[count].txRingLen = buffConfig->txRingLen; in ENET_QOS_CreateHandler()1505 handle->txDirtyRing[count].txDirtyBase = buffConfig->txDirtyStartAddr; in ENET_QOS_CreateHandler()1506 handle->txDirtyRing[count].txRingLen = buffConfig->txRingLen; in ENET_QOS_CreateHandler()1516 handle->rxBdRing[count].rxBdBase = buffConfig->rxDescStartAddrAlign; in ENET_QOS_CreateHandler()1518 handle->rxBdRing[count].rxRingLen = buffConfig->rxRingLen; in ENET_QOS_CreateHandler()1519 handle->rxBdRing[count].rxBuffSizeAlign = buffConfig->rxBuffSizeAlign; in ENET_QOS_CreateHandler()1522 handle->rxBufferStartAddr[count] = buffConfig->rxBufferStartAddr; in ENET_QOS_CreateHandler()1525 handle->rxMaintainEnable[count] = buffConfig->rxBuffNeedMaintain; in ENET_QOS_CreateHandler()[all …]
566 …TempTxDescr->buffConfig = (NETC_ETH_IP_TXBD_FRAME_INTERRUPT_MASK | NETC_ETH_IP_TXBD_EXTENDED_BUFFE… in Netc_Eth_Ip_InitTxBD()570 …TempTxDescr->buffConfig = (NETC_ETH_IP_TXBD_FRAME_INTERRUPT_MASK | (NETC_ETH_IP_TXBD_FINAL_MASK & … in Netc_Eth_Ip_InitTxBD()2378 … if (NETC_ETH_IP_TXBD_WRITEBACK_MASK == (txBDR->buffConfig & NETC_ETH_IP_TXBD_WRITEBACK_MASK))3211 txTmpBDR->buffConfig |= NETC_ETH_IP_TXBD_EXTENDED_BUFFER_MASK;3215 … txTmpBDR->buffConfig |= (NETC_ETH_IP_TXBD_FINAL_MASK & (~NETC_ETH_IP_TXBD_WRITEBACK_MASK));3494 … txBD->buffConfig = NETC_ETH_IP_TXBD_FRAME_INTERRUPT_MASK | NETC_ETH_IP_TXBD_EXTENDED_BUFFER_MASK;3497 txBD->buffConfig = NETC_ETH_IP_TXBD_FRAME_INTERRUPT_MASK;3504 … txBD->buffConfig = NETC_ETH_IP_TXBD_FRAME_INTERRUPT_MASK | NETC_ETH_IP_TXBD_EXTENDED_BUFFER_MASK;3508 … txBD->buffConfig = NETC_ETH_IP_TXBD_FRAME_INTERRUPT_MASK | NETC_ETH_IP_TXBD_FINAL_MASK;3517 … txBD->buffConfig |= (((uint32)NETC_ETH_IP_FLQ_VALUE << NETC_ETH_IP_FLQ_SHIFT) | \[all …]
867 uint32 buffConfig; /*!< Buffer descriptor configuration for a normal descriptor. */ member
