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Searched refs:VDCTRL0_CLR (Results 1 – 25 of 49) sorted by relevance

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/hal_nxp-3.6.0/imx/devices/MCIMX6X/
DMCIMX6X_M4.h23926 …__IO uint32_t VDCTRL0_CLR; /**< eLCDIF VSYNC Mode and Dotclk Mode Cont… member
24025 #define LCDIF_VDCTRL0_CLR_REG(base) ((base)->VDCTRL0_CLR)
/hal_nxp-3.6.0/imx/devices/MCIMX7D/
DMCIMX7D_M4.h28067 …__IO uint32_t VDCTRL0_CLR; /**< eLCDIF VSYNC Mode and Dotclk Mode Cont… member
28166 #define LCDIF_VDCTRL0_CLR_REG(base) ((base)->VDCTRL0_CLR)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MCIMX7U3/
DMCIMX7U3_cm4.h9539 …__IO uint32_t VDCTRL0_CLR; /**< LCDIF VSYNC Mode and Dotclk Mode Control Reg… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MCIMX7U5/
DMCIMX7U5_cm4.h9540 …__IO uint32_t VDCTRL0_CLR; /**< LCDIF VSYNC Mode and Dotclk Mode Control Reg… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h28092 …__IO uint32_t VDCTRL0_CLR; /**< LCDIF VSYNC Mode and Dotclk Mode Control Reg… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h27381 …__IO uint32_t VDCTRL0_CLR; /**< LCDIF VSYNC Mode and Dotclk Mode Control Reg… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MN2/
DMIMX8MN2_cm7.h37229 …__IO uint32_t VDCTRL0_CLR; /**< LCDIF VSYNC Mode and Dotclk Mode Control Reg… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MN5/
DMIMX8MN5_cm7.h37231 …__IO uint32_t VDCTRL0_CLR; /**< LCDIF VSYNC Mode and Dotclk Mode Control Reg… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MN3/
DMIMX8MN3_cm7.h37231 …__IO uint32_t VDCTRL0_CLR; /**< LCDIF VSYNC Mode and Dotclk Mode Control Reg… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MN4/
DMIMX8MN4_cm7.h37229 …__IO uint32_t VDCTRL0_CLR; /**< LCDIF VSYNC Mode and Dotclk Mode Control Reg… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MN1/
DMIMX8MN1_cm7.h37231 …__IO uint32_t VDCTRL0_CLR; /**< LCDIF VSYNC Mode and Dotclk Mode Control Reg… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MN6/
DMIMX8MN6_ca53.h37243 …__IO uint32_t VDCTRL0_CLR; /**< LCDIF VSYNC Mode and Dotclk Mode Control Reg… member
DMIMX8MN6_cm7.h37229 …__IO uint32_t VDCTRL0_CLR; /**< LCDIF VSYNC Mode and Dotclk Mode Control Reg… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h29617 …__IO uint32_t VDCTRL0_CLR; /**< LCDIF VSYNC Mode and Dotclk Mode Control Reg… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MQ5/
DMIMX8MQ5_cm4.h36063 …__IO uint32_t VDCTRL0_CLR; /**< LCDIF VSYNC Mode and Dotclk Mode Control Reg… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064.h29612 …__IO uint32_t VDCTRL0_CLR; /**< LCDIF VSYNC Mode and Dotclk Mode Control Reg… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MD6/
DMIMX8MD6_cm4.h36063 …__IO uint32_t VDCTRL0_CLR; /**< LCDIF VSYNC Mode and Dotclk Mode Control Reg… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MD7/
DMIMX8MD7_cm4.h36063 …__IO uint32_t VDCTRL0_CLR; /**< LCDIF VSYNC Mode and Dotclk Mode Control Reg… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MQ7/
DMIMX8MQ7_cm4.h36063 …__IO uint32_t VDCTRL0_CLR; /**< LCDIF VSYNC Mode and Dotclk Mode Control Reg… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MQ6/
DMIMX8MQ6_cm4.h36063 …__IO uint32_t VDCTRL0_CLR; /**< LCDIF VSYNC Mode and Dotclk Mode Control Reg… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MM6/
DMIMX8MM6_ca53.h37941 …__IO uint32_t VDCTRL0_CLR; /**< LCDIF VSYNC Mode and Dotclk Mode Control Reg… member
DMIMX8MM6_cm4.h37932 …__IO uint32_t VDCTRL0_CLR; /**< LCDIF VSYNC Mode and Dotclk Mode Control Reg… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MM5/
DMIMX8MM5_cm4.h37932 …__IO uint32_t VDCTRL0_CLR; /**< LCDIF VSYNC Mode and Dotclk Mode Control Reg… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1166/
DMIMXRT1166_cm4.h55860 …__IO uint32_t VDCTRL0_CLR; /**< LCDIF VSYNC Mode and Dotclk Mode Control Reg… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MM1/
DMIMX8MM1_cm4.h37932 …__IO uint32_t VDCTRL0_CLR; /**< LCDIF VSYNC Mode and Dotclk Mode Control Reg… member

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