| /hal_nxp-3.6.0/mcux/mcux-sdk/drivers/iuart/ |
| D | fsl_uart.h | 276 base->UCR2 &= ~UART_UCR2_SRST_MASK; in UART_SoftwareReset()
277 while ((base->UCR2 & UART_UCR2_SRST_MASK) == 0U) in UART_SoftwareReset()
498 base->UCR2 |= UART_UCR2_TXEN_MASK; in UART_EnableTx()
502 base->UCR2 &= ~UART_UCR2_TXEN_MASK; in UART_EnableTx()
518 base->UCR2 |= UART_UCR2_RXEN_MASK; in UART_EnableRx()
522 base->UCR2 &= ~UART_UCR2_RXEN_MASK; in UART_EnableRx()
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| D | fsl_uart.c | 209 base->UCR2 = UART_UCR2_SRST_MASK; in UART_Init()
222 base->UCR2 |= in UART_Init()
489 base->UCR2 |= (((mask >> 8) << UART_UCR2_ESCI_SHIFT) & UART_UCR2_ESCI_MASK) | in UART_EnableInterrupts()
546 base->UCR2 &= ~((((mask >> 8) << UART_UCR2_ESCI_SHIFT) & UART_UCR2_ESCI_MASK) | in UART_DisableInterrupts()
607 temp |= (((base->UCR2 & UART_UCR2_ESCI_MASK) >> UART_UCR2_ESCI_SHIFT) << 8) | in UART_GetEnabledInterrupts()
608 (((base->UCR2 & UART_UCR2_RTSEN_MASK) >> UART_UCR2_RTSEN_SHIFT) << 9) | in UART_GetEnabledInterrupts()
609 (((base->UCR2 & UART_UCR2_ATEN_MASK) >> UART_UCR2_ATEN_SHIFT) << 10); in UART_GetEnabledInterrupts()
1377 if (((UART_USR1_AGTIM_MASK & base->USR1) != 0U) && ((UART_UCR2_ATEN_MASK & base->UCR2) != 0U)) in UART_TransferHandleIRQ()
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| /hal_nxp-3.6.0/imx/devices/MCIMX6X/ |
| D | MCIMX6X_M4.h | 35080 …__IO uint32_t UCR2; /**< UART Control Register 2, offset: 0x84 … member
35109 #define UART_UCR2_REG(base) ((base)->UCR2)
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| /hal_nxp-3.6.0/imx/devices/MCIMX7D/ |
| D | MCIMX7D_M4.h | 41328 …__IO uint32_t UCR2; /**< UART Control Register 2, offset: 0x84 … member
41357 #define UART_UCR2_REG(base) ((base)->UCR2)
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MN2/ |
| D | MIMX8MN2_cm7.h | 50350 __IO uint32_t UCR2; /**< UART Control Register 2, offset: 0x84 */ member
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MN5/ |
| D | MIMX8MN5_cm7.h | 50352 __IO uint32_t UCR2; /**< UART Control Register 2, offset: 0x84 */ member
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MN3/ |
| D | MIMX8MN3_cm7.h | 50352 __IO uint32_t UCR2; /**< UART Control Register 2, offset: 0x84 */ member
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MN4/ |
| D | MIMX8MN4_cm7.h | 50350 __IO uint32_t UCR2; /**< UART Control Register 2, offset: 0x84 */ member
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MN1/ |
| D | MIMX8MN1_cm7.h | 50352 __IO uint32_t UCR2; /**< UART Control Register 2, offset: 0x84 */ member
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MN6/ |
| D | MIMX8MN6_ca53.h | 50364 __IO uint32_t UCR2; /**< UART Control Register 2, offset: 0x84 */ member
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| D | MIMX8MN6_cm7.h | 50350 __IO uint32_t UCR2; /**< UART Control Register 2, offset: 0x84 */ member
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MQ5/ |
| D | MIMX8MQ5_cm4.h | 53499 __IO uint32_t UCR2; /**< UART Control Register 2, offset: 0x84 */ member
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MD6/ |
| D | MIMX8MD6_cm4.h | 55672 __IO uint32_t UCR2; /**< UART Control Register 2, offset: 0x84 */ member
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MD7/ |
| D | MIMX8MD7_cm4.h | 55672 __IO uint32_t UCR2; /**< UART Control Register 2, offset: 0x84 */ member
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MQ7/ |
| D | MIMX8MQ7_cm4.h | 55672 __IO uint32_t UCR2; /**< UART Control Register 2, offset: 0x84 */ member
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MQ6/ |
| D | MIMX8MQ6_cm4.h | 55672 __IO uint32_t UCR2; /**< UART Control Register 2, offset: 0x84 */ member
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MM6/ |
| D | MIMX8MM6_ca53.h | 68625 __IO uint32_t UCR2; /**< UART Control Register 2, offset: 0x84 */ member
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| D | MIMX8MM6_cm4.h | 69160 __IO uint32_t UCR2; /**< UART Control Register 2, offset: 0x84 */ member
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MM5/ |
| D | MIMX8MM5_cm4.h | 69160 __IO uint32_t UCR2; /**< UART Control Register 2, offset: 0x84 */ member
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MM1/ |
| D | MIMX8MM1_cm4.h | 69160 __IO uint32_t UCR2; /**< UART Control Register 2, offset: 0x84 */ member
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MM2/ |
| D | MIMX8MM2_cm4.h | 69160 __IO uint32_t UCR2; /**< UART Control Register 2, offset: 0x84 */ member
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MM3/ |
| D | MIMX8MM3_cm4.h | 69160 __IO uint32_t UCR2; /**< UART Control Register 2, offset: 0x84 */ member
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MM4/ |
| D | MIMX8MM4_cm4.h | 69160 __IO uint32_t UCR2; /**< UART Control Register 2, offset: 0x84 */ member
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8ML3/ |
| D | MIMX8ML3_cm7.h | 96353 __IO uint32_t UCR2; /**< UART Control Register 2, offset: 0x84 */ member
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8ML4/ |
| D | MIMX8ML4_cm7.h | 96353 __IO uint32_t UCR2; /**< UART Control Register 2, offset: 0x84 */ member
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