1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2023 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_TMR0_BASE.h 10 * @version 2.1 11 * @date 2023-07-20 12 * @brief Peripheral Access Layer for S32Z2_TMR0_BASE 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_TMR0_BASE_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_TMR0_BASE_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- TMR0_BASE Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup TMR0_BASE_Peripheral_Access_Layer TMR0_BASE Peripheral Access Layer 68 * @{ 69 */ 70 71 /** TMR0_BASE - Size of Registers Arrays */ 72 #define TMR0_BASE_TMR_FIPERF_COUNT 3u 73 74 /** TMR0_BASE - Register Layout Typedef */ 75 typedef struct { 76 __I uint32_t TMR_ID; /**< Module ID Register, offset: 0x0 */ 77 uint8_t RESERVED_0[4]; 78 __I uint32_t TMR_CAPR; /**< Timer Capability Register, offset: 0x8 */ 79 uint8_t RESERVED_1[20]; 80 __I uint32_t TMR_FRT_L; /**< Timer free running time low register, offset: 0x20 */ 81 __I uint32_t TMR_FRT_H; /**< Timer free running time high register, offset: 0x24 */ 82 __I uint32_t TMR_SRT_L; /**< Timer synchronous time low register, offset: 0x28 */ 83 __I uint32_t TMR_SRT_H; /**< Timer synchronous time high register., offset: 0x2C */ 84 __I uint32_t TMR_DEF_CNT_L; /**< Default ns timer counter low register, offset: 0x30 */ 85 __I uint32_t TMR_DEF_CNT_H; /**< Default ns timer counter high register, offset: 0x34 */ 86 uint8_t RESERVED_2[72]; 87 __IO uint32_t TMR_CTRL; /**< Timer Control Register, offset: 0x80 */ 88 __IO uint32_t TMR_TEVENT; /**< Timer Event Register, offset: 0x84 */ 89 __IO uint32_t TMR_TEMASK; /**< Timer event mask register, offset: 0x88 */ 90 uint8_t RESERVED_3[8]; 91 __I uint32_t TMR_STAT; /**< Timer status register, offset: 0x94 */ 92 __IO uint32_t TMR_CNT_L; /**< Timer counter low register, offset: 0x98 */ 93 __IO uint32_t TMR_CNT_H; /**< Timer counter high register, offset: 0x9C */ 94 __IO uint32_t TMR_ADD; /**< Timer addend register, offset: 0xA0 */ 95 __I uint32_t TMR_ACC; /**< Timer accumulator register, offset: 0xA4 */ 96 __IO uint32_t TMR_PRSC; /**< Timer prescale register, offset: 0xA8 */ 97 __IO uint32_t TMR_ECTRL; /**< Extended timer control register, offset: 0xAC */ 98 __IO uint32_t TMROFF_L; /**< Timer offset low register, offset: 0xB0 */ 99 __IO uint32_t TMROFF_H; /**< Timer offset high register, offset: 0xB4 */ 100 __IO uint32_t TMR_ALARM1_L; /**< Alarm 1 time comparator low register, offset: 0xB8 */ 101 __IO uint32_t TMR_ALARM1_H; /**< Alarm 1 time comparator high register, offset: 0xBC */ 102 __IO uint32_t TMR_ALARM2_L; /**< Alarm 2 time comparator low register, offset: 0xC0 */ 103 __IO uint32_t TMR_ALARM2_H; /**< Alarm 2 time comparator high register, offset: 0xC4 */ 104 uint8_t RESERVED_4[4]; 105 __IO uint32_t TMR_ALARM_CTRL; /**< Timer Alarm Control Register, offset: 0xCC */ 106 __IO uint32_t TMR_FIPER[TMR0_BASE_TMR_FIPERF_COUNT]; /**< Timer 1 fixed interval period register..Timer 3 fixed interval period register, array offset: 0xD0, array step: 0x4 */ 107 __IO uint32_t TMR_FIPER_CTRL; /**< Timer FIPER Control Register, offset: 0xDC */ 108 __I uint32_t TMR_ETTS1_L; /**< External trigger stamp register, offset: 0xE0 */ 109 __I uint32_t TMR_ETTS1_H; /**< External trigger stamp register, offset: 0xE4 */ 110 __I uint32_t TMR_ETTS2_L; /**< External trigger stamp register, offset: 0xE8 */ 111 __I uint32_t TMR_ETTS2_H; /**< External trigger stamp register, offset: 0xEC */ 112 __I uint32_t TMR_CUR_TIME_L; /**< Timer current time low register, offset: 0xF0 */ 113 __I uint32_t TMR_CUR_TIME_H; /**< Timer current time high register, offset: 0xF4 */ 114 __IO uint32_t TMR_PARAM; /**< Timer parameter register, offset: 0xF8 */ 115 } TMR0_BASE_Type, *TMR0_BASE_MemMapPtr; 116 117 /** Number of instances of the TMR0_BASE module. */ 118 #define TMR0_BASE_INSTANCE_COUNT (1u) 119 120 /* TMR0_BASE - Peripheral instance base addresses */ 121 /** Peripheral NETC__TMR0_BASE base address */ 122 #define IP_NETC__TMR0_BASE_BASE (0x74B40000u) 123 /** Peripheral NETC__TMR0_BASE base pointer */ 124 #define IP_NETC__TMR0_BASE ((TMR0_BASE_Type *)IP_NETC__TMR0_BASE_BASE) 125 /** Array initializer of TMR0_BASE peripheral base addresses */ 126 #define IP_TMR0_BASE_BASE_ADDRS { IP_NETC__TMR0_BASE_BASE } 127 /** Array initializer of TMR0_BASE peripheral base pointers */ 128 #define IP_TMR0_BASE_BASE_PTRS { IP_NETC__TMR0_BASE } 129 130 /* ---------------------------------------------------------------------------- 131 -- TMR0_BASE Register Masks 132 ---------------------------------------------------------------------------- */ 133 134 /*! 135 * @addtogroup TMR0_BASE_Register_Masks TMR0_BASE Register Masks 136 * @{ 137 */ 138 139 /*! @name TMR_ID - Module ID Register */ 140 /*! @{ */ 141 142 #define TMR0_BASE_TMR_ID_REV_MN_MASK (0xFFU) 143 #define TMR0_BASE_TMR_ID_REV_MN_SHIFT (0U) 144 #define TMR0_BASE_TMR_ID_REV_MN_WIDTH (8U) 145 #define TMR0_BASE_TMR_ID_REV_MN(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_ID_REV_MN_SHIFT)) & TMR0_BASE_TMR_ID_REV_MN_MASK) 146 147 #define TMR0_BASE_TMR_ID_REV_MJ_MASK (0xFF00U) 148 #define TMR0_BASE_TMR_ID_REV_MJ_SHIFT (8U) 149 #define TMR0_BASE_TMR_ID_REV_MJ_WIDTH (8U) 150 #define TMR0_BASE_TMR_ID_REV_MJ(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_ID_REV_MJ_SHIFT)) & TMR0_BASE_TMR_ID_REV_MJ_MASK) 151 152 #define TMR0_BASE_TMR_ID_TMR_ID_MASK (0xFFFF0000U) 153 #define TMR0_BASE_TMR_ID_TMR_ID_SHIFT (16U) 154 #define TMR0_BASE_TMR_ID_TMR_ID_WIDTH (16U) 155 #define TMR0_BASE_TMR_ID_TMR_ID(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_ID_TMR_ID_SHIFT)) & TMR0_BASE_TMR_ID_TMR_ID_MASK) 156 /*! @} */ 157 158 /*! @name TMR_CAPR - Timer Capability Register */ 159 /*! @{ */ 160 161 #define TMR0_BASE_TMR_CAPR_IEEE_1722_MASK (0x1U) 162 #define TMR0_BASE_TMR_CAPR_IEEE_1722_SHIFT (0U) 163 #define TMR0_BASE_TMR_CAPR_IEEE_1722_WIDTH (1U) 164 #define TMR0_BASE_TMR_CAPR_IEEE_1722(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_CAPR_IEEE_1722_SHIFT)) & TMR0_BASE_TMR_CAPR_IEEE_1722_MASK) 165 166 #define TMR0_BASE_TMR_CAPR_ECADJ_MASK (0x2U) 167 #define TMR0_BASE_TMR_CAPR_ECADJ_SHIFT (1U) 168 #define TMR0_BASE_TMR_CAPR_ECADJ_WIDTH (1U) 169 #define TMR0_BASE_TMR_CAPR_ECADJ(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_CAPR_ECADJ_SHIFT)) & TMR0_BASE_TMR_CAPR_ECADJ_MASK) 170 171 #define TMR0_BASE_TMR_CAPR_IEEE_8021AS_REV_MASK (0x4U) 172 #define TMR0_BASE_TMR_CAPR_IEEE_8021AS_REV_SHIFT (2U) 173 #define TMR0_BASE_TMR_CAPR_IEEE_8021AS_REV_WIDTH (1U) 174 #define TMR0_BASE_TMR_CAPR_IEEE_8021AS_REV(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_CAPR_IEEE_8021AS_REV_SHIFT)) & TMR0_BASE_TMR_CAPR_IEEE_8021AS_REV_MASK) 175 176 #define TMR0_BASE_TMR_CAPR_NUM_MSIX_MASK (0x10000U) 177 #define TMR0_BASE_TMR_CAPR_NUM_MSIX_SHIFT (16U) 178 #define TMR0_BASE_TMR_CAPR_NUM_MSIX_WIDTH (1U) 179 #define TMR0_BASE_TMR_CAPR_NUM_MSIX(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_CAPR_NUM_MSIX_SHIFT)) & TMR0_BASE_TMR_CAPR_NUM_MSIX_MASK) 180 /*! @} */ 181 182 /*! @name TMR_FRT_L - Timer free running time low register */ 183 /*! @{ */ 184 185 #define TMR0_BASE_TMR_FRT_L_TMR_FRT_L_MASK (0xFFFFFFFFU) 186 #define TMR0_BASE_TMR_FRT_L_TMR_FRT_L_SHIFT (0U) 187 #define TMR0_BASE_TMR_FRT_L_TMR_FRT_L_WIDTH (32U) 188 #define TMR0_BASE_TMR_FRT_L_TMR_FRT_L(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_FRT_L_TMR_FRT_L_SHIFT)) & TMR0_BASE_TMR_FRT_L_TMR_FRT_L_MASK) 189 /*! @} */ 190 191 /*! @name TMR_FRT_H - Timer free running time high register */ 192 /*! @{ */ 193 194 #define TMR0_BASE_TMR_FRT_H_TMR_FRT_H_MASK (0xFFFFFFFFU) 195 #define TMR0_BASE_TMR_FRT_H_TMR_FRT_H_SHIFT (0U) 196 #define TMR0_BASE_TMR_FRT_H_TMR_FRT_H_WIDTH (32U) 197 #define TMR0_BASE_TMR_FRT_H_TMR_FRT_H(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_FRT_H_TMR_FRT_H_SHIFT)) & TMR0_BASE_TMR_FRT_H_TMR_FRT_H_MASK) 198 /*! @} */ 199 200 /*! @name TMR_SRT_L - Timer synchronous time low register */ 201 /*! @{ */ 202 203 #define TMR0_BASE_TMR_SRT_L_TMR_SRT_L_MASK (0xFFFFFFFFU) 204 #define TMR0_BASE_TMR_SRT_L_TMR_SRT_L_SHIFT (0U) 205 #define TMR0_BASE_TMR_SRT_L_TMR_SRT_L_WIDTH (32U) 206 #define TMR0_BASE_TMR_SRT_L_TMR_SRT_L(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_SRT_L_TMR_SRT_L_SHIFT)) & TMR0_BASE_TMR_SRT_L_TMR_SRT_L_MASK) 207 /*! @} */ 208 209 /*! @name TMR_SRT_H - Timer synchronous time high register. */ 210 /*! @{ */ 211 212 #define TMR0_BASE_TMR_SRT_H_TMR_SRT_H_MASK (0xFFFFFFFFU) 213 #define TMR0_BASE_TMR_SRT_H_TMR_SRT_H_SHIFT (0U) 214 #define TMR0_BASE_TMR_SRT_H_TMR_SRT_H_WIDTH (32U) 215 #define TMR0_BASE_TMR_SRT_H_TMR_SRT_H(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_SRT_H_TMR_SRT_H_SHIFT)) & TMR0_BASE_TMR_SRT_H_TMR_SRT_H_MASK) 216 /*! @} */ 217 218 /*! @name TMR_DEF_CNT_L - Default ns timer counter low register */ 219 /*! @{ */ 220 221 #define TMR0_BASE_TMR_DEF_CNT_L_TMR_DEF_CNT_L_MASK (0xFFFFFFFFU) 222 #define TMR0_BASE_TMR_DEF_CNT_L_TMR_DEF_CNT_L_SHIFT (0U) 223 #define TMR0_BASE_TMR_DEF_CNT_L_TMR_DEF_CNT_L_WIDTH (32U) 224 #define TMR0_BASE_TMR_DEF_CNT_L_TMR_DEF_CNT_L(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_DEF_CNT_L_TMR_DEF_CNT_L_SHIFT)) & TMR0_BASE_TMR_DEF_CNT_L_TMR_DEF_CNT_L_MASK) 225 /*! @} */ 226 227 /*! @name TMR_DEF_CNT_H - Default ns timer counter high register */ 228 /*! @{ */ 229 230 #define TMR0_BASE_TMR_DEF_CNT_H_TMR_DEF_CNT_H_MASK (0xFFFFFFFFU) 231 #define TMR0_BASE_TMR_DEF_CNT_H_TMR_DEF_CNT_H_SHIFT (0U) 232 #define TMR0_BASE_TMR_DEF_CNT_H_TMR_DEF_CNT_H_WIDTH (32U) 233 #define TMR0_BASE_TMR_DEF_CNT_H_TMR_DEF_CNT_H(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_DEF_CNT_H_TMR_DEF_CNT_H_SHIFT)) & TMR0_BASE_TMR_DEF_CNT_H_TMR_DEF_CNT_H_MASK) 234 /*! @} */ 235 236 /*! @name TMR_CTRL - Timer Control Register */ 237 /*! @{ */ 238 239 #define TMR0_BASE_TMR_CTRL_CK_SEL_MASK (0x3U) 240 #define TMR0_BASE_TMR_CTRL_CK_SEL_SHIFT (0U) 241 #define TMR0_BASE_TMR_CTRL_CK_SEL_WIDTH (2U) 242 #define TMR0_BASE_TMR_CTRL_CK_SEL(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_CTRL_CK_SEL_SHIFT)) & TMR0_BASE_TMR_CTRL_CK_SEL_MASK) 243 244 #define TMR0_BASE_TMR_CTRL_TE_MASK (0x4U) 245 #define TMR0_BASE_TMR_CTRL_TE_SHIFT (2U) 246 #define TMR0_BASE_TMR_CTRL_TE_WIDTH (1U) 247 #define TMR0_BASE_TMR_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_CTRL_TE_SHIFT)) & TMR0_BASE_TMR_CTRL_TE_MASK) 248 249 #define TMR0_BASE_TMR_CTRL_CIPH_MASK (0x40U) 250 #define TMR0_BASE_TMR_CTRL_CIPH_SHIFT (6U) 251 #define TMR0_BASE_TMR_CTRL_CIPH_WIDTH (1U) 252 #define TMR0_BASE_TMR_CTRL_CIPH(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_CTRL_CIPH_SHIFT)) & TMR0_BASE_TMR_CTRL_CIPH_MASK) 253 254 #define TMR0_BASE_TMR_CTRL_COPH_MASK (0x80U) 255 #define TMR0_BASE_TMR_CTRL_COPH_SHIFT (7U) 256 #define TMR0_BASE_TMR_CTRL_COPH_WIDTH (1U) 257 #define TMR0_BASE_TMR_CTRL_COPH(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_CTRL_COPH_SHIFT)) & TMR0_BASE_TMR_CTRL_COPH_MASK) 258 259 #define TMR0_BASE_TMR_CTRL_ETEP1_MASK (0x100U) 260 #define TMR0_BASE_TMR_CTRL_ETEP1_SHIFT (8U) 261 #define TMR0_BASE_TMR_CTRL_ETEP1_WIDTH (1U) 262 #define TMR0_BASE_TMR_CTRL_ETEP1(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_CTRL_ETEP1_SHIFT)) & TMR0_BASE_TMR_CTRL_ETEP1_MASK) 263 264 #define TMR0_BASE_TMR_CTRL_ETEP2_MASK (0x200U) 265 #define TMR0_BASE_TMR_CTRL_ETEP2_SHIFT (9U) 266 #define TMR0_BASE_TMR_CTRL_ETEP2_WIDTH (1U) 267 #define TMR0_BASE_TMR_CTRL_ETEP2(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_CTRL_ETEP2_SHIFT)) & TMR0_BASE_TMR_CTRL_ETEP2_MASK) 268 269 #define TMR0_BASE_TMR_CTRL_TCLK_PERIOD_MASK (0x3FF0000U) 270 #define TMR0_BASE_TMR_CTRL_TCLK_PERIOD_SHIFT (16U) 271 #define TMR0_BASE_TMR_CTRL_TCLK_PERIOD_WIDTH (10U) 272 #define TMR0_BASE_TMR_CTRL_TCLK_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_CTRL_TCLK_PERIOD_SHIFT)) & TMR0_BASE_TMR_CTRL_TCLK_PERIOD_MASK) 273 274 #define TMR0_BASE_TMR_CTRL_PP2L_MASK (0x4000000U) 275 #define TMR0_BASE_TMR_CTRL_PP2L_SHIFT (26U) 276 #define TMR0_BASE_TMR_CTRL_PP2L_WIDTH (1U) 277 #define TMR0_BASE_TMR_CTRL_PP2L(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_CTRL_PP2L_SHIFT)) & TMR0_BASE_TMR_CTRL_PP2L_MASK) 278 279 #define TMR0_BASE_TMR_CTRL_PP1L_MASK (0x8000000U) 280 #define TMR0_BASE_TMR_CTRL_PP1L_SHIFT (27U) 281 #define TMR0_BASE_TMR_CTRL_PP1L_WIDTH (1U) 282 #define TMR0_BASE_TMR_CTRL_PP1L(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_CTRL_PP1L_SHIFT)) & TMR0_BASE_TMR_CTRL_PP1L_MASK) 283 284 #define TMR0_BASE_TMR_CTRL_FS_MASK (0x10000000U) 285 #define TMR0_BASE_TMR_CTRL_FS_SHIFT (28U) 286 #define TMR0_BASE_TMR_CTRL_FS_WIDTH (1U) 287 #define TMR0_BASE_TMR_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_CTRL_FS_SHIFT)) & TMR0_BASE_TMR_CTRL_FS_MASK) 288 289 #define TMR0_BASE_TMR_CTRL_ALM2P_MASK (0x40000000U) 290 #define TMR0_BASE_TMR_CTRL_ALM2P_SHIFT (30U) 291 #define TMR0_BASE_TMR_CTRL_ALM2P_WIDTH (1U) 292 #define TMR0_BASE_TMR_CTRL_ALM2P(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_CTRL_ALM2P_SHIFT)) & TMR0_BASE_TMR_CTRL_ALM2P_MASK) 293 294 #define TMR0_BASE_TMR_CTRL_ALM1P_MASK (0x80000000U) 295 #define TMR0_BASE_TMR_CTRL_ALM1P_SHIFT (31U) 296 #define TMR0_BASE_TMR_CTRL_ALM1P_WIDTH (1U) 297 #define TMR0_BASE_TMR_CTRL_ALM1P(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_CTRL_ALM1P_SHIFT)) & TMR0_BASE_TMR_CTRL_ALM1P_MASK) 298 /*! @} */ 299 300 /*! @name TMR_TEVENT - Timer Event Register */ 301 /*! @{ */ 302 303 #define TMR0_BASE_TMR_TEVENT_PP3EN_MASK (0x20U) 304 #define TMR0_BASE_TMR_TEVENT_PP3EN_SHIFT (5U) 305 #define TMR0_BASE_TMR_TEVENT_PP3EN_WIDTH (1U) 306 #define TMR0_BASE_TMR_TEVENT_PP3EN(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_TEVENT_PP3EN_SHIFT)) & TMR0_BASE_TMR_TEVENT_PP3EN_MASK) 307 308 #define TMR0_BASE_TMR_TEVENT_PP2EN_MASK (0x40U) 309 #define TMR0_BASE_TMR_TEVENT_PP2EN_SHIFT (6U) 310 #define TMR0_BASE_TMR_TEVENT_PP2EN_WIDTH (1U) 311 #define TMR0_BASE_TMR_TEVENT_PP2EN(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_TEVENT_PP2EN_SHIFT)) & TMR0_BASE_TMR_TEVENT_PP2EN_MASK) 312 313 #define TMR0_BASE_TMR_TEVENT_PP1EN_MASK (0x80U) 314 #define TMR0_BASE_TMR_TEVENT_PP1EN_SHIFT (7U) 315 #define TMR0_BASE_TMR_TEVENT_PP1EN_WIDTH (1U) 316 #define TMR0_BASE_TMR_TEVENT_PP1EN(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_TEVENT_PP1EN_SHIFT)) & TMR0_BASE_TMR_TEVENT_PP1EN_MASK) 317 318 #define TMR0_BASE_TMR_TEVENT_ALM1EN_MASK (0x10000U) 319 #define TMR0_BASE_TMR_TEVENT_ALM1EN_SHIFT (16U) 320 #define TMR0_BASE_TMR_TEVENT_ALM1EN_WIDTH (1U) 321 #define TMR0_BASE_TMR_TEVENT_ALM1EN(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_TEVENT_ALM1EN_SHIFT)) & TMR0_BASE_TMR_TEVENT_ALM1EN_MASK) 322 323 #define TMR0_BASE_TMR_TEVENT_ALM2EN_MASK (0x20000U) 324 #define TMR0_BASE_TMR_TEVENT_ALM2EN_SHIFT (17U) 325 #define TMR0_BASE_TMR_TEVENT_ALM2EN_WIDTH (1U) 326 #define TMR0_BASE_TMR_TEVENT_ALM2EN(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_TEVENT_ALM2EN_SHIFT)) & TMR0_BASE_TMR_TEVENT_ALM2EN_MASK) 327 328 #define TMR0_BASE_TMR_TEVENT_ETS1_THREN_MASK (0x100000U) 329 #define TMR0_BASE_TMR_TEVENT_ETS1_THREN_SHIFT (20U) 330 #define TMR0_BASE_TMR_TEVENT_ETS1_THREN_WIDTH (1U) 331 #define TMR0_BASE_TMR_TEVENT_ETS1_THREN(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_TEVENT_ETS1_THREN_SHIFT)) & TMR0_BASE_TMR_TEVENT_ETS1_THREN_MASK) 332 333 #define TMR0_BASE_TMR_TEVENT_ETS2_THREN_MASK (0x200000U) 334 #define TMR0_BASE_TMR_TEVENT_ETS2_THREN_SHIFT (21U) 335 #define TMR0_BASE_TMR_TEVENT_ETS2_THREN_WIDTH (1U) 336 #define TMR0_BASE_TMR_TEVENT_ETS2_THREN(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_TEVENT_ETS2_THREN_SHIFT)) & TMR0_BASE_TMR_TEVENT_ETS2_THREN_MASK) 337 338 #define TMR0_BASE_TMR_TEVENT_ETS1EN_MASK (0x1000000U) 339 #define TMR0_BASE_TMR_TEVENT_ETS1EN_SHIFT (24U) 340 #define TMR0_BASE_TMR_TEVENT_ETS1EN_WIDTH (1U) 341 #define TMR0_BASE_TMR_TEVENT_ETS1EN(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_TEVENT_ETS1EN_SHIFT)) & TMR0_BASE_TMR_TEVENT_ETS1EN_MASK) 342 343 #define TMR0_BASE_TMR_TEVENT_ETS2EN_MASK (0x2000000U) 344 #define TMR0_BASE_TMR_TEVENT_ETS2EN_SHIFT (25U) 345 #define TMR0_BASE_TMR_TEVENT_ETS2EN_WIDTH (1U) 346 #define TMR0_BASE_TMR_TEVENT_ETS2EN(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_TEVENT_ETS2EN_SHIFT)) & TMR0_BASE_TMR_TEVENT_ETS2EN_MASK) 347 348 #define TMR0_BASE_TMR_TEVENT_ETS1_OVEN_MASK (0x10000000U) 349 #define TMR0_BASE_TMR_TEVENT_ETS1_OVEN_SHIFT (28U) 350 #define TMR0_BASE_TMR_TEVENT_ETS1_OVEN_WIDTH (1U) 351 #define TMR0_BASE_TMR_TEVENT_ETS1_OVEN(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_TEVENT_ETS1_OVEN_SHIFT)) & TMR0_BASE_TMR_TEVENT_ETS1_OVEN_MASK) 352 353 #define TMR0_BASE_TMR_TEVENT_ETS2_OVEN_MASK (0x20000000U) 354 #define TMR0_BASE_TMR_TEVENT_ETS2_OVEN_SHIFT (29U) 355 #define TMR0_BASE_TMR_TEVENT_ETS2_OVEN_WIDTH (1U) 356 #define TMR0_BASE_TMR_TEVENT_ETS2_OVEN(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_TEVENT_ETS2_OVEN_SHIFT)) & TMR0_BASE_TMR_TEVENT_ETS2_OVEN_MASK) 357 /*! @} */ 358 359 /*! @name TMR_TEMASK - Timer event mask register */ 360 /*! @{ */ 361 362 #define TMR0_BASE_TMR_TEMASK_PP3EN_MASK (0x20U) 363 #define TMR0_BASE_TMR_TEMASK_PP3EN_SHIFT (5U) 364 #define TMR0_BASE_TMR_TEMASK_PP3EN_WIDTH (1U) 365 #define TMR0_BASE_TMR_TEMASK_PP3EN(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_TEMASK_PP3EN_SHIFT)) & TMR0_BASE_TMR_TEMASK_PP3EN_MASK) 366 367 #define TMR0_BASE_TMR_TEMASK_PP2EN_MASK (0x40U) 368 #define TMR0_BASE_TMR_TEMASK_PP2EN_SHIFT (6U) 369 #define TMR0_BASE_TMR_TEMASK_PP2EN_WIDTH (1U) 370 #define TMR0_BASE_TMR_TEMASK_PP2EN(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_TEMASK_PP2EN_SHIFT)) & TMR0_BASE_TMR_TEMASK_PP2EN_MASK) 371 372 #define TMR0_BASE_TMR_TEMASK_PP1EN_MASK (0x80U) 373 #define TMR0_BASE_TMR_TEMASK_PP1EN_SHIFT (7U) 374 #define TMR0_BASE_TMR_TEMASK_PP1EN_WIDTH (1U) 375 #define TMR0_BASE_TMR_TEMASK_PP1EN(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_TEMASK_PP1EN_SHIFT)) & TMR0_BASE_TMR_TEMASK_PP1EN_MASK) 376 377 #define TMR0_BASE_TMR_TEMASK_ALM1EN_MASK (0x10000U) 378 #define TMR0_BASE_TMR_TEMASK_ALM1EN_SHIFT (16U) 379 #define TMR0_BASE_TMR_TEMASK_ALM1EN_WIDTH (1U) 380 #define TMR0_BASE_TMR_TEMASK_ALM1EN(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_TEMASK_ALM1EN_SHIFT)) & TMR0_BASE_TMR_TEMASK_ALM1EN_MASK) 381 382 #define TMR0_BASE_TMR_TEMASK_ALM2EN_MASK (0x20000U) 383 #define TMR0_BASE_TMR_TEMASK_ALM2EN_SHIFT (17U) 384 #define TMR0_BASE_TMR_TEMASK_ALM2EN_WIDTH (1U) 385 #define TMR0_BASE_TMR_TEMASK_ALM2EN(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_TEMASK_ALM2EN_SHIFT)) & TMR0_BASE_TMR_TEMASK_ALM2EN_MASK) 386 387 #define TMR0_BASE_TMR_TEMASK_ETS1_THREN_MASK (0x100000U) 388 #define TMR0_BASE_TMR_TEMASK_ETS1_THREN_SHIFT (20U) 389 #define TMR0_BASE_TMR_TEMASK_ETS1_THREN_WIDTH (1U) 390 #define TMR0_BASE_TMR_TEMASK_ETS1_THREN(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_TEMASK_ETS1_THREN_SHIFT)) & TMR0_BASE_TMR_TEMASK_ETS1_THREN_MASK) 391 392 #define TMR0_BASE_TMR_TEMASK_ETS2_THREN_MASK (0x200000U) 393 #define TMR0_BASE_TMR_TEMASK_ETS2_THREN_SHIFT (21U) 394 #define TMR0_BASE_TMR_TEMASK_ETS2_THREN_WIDTH (1U) 395 #define TMR0_BASE_TMR_TEMASK_ETS2_THREN(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_TEMASK_ETS2_THREN_SHIFT)) & TMR0_BASE_TMR_TEMASK_ETS2_THREN_MASK) 396 397 #define TMR0_BASE_TMR_TEMASK_ETS1EN_MASK (0x1000000U) 398 #define TMR0_BASE_TMR_TEMASK_ETS1EN_SHIFT (24U) 399 #define TMR0_BASE_TMR_TEMASK_ETS1EN_WIDTH (1U) 400 #define TMR0_BASE_TMR_TEMASK_ETS1EN(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_TEMASK_ETS1EN_SHIFT)) & TMR0_BASE_TMR_TEMASK_ETS1EN_MASK) 401 402 #define TMR0_BASE_TMR_TEMASK_ETS2EN_MASK (0x2000000U) 403 #define TMR0_BASE_TMR_TEMASK_ETS2EN_SHIFT (25U) 404 #define TMR0_BASE_TMR_TEMASK_ETS2EN_WIDTH (1U) 405 #define TMR0_BASE_TMR_TEMASK_ETS2EN(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_TEMASK_ETS2EN_SHIFT)) & TMR0_BASE_TMR_TEMASK_ETS2EN_MASK) 406 407 #define TMR0_BASE_TMR_TEMASK_ETS1_OVEN_MASK (0x10000000U) 408 #define TMR0_BASE_TMR_TEMASK_ETS1_OVEN_SHIFT (28U) 409 #define TMR0_BASE_TMR_TEMASK_ETS1_OVEN_WIDTH (1U) 410 #define TMR0_BASE_TMR_TEMASK_ETS1_OVEN(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_TEMASK_ETS1_OVEN_SHIFT)) & TMR0_BASE_TMR_TEMASK_ETS1_OVEN_MASK) 411 412 #define TMR0_BASE_TMR_TEMASK_ETS2_OVEN_MASK (0x20000000U) 413 #define TMR0_BASE_TMR_TEMASK_ETS2_OVEN_SHIFT (29U) 414 #define TMR0_BASE_TMR_TEMASK_ETS2_OVEN_WIDTH (1U) 415 #define TMR0_BASE_TMR_TEMASK_ETS2_OVEN(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_TEMASK_ETS2_OVEN_SHIFT)) & TMR0_BASE_TMR_TEMASK_ETS2_OVEN_MASK) 416 /*! @} */ 417 418 /*! @name TMR_STAT - Timer status register */ 419 /*! @{ */ 420 421 #define TMR0_BASE_TMR_STAT_ETS1_VLD_MASK (0x1000000U) 422 #define TMR0_BASE_TMR_STAT_ETS1_VLD_SHIFT (24U) 423 #define TMR0_BASE_TMR_STAT_ETS1_VLD_WIDTH (1U) 424 #define TMR0_BASE_TMR_STAT_ETS1_VLD(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_STAT_ETS1_VLD_SHIFT)) & TMR0_BASE_TMR_STAT_ETS1_VLD_MASK) 425 426 #define TMR0_BASE_TMR_STAT_ETS2_VLD_MASK (0x2000000U) 427 #define TMR0_BASE_TMR_STAT_ETS2_VLD_SHIFT (25U) 428 #define TMR0_BASE_TMR_STAT_ETS2_VLD_WIDTH (1U) 429 #define TMR0_BASE_TMR_STAT_ETS2_VLD(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_STAT_ETS2_VLD_SHIFT)) & TMR0_BASE_TMR_STAT_ETS2_VLD_MASK) 430 431 #define TMR0_BASE_TMR_STAT_RCD_MASK (0x80000000U) 432 #define TMR0_BASE_TMR_STAT_RCD_SHIFT (31U) 433 #define TMR0_BASE_TMR_STAT_RCD_WIDTH (1U) 434 #define TMR0_BASE_TMR_STAT_RCD(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_STAT_RCD_SHIFT)) & TMR0_BASE_TMR_STAT_RCD_MASK) 435 /*! @} */ 436 437 /*! @name TMR_CNT_L - Timer counter low register */ 438 /*! @{ */ 439 440 #define TMR0_BASE_TMR_CNT_L_TMR_CNT_L_MASK (0xFFFFFFFFU) 441 #define TMR0_BASE_TMR_CNT_L_TMR_CNT_L_SHIFT (0U) 442 #define TMR0_BASE_TMR_CNT_L_TMR_CNT_L_WIDTH (32U) 443 #define TMR0_BASE_TMR_CNT_L_TMR_CNT_L(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_CNT_L_TMR_CNT_L_SHIFT)) & TMR0_BASE_TMR_CNT_L_TMR_CNT_L_MASK) 444 /*! @} */ 445 446 /*! @name TMR_CNT_H - Timer counter high register */ 447 /*! @{ */ 448 449 #define TMR0_BASE_TMR_CNT_H_TMR_CNT_H_MASK (0xFFFFFFFFU) 450 #define TMR0_BASE_TMR_CNT_H_TMR_CNT_H_SHIFT (0U) 451 #define TMR0_BASE_TMR_CNT_H_TMR_CNT_H_WIDTH (32U) 452 #define TMR0_BASE_TMR_CNT_H_TMR_CNT_H(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_CNT_H_TMR_CNT_H_SHIFT)) & TMR0_BASE_TMR_CNT_H_TMR_CNT_H_MASK) 453 /*! @} */ 454 455 /*! @name TMR_ADD - Timer addend register */ 456 /*! @{ */ 457 458 #define TMR0_BASE_TMR_ADD_ADDEND_MASK (0xFFFFFFFFU) 459 #define TMR0_BASE_TMR_ADD_ADDEND_SHIFT (0U) 460 #define TMR0_BASE_TMR_ADD_ADDEND_WIDTH (32U) 461 #define TMR0_BASE_TMR_ADD_ADDEND(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_ADD_ADDEND_SHIFT)) & TMR0_BASE_TMR_ADD_ADDEND_MASK) 462 /*! @} */ 463 464 /*! @name TMR_ACC - Timer accumulator register */ 465 /*! @{ */ 466 467 #define TMR0_BASE_TMR_ACC_TMR_ACC_MASK (0xFFFFFFFFU) 468 #define TMR0_BASE_TMR_ACC_TMR_ACC_SHIFT (0U) 469 #define TMR0_BASE_TMR_ACC_TMR_ACC_WIDTH (32U) 470 #define TMR0_BASE_TMR_ACC_TMR_ACC(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_ACC_TMR_ACC_SHIFT)) & TMR0_BASE_TMR_ACC_TMR_ACC_MASK) 471 /*! @} */ 472 473 /*! @name TMR_PRSC - Timer prescale register */ 474 /*! @{ */ 475 476 #define TMR0_BASE_TMR_PRSC_PRSC_OCK_MASK (0xFFFFU) 477 #define TMR0_BASE_TMR_PRSC_PRSC_OCK_SHIFT (0U) 478 #define TMR0_BASE_TMR_PRSC_PRSC_OCK_WIDTH (16U) 479 #define TMR0_BASE_TMR_PRSC_PRSC_OCK(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_PRSC_PRSC_OCK_SHIFT)) & TMR0_BASE_TMR_PRSC_PRSC_OCK_MASK) 480 /*! @} */ 481 482 /*! @name TMR_ECTRL - Extended timer control register */ 483 /*! @{ */ 484 485 #define TMR0_BASE_TMR_ECTRL_ETFF_THR_MASK (0xFU) 486 #define TMR0_BASE_TMR_ECTRL_ETFF_THR_SHIFT (0U) 487 #define TMR0_BASE_TMR_ECTRL_ETFF_THR_WIDTH (4U) 488 #define TMR0_BASE_TMR_ECTRL_ETFF_THR(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_ECTRL_ETFF_THR_SHIFT)) & TMR0_BASE_TMR_ECTRL_ETFF_THR_MASK) 489 /*! @} */ 490 491 /*! @name TMROFF_L - Timer offset low register */ 492 /*! @{ */ 493 494 #define TMR0_BASE_TMROFF_L_TMROFF_L_MASK (0xFFFFFFFFU) 495 #define TMR0_BASE_TMROFF_L_TMROFF_L_SHIFT (0U) 496 #define TMR0_BASE_TMROFF_L_TMROFF_L_WIDTH (32U) 497 #define TMR0_BASE_TMROFF_L_TMROFF_L(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMROFF_L_TMROFF_L_SHIFT)) & TMR0_BASE_TMROFF_L_TMROFF_L_MASK) 498 /*! @} */ 499 500 /*! @name TMROFF_H - Timer offset high register */ 501 /*! @{ */ 502 503 #define TMR0_BASE_TMROFF_H_TMROFF_H_MASK (0xFFFFFFFFU) 504 #define TMR0_BASE_TMROFF_H_TMROFF_H_SHIFT (0U) 505 #define TMR0_BASE_TMROFF_H_TMROFF_H_WIDTH (32U) 506 #define TMR0_BASE_TMROFF_H_TMROFF_H(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMROFF_H_TMROFF_H_SHIFT)) & TMR0_BASE_TMROFF_H_TMROFF_H_MASK) 507 /*! @} */ 508 509 /*! @name TMR_ALARM1_L - Alarm 1 time comparator low register */ 510 /*! @{ */ 511 512 #define TMR0_BASE_TMR_ALARM1_L_ALARM_L_MASK (0xFFFFFFFFU) 513 #define TMR0_BASE_TMR_ALARM1_L_ALARM_L_SHIFT (0U) 514 #define TMR0_BASE_TMR_ALARM1_L_ALARM_L_WIDTH (32U) 515 #define TMR0_BASE_TMR_ALARM1_L_ALARM_L(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_ALARM1_L_ALARM_L_SHIFT)) & TMR0_BASE_TMR_ALARM1_L_ALARM_L_MASK) 516 /*! @} */ 517 518 /*! @name TMR_ALARM1_H - Alarm 1 time comparator high register */ 519 /*! @{ */ 520 521 #define TMR0_BASE_TMR_ALARM1_H_ALARM_H_MASK (0xFFFFFFFFU) 522 #define TMR0_BASE_TMR_ALARM1_H_ALARM_H_SHIFT (0U) 523 #define TMR0_BASE_TMR_ALARM1_H_ALARM_H_WIDTH (32U) 524 #define TMR0_BASE_TMR_ALARM1_H_ALARM_H(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_ALARM1_H_ALARM_H_SHIFT)) & TMR0_BASE_TMR_ALARM1_H_ALARM_H_MASK) 525 /*! @} */ 526 527 /*! @name TMR_ALARM2_L - Alarm 2 time comparator low register */ 528 /*! @{ */ 529 530 #define TMR0_BASE_TMR_ALARM2_L_ALARM_L_MASK (0xFFFFFFFFU) 531 #define TMR0_BASE_TMR_ALARM2_L_ALARM_L_SHIFT (0U) 532 #define TMR0_BASE_TMR_ALARM2_L_ALARM_L_WIDTH (32U) 533 #define TMR0_BASE_TMR_ALARM2_L_ALARM_L(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_ALARM2_L_ALARM_L_SHIFT)) & TMR0_BASE_TMR_ALARM2_L_ALARM_L_MASK) 534 /*! @} */ 535 536 /*! @name TMR_ALARM2_H - Alarm 2 time comparator high register */ 537 /*! @{ */ 538 539 #define TMR0_BASE_TMR_ALARM2_H_ALARM_H_MASK (0xFFFFFFFFU) 540 #define TMR0_BASE_TMR_ALARM2_H_ALARM_H_SHIFT (0U) 541 #define TMR0_BASE_TMR_ALARM2_H_ALARM_H_WIDTH (32U) 542 #define TMR0_BASE_TMR_ALARM2_H_ALARM_H(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_ALARM2_H_ALARM_H_SHIFT)) & TMR0_BASE_TMR_ALARM2_H_ALARM_H_MASK) 543 /*! @} */ 544 545 /*! @name TMR_ALARM_CTRL - Timer Alarm Control Register */ 546 /*! @{ */ 547 548 #define TMR0_BASE_TMR_ALARM_CTRL_ALARM1_PW_MASK (0x1FU) 549 #define TMR0_BASE_TMR_ALARM_CTRL_ALARM1_PW_SHIFT (0U) 550 #define TMR0_BASE_TMR_ALARM_CTRL_ALARM1_PW_WIDTH (5U) 551 #define TMR0_BASE_TMR_ALARM_CTRL_ALARM1_PW(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_ALARM_CTRL_ALARM1_PW_SHIFT)) & TMR0_BASE_TMR_ALARM_CTRL_ALARM1_PW_MASK) 552 553 #define TMR0_BASE_TMR_ALARM_CTRL_PG1_MASK (0x80U) 554 #define TMR0_BASE_TMR_ALARM_CTRL_PG1_SHIFT (7U) 555 #define TMR0_BASE_TMR_ALARM_CTRL_PG1_WIDTH (1U) 556 #define TMR0_BASE_TMR_ALARM_CTRL_PG1(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_ALARM_CTRL_PG1_SHIFT)) & TMR0_BASE_TMR_ALARM_CTRL_PG1_MASK) 557 558 #define TMR0_BASE_TMR_ALARM_CTRL_ALARM2_PW_MASK (0x1F00U) 559 #define TMR0_BASE_TMR_ALARM_CTRL_ALARM2_PW_SHIFT (8U) 560 #define TMR0_BASE_TMR_ALARM_CTRL_ALARM2_PW_WIDTH (5U) 561 #define TMR0_BASE_TMR_ALARM_CTRL_ALARM2_PW(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_ALARM_CTRL_ALARM2_PW_SHIFT)) & TMR0_BASE_TMR_ALARM_CTRL_ALARM2_PW_MASK) 562 563 #define TMR0_BASE_TMR_ALARM_CTRL_PG2_MASK (0x8000U) 564 #define TMR0_BASE_TMR_ALARM_CTRL_PG2_SHIFT (15U) 565 #define TMR0_BASE_TMR_ALARM_CTRL_PG2_WIDTH (1U) 566 #define TMR0_BASE_TMR_ALARM_CTRL_PG2(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_ALARM_CTRL_PG2_SHIFT)) & TMR0_BASE_TMR_ALARM_CTRL_PG2_MASK) 567 /*! @} */ 568 569 /*! @name TMR_FIPER - Timer 1 fixed interval period register..Timer 3 fixed interval period register */ 570 /*! @{ */ 571 572 #define TMR0_BASE_TMR_FIPER_FIPER_MASK (0xFFFFFFFFU) 573 #define TMR0_BASE_TMR_FIPER_FIPER_SHIFT (0U) 574 #define TMR0_BASE_TMR_FIPER_FIPER_WIDTH (32U) 575 #define TMR0_BASE_TMR_FIPER_FIPER(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_FIPER_FIPER_SHIFT)) & TMR0_BASE_TMR_FIPER_FIPER_MASK) 576 /*! @} */ 577 578 /*! @name TMR_FIPER_CTRL - Timer FIPER Control Register */ 579 /*! @{ */ 580 581 #define TMR0_BASE_TMR_FIPER_CTRL_FIPER1_PW_MASK (0x1FU) 582 #define TMR0_BASE_TMR_FIPER_CTRL_FIPER1_PW_SHIFT (0U) 583 #define TMR0_BASE_TMR_FIPER_CTRL_FIPER1_PW_WIDTH (5U) 584 #define TMR0_BASE_TMR_FIPER_CTRL_FIPER1_PW(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_FIPER_CTRL_FIPER1_PW_SHIFT)) & TMR0_BASE_TMR_FIPER_CTRL_FIPER1_PW_MASK) 585 586 #define TMR0_BASE_TMR_FIPER_CTRL_PG1_MASK (0x40U) 587 #define TMR0_BASE_TMR_FIPER_CTRL_PG1_SHIFT (6U) 588 #define TMR0_BASE_TMR_FIPER_CTRL_PG1_WIDTH (1U) 589 #define TMR0_BASE_TMR_FIPER_CTRL_PG1(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_FIPER_CTRL_PG1_SHIFT)) & TMR0_BASE_TMR_FIPER_CTRL_PG1_MASK) 590 591 #define TMR0_BASE_TMR_FIPER_CTRL_FIPER1_DIS_MASK (0x80U) 592 #define TMR0_BASE_TMR_FIPER_CTRL_FIPER1_DIS_SHIFT (7U) 593 #define TMR0_BASE_TMR_FIPER_CTRL_FIPER1_DIS_WIDTH (1U) 594 #define TMR0_BASE_TMR_FIPER_CTRL_FIPER1_DIS(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_FIPER_CTRL_FIPER1_DIS_SHIFT)) & TMR0_BASE_TMR_FIPER_CTRL_FIPER1_DIS_MASK) 595 596 #define TMR0_BASE_TMR_FIPER_CTRL_FIPER2_PW_MASK (0x1F00U) 597 #define TMR0_BASE_TMR_FIPER_CTRL_FIPER2_PW_SHIFT (8U) 598 #define TMR0_BASE_TMR_FIPER_CTRL_FIPER2_PW_WIDTH (5U) 599 #define TMR0_BASE_TMR_FIPER_CTRL_FIPER2_PW(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_FIPER_CTRL_FIPER2_PW_SHIFT)) & TMR0_BASE_TMR_FIPER_CTRL_FIPER2_PW_MASK) 600 601 #define TMR0_BASE_TMR_FIPER_CTRL_PG2_MASK (0x4000U) 602 #define TMR0_BASE_TMR_FIPER_CTRL_PG2_SHIFT (14U) 603 #define TMR0_BASE_TMR_FIPER_CTRL_PG2_WIDTH (1U) 604 #define TMR0_BASE_TMR_FIPER_CTRL_PG2(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_FIPER_CTRL_PG2_SHIFT)) & TMR0_BASE_TMR_FIPER_CTRL_PG2_MASK) 605 606 #define TMR0_BASE_TMR_FIPER_CTRL_FIPER2_DIS_MASK (0x8000U) 607 #define TMR0_BASE_TMR_FIPER_CTRL_FIPER2_DIS_SHIFT (15U) 608 #define TMR0_BASE_TMR_FIPER_CTRL_FIPER2_DIS_WIDTH (1U) 609 #define TMR0_BASE_TMR_FIPER_CTRL_FIPER2_DIS(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_FIPER_CTRL_FIPER2_DIS_SHIFT)) & TMR0_BASE_TMR_FIPER_CTRL_FIPER2_DIS_MASK) 610 611 #define TMR0_BASE_TMR_FIPER_CTRL_FIPER3_PW_MASK (0x1F0000U) 612 #define TMR0_BASE_TMR_FIPER_CTRL_FIPER3_PW_SHIFT (16U) 613 #define TMR0_BASE_TMR_FIPER_CTRL_FIPER3_PW_WIDTH (5U) 614 #define TMR0_BASE_TMR_FIPER_CTRL_FIPER3_PW(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_FIPER_CTRL_FIPER3_PW_SHIFT)) & TMR0_BASE_TMR_FIPER_CTRL_FIPER3_PW_MASK) 615 616 #define TMR0_BASE_TMR_FIPER_CTRL_PG3_MASK (0x400000U) 617 #define TMR0_BASE_TMR_FIPER_CTRL_PG3_SHIFT (22U) 618 #define TMR0_BASE_TMR_FIPER_CTRL_PG3_WIDTH (1U) 619 #define TMR0_BASE_TMR_FIPER_CTRL_PG3(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_FIPER_CTRL_PG3_SHIFT)) & TMR0_BASE_TMR_FIPER_CTRL_PG3_MASK) 620 621 #define TMR0_BASE_TMR_FIPER_CTRL_FIPER3_DIS_MASK (0x800000U) 622 #define TMR0_BASE_TMR_FIPER_CTRL_FIPER3_DIS_SHIFT (23U) 623 #define TMR0_BASE_TMR_FIPER_CTRL_FIPER3_DIS_WIDTH (1U) 624 #define TMR0_BASE_TMR_FIPER_CTRL_FIPER3_DIS(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_FIPER_CTRL_FIPER3_DIS_SHIFT)) & TMR0_BASE_TMR_FIPER_CTRL_FIPER3_DIS_MASK) 625 /*! @} */ 626 627 /*! @name TMR_ETTS1_L - External trigger stamp register */ 628 /*! @{ */ 629 630 #define TMR0_BASE_TMR_ETTS1_L_ETTS_L_MASK (0xFFFFFFFFU) 631 #define TMR0_BASE_TMR_ETTS1_L_ETTS_L_SHIFT (0U) 632 #define TMR0_BASE_TMR_ETTS1_L_ETTS_L_WIDTH (32U) 633 #define TMR0_BASE_TMR_ETTS1_L_ETTS_L(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_ETTS1_L_ETTS_L_SHIFT)) & TMR0_BASE_TMR_ETTS1_L_ETTS_L_MASK) 634 /*! @} */ 635 636 /*! @name TMR_ETTS1_H - External trigger stamp register */ 637 /*! @{ */ 638 639 #define TMR0_BASE_TMR_ETTS1_H_ETTS_H_MASK (0xFFFFFFFFU) 640 #define TMR0_BASE_TMR_ETTS1_H_ETTS_H_SHIFT (0U) 641 #define TMR0_BASE_TMR_ETTS1_H_ETTS_H_WIDTH (32U) 642 #define TMR0_BASE_TMR_ETTS1_H_ETTS_H(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_ETTS1_H_ETTS_H_SHIFT)) & TMR0_BASE_TMR_ETTS1_H_ETTS_H_MASK) 643 /*! @} */ 644 645 /*! @name TMR_ETTS2_L - External trigger stamp register */ 646 /*! @{ */ 647 648 #define TMR0_BASE_TMR_ETTS2_L_ETTS_L_MASK (0xFFFFFFFFU) 649 #define TMR0_BASE_TMR_ETTS2_L_ETTS_L_SHIFT (0U) 650 #define TMR0_BASE_TMR_ETTS2_L_ETTS_L_WIDTH (32U) 651 #define TMR0_BASE_TMR_ETTS2_L_ETTS_L(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_ETTS2_L_ETTS_L_SHIFT)) & TMR0_BASE_TMR_ETTS2_L_ETTS_L_MASK) 652 /*! @} */ 653 654 /*! @name TMR_ETTS2_H - External trigger stamp register */ 655 /*! @{ */ 656 657 #define TMR0_BASE_TMR_ETTS2_H_ETTS_H_MASK (0xFFFFFFFFU) 658 #define TMR0_BASE_TMR_ETTS2_H_ETTS_H_SHIFT (0U) 659 #define TMR0_BASE_TMR_ETTS2_H_ETTS_H_WIDTH (32U) 660 #define TMR0_BASE_TMR_ETTS2_H_ETTS_H(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_ETTS2_H_ETTS_H_SHIFT)) & TMR0_BASE_TMR_ETTS2_H_ETTS_H_MASK) 661 /*! @} */ 662 663 /*! @name TMR_CUR_TIME_L - Timer current time low register */ 664 /*! @{ */ 665 666 #define TMR0_BASE_TMR_CUR_TIME_L_TMR_CUR_TIME_L_MASK (0xFFFFFFFFU) 667 #define TMR0_BASE_TMR_CUR_TIME_L_TMR_CUR_TIME_L_SHIFT (0U) 668 #define TMR0_BASE_TMR_CUR_TIME_L_TMR_CUR_TIME_L_WIDTH (32U) 669 #define TMR0_BASE_TMR_CUR_TIME_L_TMR_CUR_TIME_L(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_CUR_TIME_L_TMR_CUR_TIME_L_SHIFT)) & TMR0_BASE_TMR_CUR_TIME_L_TMR_CUR_TIME_L_MASK) 670 /*! @} */ 671 672 /*! @name TMR_CUR_TIME_H - Timer current time high register */ 673 /*! @{ */ 674 675 #define TMR0_BASE_TMR_CUR_TIME_H_TMR_CUR_TIME_H_MASK (0xFFFFFFFFU) 676 #define TMR0_BASE_TMR_CUR_TIME_H_TMR_CUR_TIME_H_SHIFT (0U) 677 #define TMR0_BASE_TMR_CUR_TIME_H_TMR_CUR_TIME_H_WIDTH (32U) 678 #define TMR0_BASE_TMR_CUR_TIME_H_TMR_CUR_TIME_H(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_CUR_TIME_H_TMR_CUR_TIME_H_SHIFT)) & TMR0_BASE_TMR_CUR_TIME_H_TMR_CUR_TIME_H_MASK) 679 /*! @} */ 680 681 /*! @name TMR_PARAM - Timer parameter register */ 682 /*! @{ */ 683 684 #define TMR0_BASE_TMR_PARAM_SYNC_MASK (0x1U) 685 #define TMR0_BASE_TMR_PARAM_SYNC_SHIFT (0U) 686 #define TMR0_BASE_TMR_PARAM_SYNC_WIDTH (1U) 687 #define TMR0_BASE_TMR_PARAM_SYNC(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_PARAM_SYNC_SHIFT)) & TMR0_BASE_TMR_PARAM_SYNC_MASK) 688 689 #define TMR0_BASE_TMR_PARAM_PARAM_VAL_MASK (0xFFFFFFFEU) 690 #define TMR0_BASE_TMR_PARAM_PARAM_VAL_SHIFT (1U) 691 #define TMR0_BASE_TMR_PARAM_PARAM_VAL_WIDTH (31U) 692 #define TMR0_BASE_TMR_PARAM_PARAM_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMR0_BASE_TMR_PARAM_PARAM_VAL_SHIFT)) & TMR0_BASE_TMR_PARAM_PARAM_VAL_MASK) 693 /*! @} */ 694 695 /*! 696 * @} 697 */ /* end of group TMR0_BASE_Register_Masks */ 698 699 /*! 700 * @} 701 */ /* end of group TMR0_BASE_Peripheral_Access_Layer */ 702 703 #endif /* #if !defined(S32Z2_TMR0_BASE_H_) */ 704
