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Searched refs:Siul2_Icu_Ip_pBase (Results 1 – 6 of 6) sorted by relevance

/hal_nxp-3.6.0/s32/drivers/s32k3/Icu/src/
DSiul2_Icu_Ip.c107 SIUL2_Type * const Siul2_Icu_Ip_pBase[] = SIUL2_ICU_IP_BASE_PTRS; variable
183 (Siul2_Icu_Ip_pBase[instance])->IFCPR = (uint32)prescaler & SIUL2_IFCPR_IFCP_MASK; in Siul2_Icu_Ip_ConfigIntFilterClock()
225 base = Siul2_Icu_Ip_pBase[instance]; in Siul2_Icu_Ip_DeInit()
280 base = Siul2_Icu_Ip_pBase[instance]; in Siul2_Icu_Ip_Init()
287 Call_Siul2_Icu_SetUserAccessAllowed((uint32)Siul2_Icu_Ip_pBase[instance]); in Siul2_Icu_Ip_Init()
378 base = Siul2_Icu_Ip_pBase[instance]; in Siul2_Icu_Ip_SetActivationCondition()
415 flag = (Siul2_Icu_Ip_pBase[instance])->DISR0 & ((uint32)1U << hwChannel); in Siul2_Icu_Ip_GetInputState()
416 irqEnable = (Siul2_Icu_Ip_pBase[instance])->DIRER0 & ((uint32)1U << hwChannel); in Siul2_Icu_Ip_GetInputState()
422 (Siul2_Icu_Ip_pBase[instance])->DISR0 = flag; in Siul2_Icu_Ip_GetInputState()
458 (Siul2_Icu_Ip_pBase[instance])->DISR0 = ((uint32)1U << hwChannel); in Siul2_Icu_Ip_EnableInterrupt()
[all …]
DSiul2_Icu_Ip_Irq.c185 uint32 u32RegFlags = Siul2_Icu_Ip_pBase[instance]->DISR0; in Siul2_Icu_Ip_ProcessSingleInterrupt()
186 uint32 u32RegIrqEn = Siul2_Icu_Ip_pBase[instance]->DIRER0; in Siul2_Icu_Ip_ProcessSingleInterrupt()
196 Siul2_Icu_Ip_pBase[instance]->DISR0 = u32RegFlags & u32ChannelMask; in Siul2_Icu_Ip_ProcessSingleInterrupt()
228 uint32 u32RegFlags = (Siul2_Icu_Ip_pBase[instance])->DISR0; in Siul2_Icu_Ip_ProcessInterrupt()
229 uint32 u32RegIrqEn = (Siul2_Icu_Ip_pBase[instance])->DIRER0; in Siul2_Icu_Ip_ProcessInterrupt()
239 (Siul2_Icu_Ip_pBase[instance])->DISR0 = u32RegFlags & u32ChannelMask; in Siul2_Icu_Ip_ProcessInterrupt()
/hal_nxp-3.6.0/s32/drivers/s32ze/Icu/src/
DSiul2_Icu_Ip.c107 SIUL2_Type * const Siul2_Icu_Ip_pBase[] = SIUL2_ICU_IP_BASE_PTRS; variable
196 (Siul2_Icu_Ip_pBase[instance])->IFCPR = (uint32)prescaler & SIUL2_IFCPR_IFCP_MASK; in Siul2_Icu_Ip_ConfigIntFilterClock()
199 (Siul2_Icu_Ip_pBase[instance])->IFCPR = (uint32)prescaler & SIUL2_IFCPR_IFCP_MASK; in Siul2_Icu_Ip_ConfigIntFilterClock()
273 base = Siul2_Icu_Ip_pBase[instance]; in Siul2_Icu_Ip_DeInit()
359 base = Siul2_Icu_Ip_pBase[instance]; in Siul2_Icu_Ip_Init()
362 base = Siul2_Icu_Ip_pBase[instance]; in Siul2_Icu_Ip_Init()
363 Call_Siul2_Icu_SetUserAccessAllowed((uint32)Siul2_Icu_Ip_pBase[instance]); in Siul2_Icu_Ip_Init()
527 base = Siul2_Icu_Ip_pBase[instance]; in Siul2_Icu_Ip_SetActivationCondition()
612 flag = (Siul2_Icu_Ip_pBase[instance])->DISR0 & ((uint32)1U << hwChannel); in Siul2_Icu_Ip_GetInputState()
613 irqEnable = (Siul2_Icu_Ip_pBase[instance])->DIRER0 & ((uint32)1U << hwChannel); in Siul2_Icu_Ip_GetInputState()
[all …]
DSiul2_Icu_Ip_Irq.c196 u32RegFlags = Siul2_Icu_Ip_pBase[instance]->DISR0; in Siul2_Icu_Ip_ProcessSingleInterrupt()
197 u32RegIrqEn = Siul2_Icu_Ip_pBase[instance]->DIRER0; in Siul2_Icu_Ip_ProcessSingleInterrupt()
220 Siul2_Icu_Ip_pBase[instance]->DISR0 = u32RegFlags & u32ChannelMask; in Siul2_Icu_Ip_ProcessSingleInterrupt()
242 Siul2_Icu_Ip_pBase[instance]->DISR0 = u32RegFlags & u32ChannelMask; in Siul2_Icu_Ip_ProcessSingleInterrupt()
278 uint32 u32RegFlags = (Siul2_Icu_Ip_pBase[instance])->DISR0; in Siul2_Icu_Ip_ProcessInterrupt()
279 uint32 u32RegIrqEn = (Siul2_Icu_Ip_pBase[instance])->DIRER0; in Siul2_Icu_Ip_ProcessInterrupt()
289 (Siul2_Icu_Ip_pBase[instance])->DISR0 = u32RegFlags & u32ChannelMask; in Siul2_Icu_Ip_ProcessInterrupt()
/hal_nxp-3.6.0/s32/drivers/s32k3/Icu/include/
DSiul2_Icu_Ip.h130 extern SIUL2_Type * const Siul2_Icu_Ip_pBase[];
/hal_nxp-3.6.0/s32/drivers/s32ze/Icu/include/
DSiul2_Icu_Ip.h130 extern SIUL2_Type * const Siul2_Icu_Ip_pBase[];