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Searched refs:SYSCTL0_PDRCFGSET_REG (Results 1 – 12 of 12) sorted by relevance

/hal_nxp-3.6.0/mcux/mcux-sdk/components/power_manager/devices/MIMXRT685S/
Dfsl_pm_device.c301 SYSCTL0_PDRCFGSET_REG(1) = enResPRAMs[feature].ppd_mask; in iMXRT600_DisablePeripheralsSleep()
307 SYSCTL0_PDRCFGSET_REG(1) = enResPRAMs[feature].apd_mask | enResPRAMs[feature].ppd_mask; in iMXRT600_DisablePeripheralsSleep()
331 SYSCTL0_PDRCFGSET_REG(3) = enResSRAMs[feature]; in iMXRT600_DisablePeripheralsSleep()
337 SYSCTL0_PDRCFGSET_REG(2) = enResSRAMs[feature]; in iMXRT600_DisablePeripheralsSleep()
338 SYSCTL0_PDRCFGSET_REG(3) = enResSRAMs[feature]; in iMXRT600_DisablePeripheralsSleep()
357 SYSCTL0_PDRCFGSET_REG(enResPeripherals[feature].group) = enResPeripherals[feature].mask; in iMXRT600_DisablePeripheralsSleep()
/hal_nxp-3.6.0/mcux/mcux-sdk/components/power_manager/devices/MIMXRT533S/
Dfsl_pm_device.c328 SYSCTL0_PDRCFGSET_REG(1) = enResPRAMs[feature].ppd_mask; in iMXRT500_DisablePeripheralsSleep()
334 SYSCTL0_PDRCFGSET_REG(1) = enResPRAMs[feature].apd_mask | enResPRAMs[feature].ppd_mask; in iMXRT500_DisablePeripheralsSleep()
358 SYSCTL0_PDRCFGSET_REG(3) = enResSRAMs[feature]; in iMXRT500_DisablePeripheralsSleep()
364 SYSCTL0_PDRCFGSET_REG(2) = enResSRAMs[feature]; in iMXRT500_DisablePeripheralsSleep()
365 SYSCTL0_PDRCFGSET_REG(3) = enResSRAMs[feature]; in iMXRT500_DisablePeripheralsSleep()
384 SYSCTL0_PDRCFGSET_REG(enResPeripherals[feature].group) = enResPeripherals[feature].mask; in iMXRT500_DisablePeripheralsSleep()
/hal_nxp-3.6.0/mcux/mcux-sdk/components/power_manager/devices/MIMXRT555S/
Dfsl_pm_device.c328 SYSCTL0_PDRCFGSET_REG(1) = enResPRAMs[feature].ppd_mask; in iMXRT500_DisablePeripheralsSleep()
334 SYSCTL0_PDRCFGSET_REG(1) = enResPRAMs[feature].apd_mask | enResPRAMs[feature].ppd_mask; in iMXRT500_DisablePeripheralsSleep()
358 SYSCTL0_PDRCFGSET_REG(3) = enResSRAMs[feature]; in iMXRT500_DisablePeripheralsSleep()
364 SYSCTL0_PDRCFGSET_REG(2) = enResSRAMs[feature]; in iMXRT500_DisablePeripheralsSleep()
365 SYSCTL0_PDRCFGSET_REG(3) = enResSRAMs[feature]; in iMXRT500_DisablePeripheralsSleep()
384 SYSCTL0_PDRCFGSET_REG(enResPeripherals[feature].group) = enResPeripherals[feature].mask; in iMXRT500_DisablePeripheralsSleep()
/hal_nxp-3.6.0/mcux/mcux-sdk/components/power_manager/devices/MIMXRT595S/
Dfsl_pm_device.c328 SYSCTL0_PDRCFGSET_REG(1) = enResPRAMs[feature].ppd_mask; in iMXRT500_DisablePeripheralsSleep()
334 SYSCTL0_PDRCFGSET_REG(1) = enResPRAMs[feature].apd_mask | enResPRAMs[feature].ppd_mask; in iMXRT500_DisablePeripheralsSleep()
358 SYSCTL0_PDRCFGSET_REG(3) = enResSRAMs[feature]; in iMXRT500_DisablePeripheralsSleep()
364 SYSCTL0_PDRCFGSET_REG(2) = enResSRAMs[feature]; in iMXRT500_DisablePeripheralsSleep()
365 SYSCTL0_PDRCFGSET_REG(3) = enResSRAMs[feature]; in iMXRT500_DisablePeripheralsSleep()
384 SYSCTL0_PDRCFGSET_REG(enResPeripherals[feature].group) = enResPeripherals[feature].mask; in iMXRT500_DisablePeripheralsSleep()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT633S/drivers/
Dfsl_power.h27 #define SYSCTL0_PDRCFGSET_REG(x) (*((volatile uint32_t *)((uint32_t)(&(SYSCTL0->PDRUNCFG0_SET)) + (… macro
344 SYSCTL0_PDRCFGSET_REG(((uint32_t)en) >> 8UL) = (1UL << (((uint32_t)en) & 0xFFU)); in POWER_EnablePD()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT685S/drivers/
Dfsl_power.h27 #define SYSCTL0_PDRCFGSET_REG(x) (*((volatile uint32_t *)((uint32_t)(&(SYSCTL0->PDRUNCFG0_SET)) + (… macro
344 SYSCTL0_PDRCFGSET_REG(((uint32_t)en) >> 8UL) = (1UL << (((uint32_t)en) & 0xFFU)); in POWER_EnablePD()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT555S/drivers/
Dfsl_power.h28 #define SYSCTL0_PDRCFGSET_REG(x) (*((volatile uint32_t *)((uint32_t)(&(SYSCTL0->PDRUNCFG0_SET)) + (… macro
Dfsl_power.c252 SYSCTL0_PDRCFGSET_REG(((uint32_t)en) >> 8UL) = (1UL << (((uint32_t)en) & 0xFFU)); in POWER_EnablePD()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT595S/drivers/
Dfsl_power.h28 #define SYSCTL0_PDRCFGSET_REG(x) (*((volatile uint32_t *)((uint32_t)(&(SYSCTL0->PDRUNCFG0_SET)) + (… macro
Dfsl_power.c252 SYSCTL0_PDRCFGSET_REG(((uint32_t)en) >> 8UL) = (1UL << (((uint32_t)en) & 0xFFU)); in POWER_EnablePD()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT533S/drivers/
Dfsl_power.h28 #define SYSCTL0_PDRCFGSET_REG(x) (*((volatile uint32_t *)((uint32_t)(&(SYSCTL0->PDRUNCFG0_SET)) + (… macro
Dfsl_power.c252 SYSCTL0_PDRCFGSET_REG(((uint32_t)en) >> 8UL) = (1UL << (((uint32_t)en) & 0xFFU)); in POWER_EnablePD()