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Searched refs:SYSCTL0_PDRCFGCLR_REG (Results 1 – 12 of 12) sorted by relevance

/hal_nxp-3.6.0/mcux/mcux-sdk/components/power_manager/devices/MIMXRT685S/
Dfsl_pm_device.c294 … SYSCTL0_PDRCFGCLR_REG(1) = enResPRAMs[feature].apd_mask | enResPRAMs[feature].ppd_mask; in iMXRT600_DisablePeripheralsSleep()
299 SYSCTL0_PDRCFGCLR_REG(1) = enResPRAMs[feature].apd_mask; in iMXRT600_DisablePeripheralsSleep()
323 SYSCTL0_PDRCFGCLR_REG(2) = enResSRAMs[feature]; in iMXRT600_DisablePeripheralsSleep()
324 SYSCTL0_PDRCFGCLR_REG(3) = enResSRAMs[feature]; in iMXRT600_DisablePeripheralsSleep()
329 SYSCTL0_PDRCFGCLR_REG(2) = enResSRAMs[feature]; in iMXRT600_DisablePeripheralsSleep()
352 SYSCTL0_PDRCFGCLR_REG(enResPeripherals[feature].group) = enResPeripherals[feature].mask; in iMXRT600_DisablePeripheralsSleep()
/hal_nxp-3.6.0/mcux/mcux-sdk/components/power_manager/devices/MIMXRT533S/
Dfsl_pm_device.c321 … SYSCTL0_PDRCFGCLR_REG(1) = enResPRAMs[feature].apd_mask | enResPRAMs[feature].ppd_mask; in iMXRT500_DisablePeripheralsSleep()
326 SYSCTL0_PDRCFGCLR_REG(1) = enResPRAMs[feature].apd_mask; in iMXRT500_DisablePeripheralsSleep()
350 SYSCTL0_PDRCFGCLR_REG(2) = enResSRAMs[feature]; in iMXRT500_DisablePeripheralsSleep()
351 SYSCTL0_PDRCFGCLR_REG(3) = enResSRAMs[feature]; in iMXRT500_DisablePeripheralsSleep()
356 SYSCTL0_PDRCFGCLR_REG(2) = enResSRAMs[feature]; in iMXRT500_DisablePeripheralsSleep()
379 SYSCTL0_PDRCFGCLR_REG(enResPeripherals[feature].group) = enResPeripherals[feature].mask; in iMXRT500_DisablePeripheralsSleep()
/hal_nxp-3.6.0/mcux/mcux-sdk/components/power_manager/devices/MIMXRT555S/
Dfsl_pm_device.c321 … SYSCTL0_PDRCFGCLR_REG(1) = enResPRAMs[feature].apd_mask | enResPRAMs[feature].ppd_mask; in iMXRT500_DisablePeripheralsSleep()
326 SYSCTL0_PDRCFGCLR_REG(1) = enResPRAMs[feature].apd_mask; in iMXRT500_DisablePeripheralsSleep()
350 SYSCTL0_PDRCFGCLR_REG(2) = enResSRAMs[feature]; in iMXRT500_DisablePeripheralsSleep()
351 SYSCTL0_PDRCFGCLR_REG(3) = enResSRAMs[feature]; in iMXRT500_DisablePeripheralsSleep()
356 SYSCTL0_PDRCFGCLR_REG(2) = enResSRAMs[feature]; in iMXRT500_DisablePeripheralsSleep()
379 SYSCTL0_PDRCFGCLR_REG(enResPeripherals[feature].group) = enResPeripherals[feature].mask; in iMXRT500_DisablePeripheralsSleep()
/hal_nxp-3.6.0/mcux/mcux-sdk/components/power_manager/devices/MIMXRT595S/
Dfsl_pm_device.c321 … SYSCTL0_PDRCFGCLR_REG(1) = enResPRAMs[feature].apd_mask | enResPRAMs[feature].ppd_mask; in iMXRT500_DisablePeripheralsSleep()
326 SYSCTL0_PDRCFGCLR_REG(1) = enResPRAMs[feature].apd_mask; in iMXRT500_DisablePeripheralsSleep()
350 SYSCTL0_PDRCFGCLR_REG(2) = enResSRAMs[feature]; in iMXRT500_DisablePeripheralsSleep()
351 SYSCTL0_PDRCFGCLR_REG(3) = enResSRAMs[feature]; in iMXRT500_DisablePeripheralsSleep()
356 SYSCTL0_PDRCFGCLR_REG(2) = enResSRAMs[feature]; in iMXRT500_DisablePeripheralsSleep()
379 SYSCTL0_PDRCFGCLR_REG(enResPeripherals[feature].group) = enResPeripherals[feature].mask; in iMXRT500_DisablePeripheralsSleep()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT633S/drivers/
Dfsl_power.h28 #define SYSCTL0_PDRCFGCLR_REG(x) (*((volatile uint32_t *)((uint32_t)(&(SYSCTL0->PDRUNCFG0_CLR)) + (… macro
355 SYSCTL0_PDRCFGCLR_REG(((uint32_t)en) >> 8UL) = (1UL << (((uint32_t)en) & 0xFFU)); in POWER_DisablePD()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT685S/drivers/
Dfsl_power.h28 #define SYSCTL0_PDRCFGCLR_REG(x) (*((volatile uint32_t *)((uint32_t)(&(SYSCTL0->PDRUNCFG0_CLR)) + (… macro
355 SYSCTL0_PDRCFGCLR_REG(((uint32_t)en) >> 8UL) = (1UL << (((uint32_t)en) & 0xFFU)); in POWER_DisablePD()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT555S/drivers/
Dfsl_power.h29 #define SYSCTL0_PDRCFGCLR_REG(x) (*((volatile uint32_t *)((uint32_t)(&(SYSCTL0->PDRUNCFG0_CLR)) + (… macro
Dfsl_power.c274 SYSCTL0_PDRCFGCLR_REG(((uint32_t)en) >> 8UL) = (1UL << (((uint32_t)en) & 0xFFU)); in POWER_DisablePD()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT595S/drivers/
Dfsl_power.h29 #define SYSCTL0_PDRCFGCLR_REG(x) (*((volatile uint32_t *)((uint32_t)(&(SYSCTL0->PDRUNCFG0_CLR)) + (… macro
Dfsl_power.c274 SYSCTL0_PDRCFGCLR_REG(((uint32_t)en) >> 8UL) = (1UL << (((uint32_t)en) & 0xFFU)); in POWER_DisablePD()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT533S/drivers/
Dfsl_power.h29 #define SYSCTL0_PDRCFGCLR_REG(x) (*((volatile uint32_t *)((uint32_t)(&(SYSCTL0->PDRUNCFG0_CLR)) + (… macro
Dfsl_power.c274 SYSCTL0_PDRCFGCLR_REG(((uint32_t)en) >> 8UL) = (1UL << (((uint32_t)en) & 0xFFU)); in POWER_DisablePD()