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Searched refs:SYSCON_SPIFICLKDIV_HALT_MASK (Results 1 – 18 of 18) sorted by relevance

/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54114/
DLPC54114_cm4.h9238 #define SYSCON_SPIFICLKDIV_HALT_MASK (0x40000000U) macro
9243 … (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_HALT_SHIFT)) & SYSCON_SPIFICLKDIV_HALT_MASK)
DLPC54114_cm0plus.h9225 #define SYSCON_SPIFICLKDIV_HALT_MASK (0x40000000U) macro
9230 … (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_HALT_SHIFT)) & SYSCON_SPIFICLKDIV_HALT_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54113/
DLPC54113.h9239 #define SYSCON_SPIFICLKDIV_HALT_MASK (0x40000000U) macro
9244 … (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_HALT_SHIFT)) & SYSCON_SPIFICLKDIV_HALT_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54607/
DLPC54607.h14156 #define SYSCON_SPIFICLKDIV_HALT_MASK (0x40000000U) macro
14161 … (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_HALT_SHIFT)) & SYSCON_SPIFICLKDIV_HALT_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54S005/
DLPC54S005.h14162 #define SYSCON_SPIFICLKDIV_HALT_MASK (0x40000000U) macro
14167 … (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_HALT_SHIFT)) & SYSCON_SPIFICLKDIV_HALT_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54005/
DLPC54005.h13370 #define SYSCON_SPIFICLKDIV_HALT_MASK (0x40000000U) macro
13375 … (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_HALT_SHIFT)) & SYSCON_SPIFICLKDIV_HALT_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54605/
DLPC54605.h13512 #define SYSCON_SPIFICLKDIV_HALT_MASK (0x40000000U) macro
13517 … (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_HALT_SHIFT)) & SYSCON_SPIFICLKDIV_HALT_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54616/
DLPC54616.h17735 #define SYSCON_SPIFICLKDIV_HALT_MASK (0x40000000U) macro
17740 … (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_HALT_SHIFT)) & SYSCON_SPIFICLKDIV_HALT_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54016/
DLPC54016.h16555 #define SYSCON_SPIFICLKDIV_HALT_MASK (0x40000000U) macro
16560 … (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_HALT_SHIFT)) & SYSCON_SPIFICLKDIV_HALT_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54606/
DLPC54606.h17660 #define SYSCON_SPIFICLKDIV_HALT_MASK (0x40000000U) macro
17665 … (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_HALT_SHIFT)) & SYSCON_SPIFICLKDIV_HALT_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54628/
DLPC54628.h18581 #define SYSCON_SPIFICLKDIV_HALT_MASK (0x40000000U) macro
18586 … (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_HALT_SHIFT)) & SYSCON_SPIFICLKDIV_HALT_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54618/
DLPC54618.h18380 #define SYSCON_SPIFICLKDIV_HALT_MASK (0x40000000U) macro
18385 … (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_HALT_SHIFT)) & SYSCON_SPIFICLKDIV_HALT_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54S016/
DLPC54S016.h17261 #define SYSCON_SPIFICLKDIV_HALT_MASK (0x40000000U) macro
17266 … (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_HALT_SHIFT)) & SYSCON_SPIFICLKDIV_HALT_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54608/
DLPC54608.h18303 #define SYSCON_SPIFICLKDIV_HALT_MASK (0x40000000U) macro
18308 … (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_HALT_SHIFT)) & SYSCON_SPIFICLKDIV_HALT_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54S018M/
DLPC54S018M.h19055 #define SYSCON_SPIFICLKDIV_HALT_MASK (0x40000000U) macro
19060 … (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_HALT_SHIFT)) & SYSCON_SPIFICLKDIV_HALT_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54S018/
DLPC54S018.h19055 #define SYSCON_SPIFICLKDIV_HALT_MASK (0x40000000U) macro
19060 … (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_HALT_SHIFT)) & SYSCON_SPIFICLKDIV_HALT_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54018/
DLPC54018.h18263 #define SYSCON_SPIFICLKDIV_HALT_MASK (0x40000000U) macro
18268 … (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_HALT_SHIFT)) & SYSCON_SPIFICLKDIV_HALT_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54018M/
DLPC54018M.h18263 #define SYSCON_SPIFICLKDIV_HALT_MASK (0x40000000U) macro
18268 … (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_HALT_SHIFT)) & SYSCON_SPIFICLKDIV_HALT_MASK)