SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK (reference) in projects: hal_nxp-3.6.0

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Searched refs:SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK (Results 1 – 23 of 23) sorted by relevance

/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54607/
D	LPC54607.h	`14723 #define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK (0x3U) macro 14727 …int32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK)`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54S005/
D	LPC54S005.h	`14665 #define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK (0x3U) macro 14669 …int32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK)`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54005/
D	LPC54005.h	`13873 #define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK (0x3U) macro 13877 …int32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK)`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54605/
D	LPC54605.h	`14079 #define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK (0x3U) macro 14083 …int32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK)`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54616/
D	LPC54616.h	`18302 #define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK (0x3U) macro 18306 …int32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK)`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54016/
D	LPC54016.h	`16996 #define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK (0x3U) macro 16999 …int32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK)`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54606/
D	LPC54606.h	`18227 #define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK (0x3U) macro 18231 …int32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK)`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54628/
D	LPC54628.h	`19148 #define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK (0x3U) macro 19152 …int32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK)`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54618/
D	LPC54618.h	`18947 #define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK (0x3U) macro 18951 …int32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK)`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54S016/
D	LPC54S016.h	`17702 #define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK (0x3U) macro 17705 …int32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK)`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54608/
D	LPC54608.h	`18870 #define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK (0x3U) macro 18874 …int32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK)`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54S018M/
D	LPC54S018M.h	`19558 #define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK (0x3U) macro 19562 …int32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK)`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54S018/
D	LPC54S018.h	`19558 #define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK (0x3U) macro 19562 …int32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK)`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54018/
D	LPC54018.h	`18766 #define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK (0x3U) macro 18770 …int32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK)`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54018M/
D	LPC54018M.h	`18766 #define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK (0x3U) macro 18770 …int32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK)`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC5528/
D	LPC5528.h	`22053 #define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK (0x3U) macro 22061 …int32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK)`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC5526/
D	LPC5526.h	`22053 #define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK (0x3U) macro 22061 …int32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK)`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC55S26/
D	LPC55S26.h	`23709 #define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK (0x3U) macro 23717 …int32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK)`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC55S28/
D	LPC55S28.h	`23709 #define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK (0x3U) macro 23717 …int32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK)`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC55S66/
D	LPC55S66_cm33_core0.h	`24329 #define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK (0x3U) macro 24337 …int32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK)`
D	LPC55S66_cm33_core1.h	`24329 #define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK (0x3U) macro 24337 …int32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK)`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC55S69/
D	LPC55S69_cm33_core1.h	`24329 #define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK (0x3U) macro 24337 …int32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK)`
D	LPC55S69_cm33_core0.h	`24329 #define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK (0x3U) macro 24337 …int32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK)`

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