1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2023 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_SW_ETH_MAC_PORT0.h 10 * @version 2.1 11 * @date 2023-07-20 12 * @brief Peripheral Access Layer for S32Z2_SW_ETH_MAC_PORT0 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_SW_ETH_MAC_PORT0_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_SW_ETH_MAC_PORT0_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- SW_ETH_MAC_PORT0 Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup SW_ETH_MAC_PORT0_Peripheral_Access_Layer SW_ETH_MAC_PORT0 Peripheral Access Layer 68 * @{ 69 */ 70 71 /** SW_ETH_MAC_PORT0 - Register Layout Typedef */ 72 typedef struct { 73 uint8_t RESERVED_0[8]; 74 __IO uint32_t PM0_COMMAND_CONFIG; /**< Port MAC 0 Command and Configuration Register, offset: 0x8 */ 75 __I uint32_t PM0_MAC_ADDR_0; /**< Port MAC 0 MAC Address Register 0, offset: 0xC */ 76 __I uint32_t PM0_MAC_ADDR_1; /**< Port MAC 0 MAC Address Register 1, offset: 0x10 */ 77 __IO uint32_t PM0_MAXFRM; /**< Port MAC 0 Maximum Frame Length Register, offset: 0x14 */ 78 uint8_t RESERVED_1[40]; 79 __IO uint32_t PM0_IEVENT; /**< Port MAC 0 Interrupt Event Register, offset: 0x40 */ 80 uint8_t RESERVED_2[8]; 81 __IO uint32_t PM0_IMASK; /**< Port MAC 0 Interrupt Mask Register(INT_MASK), offset: 0x4C */ 82 uint8_t RESERVED_3[4]; 83 __IO uint32_t PM0_PAUSE_QUANTA; /**< Port MAC 0 Pause Quanta Register, offset: 0x54 */ 84 uint8_t RESERVED_4[12]; 85 __IO uint32_t PM0_PAUSE_THRESH; /**< Port MAC 0 Pause Quanta Threshold Register, offset: 0x64 */ 86 uint8_t RESERVED_5[12]; 87 __I uint32_t PM0_RX_PAUSE_STATUS; /**< Port MAC 0 Receive Pause Status Register, offset: 0x74 */ 88 uint8_t RESERVED_6[64]; 89 __IO uint32_t PM0_LPWAKE_TIMER; /**< Port MAC 0 EEE Low Power Wakeup Timer Register, offset: 0xB8 */ 90 __IO uint32_t PM0_SLEEP_TIMER; /**< Port MAC 0 Transmit EEE Low Power Timer Register, offset: 0xBC */ 91 __IO uint32_t PM0_SINGLE_STEP; /**< Port MAC 0 IEEE1588 Single-Step Control Register, offset: 0xC0 */ 92 uint8_t RESERVED_7[12]; 93 __IO uint32_t PM0_HD_BACKOFF_ENTROPY; /**< Port MAC 0 half-duplex backoff entropy register, offset: 0xD0 */ 94 uint8_t RESERVED_8[12]; 95 __IO uint32_t PM0_STATN_CONFIG; /**< Port MAC 0 Statistics Configuration Register, offset: 0xE0 */ 96 uint8_t RESERVED_9[28]; 97 __I uint64_t PM0_REOCTN; /**< Port MAC 0 Receive Ethernet Octets Counter(etherStatsOctetsn), offset: 0x100 */ 98 __I uint64_t PM0_ROCTN; /**< Port MAC 0 Receive Octets Counter(iflnOctetsn), offset: 0x108 */ 99 uint8_t RESERVED_10[8]; 100 __I uint64_t PM0_RXPFN; /**< Port MAC 0 Receive Valid Pause Frame Counter Register(aPAUSEMACCtrlFramesReceivedn), offset: 0x118 */ 101 __I uint64_t PM0_RFRMN; /**< Port MAC 0 Receive Frame Counter Register(aFramesReceivedOKn), offset: 0x120 */ 102 __I uint64_t PM0_RFCSN; /**< Port MAC 0 Receive Frame Check Sequence Error Counter Register(), offset: 0x128 */ 103 __I uint64_t PM0_RVLANN; /**< Port MAC 0 Receive VLAN Frame Counter Register(VLANReceivedOKn), offset: 0x130 */ 104 __I uint64_t PM0_RERRN; /**< Port MAC 0 Receive Frame Error Counter Register(ifInErrorsn), offset: 0x138 */ 105 __I uint64_t PM0_RUCAN; /**< Port MAC 0 Receive Unicast Frame Counter Register(ifInUcastPktsn), offset: 0x140 */ 106 __I uint64_t PM0_RMCAN; /**< Port MAC 0 Receive Multicast Frame Counter Register(ifInMulticastPktsn), offset: 0x148 */ 107 __I uint64_t PM0_RBCAN; /**< Port MAC 0 Receive Broadcast Frame Counter Register(ifInBroadcastPktsn), offset: 0x150 */ 108 __I uint64_t PM0_RDRPN; /**< Port MAC 0 Receive Dropped Packets Counter Register(etherStatsDropEventsn), offset: 0x158 */ 109 __I uint64_t PM0_RPKTN; /**< Port MAC 0 Receive Packets Counter Register(etherStatsPktsn), offset: 0x160 */ 110 __I uint64_t PM0_RUNDN; /**< Port MAC 0 Receive Undersized Packet Counter Register(etherStatsUndersizePktsn), offset: 0x168 */ 111 __I uint64_t PM0_R64N; /**< Port MAC 0 Receive 64-Octet Packet Counter Register(etherStatsPkts64OctetsN), offset: 0x170 */ 112 __I uint64_t PM0_R127N; /**< Port MAC 0 Receive 65 to 127-Octet Packet Counter Register(etherStatsPkts65to127OctetsN), offset: 0x178 */ 113 __I uint64_t PM0_R255N; /**< Port MAC 0 Receive 128 to 255-Octet Packet Counter Register(etherStatsPkts128to255OctetsN), offset: 0x180 */ 114 __I uint64_t PM0_R511N; /**< Port MAC 0 Receive 256 to 511-Octet Packet Counter Register(etherStatsPkts256to511OctetsN), offset: 0x188 */ 115 __I uint64_t PM0_R1023N; /**< Port MAC 0 Receive 512 to 1023-Octet Packet Counter Register(etherStatsPkts512to1023OctetsN), offset: 0x190 */ 116 __I uint64_t PM0_R1522N; /**< Port MAC 0 Receive 1024 to 1522-Octet Packet Counter Register(etherStatsPkts1024to1522OctetsN), offset: 0x198 */ 117 __I uint64_t PM0_R1523XN; /**< Port MAC 0 Receive 1523 to Max-Octet Packet Counter Register(etherStatsPkts1523toMaxOctetsN), offset: 0x1A0 */ 118 __I uint64_t PM0_ROVRN; /**< Port MAC 0 Receive Oversized Packet Counter Register(etherStatsOversizePktsn), offset: 0x1A8 */ 119 __I uint64_t PM0_RJBRN; /**< Port MAC 0 Receive Jabber Packet Counter Register(etherStatsJabbersn), offset: 0x1B0 */ 120 __I uint64_t PM0_RFRGN; /**< Port MAC 0 Receive Fragment Packet Counter Register(etherStatsFragmentsn, offset: 0x1B8 */ 121 __I uint64_t PM0_RCNPN; /**< Port MAC 0 Receive Control Packet Counter Register, offset: 0x1C0 */ 122 __I uint64_t PM0_RDRNTPN; /**< Port MAC 0 Receive Dropped Not Truncated Packets Counter Register(etherStatsDropEventsn), offset: 0x1C8 */ 123 uint8_t RESERVED_11[48]; 124 __I uint64_t PM0_TEOCTN; /**< Port MAC 0 Transmit Ethernet Octets Counter(etherStatsOctetsn), offset: 0x200 */ 125 __I uint64_t PM0_TOCTN; /**< Port MAC 0 Transmit Octets Counter Register(ifOutOctetsn), offset: 0x208 */ 126 uint8_t RESERVED_12[8]; 127 __I uint64_t PM0_TXPFN; /**< Port MAC 0 Transmit Valid Pause Frame Counter Register(aPAUSEMACCtrlFramesReceivedn), offset: 0x218 */ 128 __I uint64_t PM0_TFRMN; /**< Port MAC 0 Transmit Frame Counter Register(aFramesTransmittedOKn), offset: 0x220 */ 129 __I uint64_t PM0_TFCSN; /**< Port MAC 0 Transmit Frame Check Sequence Error Counter Register(), offset: 0x228 */ 130 __I uint64_t PM0_TVLANN; /**< Port MAC 0 Transmit VLAN Frame Counter Register(VLANTransmittedOKn), offset: 0x230 */ 131 __I uint64_t PM0_TERRN; /**< Port MAC 0 Transmit Frame Error Counter Register(ifOutErrorsn), offset: 0x238 */ 132 __I uint64_t PM0_TUCAN; /**< Port MAC 0 Transmit Unicast Frame Counter Register(ifOutUcastPktsn), offset: 0x240 */ 133 __I uint64_t PM0_TMCAN; /**< Port MAC 0 Transmit Multicast Frame Counter Register(ifOutMulticastPktsn), offset: 0x248 */ 134 __I uint64_t PM0_TBCAN; /**< Port MAC 0 Transmit Broadcast Frame Counter Register(ifOutBroadcastPktsn), offset: 0x250 */ 135 uint8_t RESERVED_13[8]; 136 __I uint64_t PM0_TPKTN; /**< Port MAC 0 Transmit Packets Counter Register(etherStatsPktsn), offset: 0x260 */ 137 __I uint64_t PM0_TUNDN; /**< Port MAC 0 Transmit Undersized Packet Counter Register(etherStatsUndersizePktsn), offset: 0x268 */ 138 __I uint64_t PM0_T64N; /**< Port MAC 0 Transmit 64-Octet Packet Counter Register (etherStatsPkts64OctetsN), offset: 0x270 */ 139 __I uint64_t PM0_T127N; /**< Port MAC 0 Transmit 65 to 127-Octet Packet Counter Register (etherStatsPkts65to127OctetsN), offset: 0x278 */ 140 __I uint64_t PM0_T255N; /**< Port MAC 0 Transmit 128 to 255-Octet Packet Counter Register (etherStatsPkts128to255OctetsN), offset: 0x280 */ 141 __I uint64_t PM0_T511N; /**< Port MAC 0 Transmit 256 to 511-Octet Packet Counter Register (etherStatsPkts256to511OctetsN), offset: 0x288 */ 142 __I uint64_t PM0_T1023N; /**< Port MAC 0 Transmit 512 to 1023-Octet Packet Counter Register (etherStatsPkts512to1023OctetsN), offset: 0x290 */ 143 __I uint64_t PM0_T1522N; /**< Port MAC 0 Transmit 1024 to 1522-Octet Packet Counter Register (etherStatsPkts1024to1522OctetsN), offset: 0x298 */ 144 __I uint64_t PM0_T1523XN; /**< Port MAC 0 Transmit 1523 to TX_MTU-Octet Packet Counter Register (etherStatsPkts1523toMaxOctetsN), offset: 0x2A0 */ 145 uint8_t RESERVED_14[24]; 146 __I uint64_t PM0_TCNPN; /**< Port MAC 0 Transmit Control Packet Counter Register, offset: 0x2C0 */ 147 uint8_t RESERVED_15[8]; 148 __I uint64_t PM0_TDFRN; /**< Port MAC 0 Transmit Deferred Packet Counter Register(aFramesWithDeferredXmissions), offset: 0x2D0 */ 149 __I uint64_t PM0_TMCOLN; /**< Port MAC 0 Transmit Multiple Collisions Counter Register(aMultipleCollisionFrames), offset: 0x2D8 */ 150 __I uint64_t PM0_TSCOLN; /**< Port MAC 0 Transmit Single Collision Counter(aSingleCollisionFrames) Register, offset: 0x2E0 */ 151 __I uint64_t PM0_TLCOLN; /**< Port MAC 0 Transmit Late Collision Counter(aLateCollisions) Register, offset: 0x2E8 */ 152 __I uint64_t PM0_TECOLN; /**< Port MAC 0 Transmit Excessive Collisions Counter Register, offset: 0x2F0 */ 153 uint8_t RESERVED_16[8]; 154 __IO uint32_t PM0_IF_MODE; /**< Port MAC 0 Interface Mode Control Register, offset: 0x300 */ 155 uint8_t RESERVED_17[260]; 156 __IO uint32_t PM1_COMMAND_CONFIG; /**< Port MAC 1 Command and Configuration Register, offset: 0x408 */ 157 __I uint32_t PM1_MAC_ADDR_0; /**< Port MAC 1 MAC Address Register 0, offset: 0x40C */ 158 __I uint32_t PM1_MAC_ADDR_1; /**< Port MAC 1 MAC Address Register 1, offset: 0x410 */ 159 __IO uint32_t PM1_MAXFRM; /**< Port MAC 1 Maximum Frame Length Register, offset: 0x414 */ 160 uint8_t RESERVED_18[40]; 161 __IO uint32_t PM1_IEVENT; /**< Port MAC 1 Interrupt Event Register, offset: 0x440 */ 162 uint8_t RESERVED_19[8]; 163 __IO uint32_t PM1_IMASK; /**< Port MAC 1 Interrupt Mask Register(INT_MASK), offset: 0x44C */ 164 uint8_t RESERVED_20[4]; 165 __IO uint32_t PM1_PAUSE_QUANTA; /**< Port MAC 1 Pause Quanta Register, offset: 0x454 */ 166 uint8_t RESERVED_21[12]; 167 __IO uint32_t PM1_PAUSE_THRESH; /**< Port MAC 1 Pause Quanta Threshold Register, offset: 0x464 */ 168 uint8_t RESERVED_22[12]; 169 __I uint32_t PM1_RX_PAUSE_STATUS; /**< Port MAC 1 Receive Pause Status Register, offset: 0x474 */ 170 uint8_t RESERVED_23[64]; 171 __IO uint32_t PM1_LPWAKE_TIMER; /**< Port MAC 1 EEE Low Power Wakeup Timer Register, offset: 0x4B8 */ 172 __IO uint32_t PM1_SLEEP_TIMER; /**< Port MAC 1 Transmit EEE Low Power Timer Register, offset: 0x4BC */ 173 __IO uint32_t PM1_SINGLE_STEP; /**< Port MAC 1 IEEE1588 Single-Step Control Register, offset: 0x4C0 */ 174 uint8_t RESERVED_24[12]; 175 __IO uint32_t PM1_HD_BACKOFF_ENTROPY; /**< Port MAC 1 half-duplex backoff entropy register, offset: 0x4D0 */ 176 uint8_t RESERVED_25[12]; 177 __IO uint32_t PM1_STATN_CONFIG; /**< Port MAC 1 Statistics Configuration Register, offset: 0x4E0 */ 178 uint8_t RESERVED_26[28]; 179 __I uint64_t PM1_REOCTN; /**< Port MAC 1 Receive Ethernet Octets Counter(etherStatsOctetsn), offset: 0x500 */ 180 __I uint64_t PM1_ROCTN; /**< Port MAC 1 Receive Octets Counter(iflnOctetsn), offset: 0x508 */ 181 uint8_t RESERVED_27[8]; 182 __I uint64_t PM1_RXPFN; /**< Port MAC 1 Receive Valid Pause Frame Counter Register(aPAUSEMACCtrlFramesReceivedn), offset: 0x518 */ 183 __I uint64_t PM1_RFRMN; /**< Port MAC 1 Receive Frame Counter Register(aFramesReceivedOKn), offset: 0x520 */ 184 __I uint64_t PM1_RFCSN; /**< Port MAC 1 Receive Frame Check Sequence Error Counter Register(), offset: 0x528 */ 185 __I uint64_t PM1_RVLANN; /**< Port MAC 1 Receive VLAN Frame Counter Register(VLANReceivedOKn), offset: 0x530 */ 186 __I uint64_t PM1_RERRN; /**< Port MAC 1 Receive Frame Error Counter Register(ifInErrorsn), offset: 0x538 */ 187 __I uint64_t PM1_RUCAN; /**< Port MAC 1 Receive Unicast Frame Counter Register(ifInUcastPktsn), offset: 0x540 */ 188 __I uint64_t PM1_RMCAN; /**< Port MAC 1 Receive Multicast Frame Counter Register(ifInMulticastPktsn), offset: 0x548 */ 189 __I uint64_t PM1_RBCAN; /**< Port MAC 1 Receive Broadcast Frame Counter Register(ifInBroadcastPktsn), offset: 0x550 */ 190 __I uint64_t PM1_RDRPN; /**< Port MAC 1 Receive Dropped Packets Counter Register(etherStatsDropEventsn), offset: 0x558 */ 191 __I uint64_t PM1_RPKTN; /**< Port MAC 1 Receive Packets Counter Register(etherStatsPktsn), offset: 0x560 */ 192 __I uint64_t PM1_RUNDN; /**< Port MAC 1 Receive Undersized Packet Counter Register(etherStatsUndersizePktsn), offset: 0x568 */ 193 __I uint64_t PM1_R64N; /**< Port MAC 1 Receive 64-Octet Packet Counter Register(etherStatsPkts64OctetsN), offset: 0x570 */ 194 __I uint64_t PM1_R127N; /**< Port MAC 1 Receive 65 to 127-Octet Packet Counter Register(etherStatsPkts65to127OctetsN), offset: 0x578 */ 195 __I uint64_t PM1_R255N; /**< Port MAC 1 Receive 128 to 255-Octet Packet Counter Register(etherStatsPkts128to255OctetsN), offset: 0x580 */ 196 __I uint64_t PM1_R511N; /**< Port MAC 1 Receive 256 to 511-Octet Packet Counter Register(etherStatsPkts256to511OctetsN), offset: 0x588 */ 197 __I uint64_t PM1_R1023N; /**< Port MAC 1 Receive 512 to 1023-Octet Packet Counter Register(etherStatsPkts512to1023OctetsN), offset: 0x590 */ 198 __I uint64_t PM1_R1522N; /**< Port MAC 1 Receive 1024 to 1522-Octet Packet Counter Register(etherStatsPkts1024to1522OctetsN), offset: 0x598 */ 199 __I uint64_t PM1_R1523XN; /**< Port MAC 1 Receive 1523 to Max-Octet Packet Counter Register(etherStatsPkts1523toMaxOctetsN), offset: 0x5A0 */ 200 __I uint64_t PM1_ROVRN; /**< Port MAC 1 Receive Oversized Packet Counter Register(etherStatsOversizePktsn), offset: 0x5A8 */ 201 __I uint64_t PM1_RJBRN; /**< Port MAC 1 Receive Jabber Packet Counter Register(etherStatsJabbersn), offset: 0x5B0 */ 202 __I uint64_t PM1_RFRGN; /**< Port MAC 1 Receive Fragment Packet Counter Register(etherStatsFragmentsn, offset: 0x5B8 */ 203 __I uint64_t PM1_RCNPN; /**< Port MAC 1 Receive Control Packet Counter Register, offset: 0x5C0 */ 204 __I uint64_t PM1_RDRNTPN; /**< Port MAC 1 Receive Dropped Not Truncated Packets Counter Register(etherStatsDropEventsn), offset: 0x5C8 */ 205 uint8_t RESERVED_28[48]; 206 __I uint64_t PM1_TEOCTN; /**< Port MAC 1 Transmit Ethernet Octets Counter(etherStatsOctetsn), offset: 0x600 */ 207 __I uint64_t PM1_TOCTN; /**< Port MAC 1 Transmit Octets Counter Register(ifOutOctetsn), offset: 0x608 */ 208 uint8_t RESERVED_29[8]; 209 __I uint64_t PM1_TXPFN; /**< Port MAC 1 Transmit Valid Pause Frame Counter Register(aPAUSEMACCtrlFramesReceivedn), offset: 0x618 */ 210 __I uint64_t PM1_TFRMN; /**< Port MAC 1 Transmit Frame Counter Register(aFramesTransmittedOKn), offset: 0x620 */ 211 __I uint64_t PM1_TFCSN; /**< Port MAC 1 Transmit Frame Check Sequence Error Counter Register(), offset: 0x628 */ 212 __I uint64_t PM1_TVLANN; /**< Port MAC 1 Transmit VLAN Frame Counter Register(VLANTransmittedOKn), offset: 0x630 */ 213 __I uint64_t PM1_TERRN; /**< Port MAC 1 Transmit Frame Error Counter Register(ifOutErrorsn), offset: 0x638 */ 214 __I uint64_t PM1_TUCAN; /**< Port MAC 1 Transmit Unicast Frame Counter Register(ifOutUcastPktsn), offset: 0x640 */ 215 __I uint64_t PM1_TMCAN; /**< Port MAC 1 Transmit Multicast Frame Counter Register(ifOutMulticastPktsn), offset: 0x648 */ 216 __I uint64_t PM1_TBCAN; /**< Port MAC 1 Transmit Broadcast Frame Counter Register(ifOutBroadcastPktsn), offset: 0x650 */ 217 uint8_t RESERVED_30[8]; 218 __I uint64_t PM1_TPKTN; /**< Port MAC 1 Transmit Packets Counter Register(etherStatsPktsn), offset: 0x660 */ 219 __I uint64_t PM1_TUNDN; /**< Port MAC 1 Transmit Undersized Packet Counter Register(etherStatsUndersizePktsn), offset: 0x668 */ 220 __I uint64_t PM1_T64N; /**< Port MAC 1 Transmit 64-Octet Packet Counter Register (etherStatsPkts64OctetsN), offset: 0x670 */ 221 __I uint64_t PM1_T127N; /**< Port MAC 1 Transmit 65 to 127-Octet Packet Counter Register (etherStatsPkts65to127OctetsN), offset: 0x678 */ 222 __I uint64_t PM1_T255N; /**< Port MAC 1 Transmit 128 to 255-Octet Packet Counter Register (etherStatsPkts128to255OctetsN), offset: 0x680 */ 223 __I uint64_t PM1_T511N; /**< Port MAC 1 Transmit 256 to 511-Octet Packet Counter Register (etherStatsPkts256to511OctetsN), offset: 0x688 */ 224 __I uint64_t PM1_T1023N; /**< Port MAC 1 Transmit 512 to 1023-Octet Packet Counter Register (etherStatsPkts512to1023OctetsN), offset: 0x690 */ 225 __I uint64_t PM1_T1522N; /**< Port MAC 1 Transmit 1024 to 1522-Octet Packet Counter Register (etherStatsPkts1024to1522OctetsN), offset: 0x698 */ 226 __I uint64_t PM1_T1523XN; /**< Port MAC 1 Transmit 1523 to TX_MTU-Octet Packet Counter Register (etherStatsPkts1523toMaxOctetsN), offset: 0x6A0 */ 227 uint8_t RESERVED_31[24]; 228 __I uint64_t PM1_TCNPN; /**< Port MAC 1 Transmit Control Packet Counter Register, offset: 0x6C0 */ 229 uint8_t RESERVED_32[8]; 230 __I uint64_t PM1_TDFRN; /**< Port MAC 1 Transmit Deferred Packet Counter Register(aFramesWithDeferredXmissions), offset: 0x6D0 */ 231 __I uint64_t PM1_TMCOLN; /**< Port MAC 1 Transmit Multiple Collisions Counter Register(aMultipleCollisionFrames), offset: 0x6D8 */ 232 __I uint64_t PM1_TSCOLN; /**< Port MAC 1 Transmit Single Collision Counter(aSingleCollisionFrames) Register, offset: 0x6E0 */ 233 __I uint64_t PM1_TLCOLN; /**< Port MAC 1 Transmit Late Collision Counter(aLateCollisions) Register, offset: 0x6E8 */ 234 __I uint64_t PM1_TECOLN; /**< Port MAC 1 Transmit Excessive Collisions Counter Register, offset: 0x6F0 */ 235 uint8_t RESERVED_33[8]; 236 __IO uint32_t PM1_IF_MODE; /**< Port MAC 1 Interface Mode Control Register, offset: 0x700 */ 237 uint8_t RESERVED_34[252]; 238 __IO uint32_t MAC_MERGE_MMCSR; /**< Port MAC Merge Control and Status Register, offset: 0x800 */ 239 uint8_t RESERVED_35[4]; 240 __IO uint32_t MAC_MERGE_MMFAECR; /**< Port MAC Merge Frame Assembly Error Count Register, offset: 0x808 */ 241 __IO uint32_t MAC_MERGE_MMFSECR; /**< Port MAC Merge Frame SMD Error Count Register, offset: 0x80C */ 242 __IO uint32_t MAC_MERGE_MMFAOCR; /**< Port MAC Merge Frame Assembly OK Count Register, offset: 0x810 */ 243 __IO uint32_t MAC_MERGE_MMFCRXR; /**< Port MAC Merge Fragment Count RX Register, offset: 0x814 */ 244 __IO uint32_t MAC_MERGE_MMFCTXR; /**< Port MAC Merge Fragment Count TX Register, offset: 0x818 */ 245 __IO uint32_t MAC_MERGE_MMHCR; /**< Port MAC Merge Hold Count Register, offset: 0x81C */ 246 uint8_t RESERVED_36[992]; 247 __IO uint32_t PEMDIOCR; /**< Port external MDIO configuration register, offset: 0xC00 */ 248 __IO uint32_t PEMDIOICR; /**< Port external MDIO interface control register, offset: 0xC04 */ 249 __IO uint32_t PEMDIOIDR; /**< Port external MDIO interface data register, offset: 0xC08 */ 250 __IO uint32_t PEMDIORAR; /**< Port external MDIO register address register, offset: 0xC0C */ 251 __I uint32_t PEMDIOSR; /**< Port external MDIO status register, offset: 0xC10 */ 252 uint8_t RESERVED_37[12]; 253 __IO uint32_t PPSCR; /**< PHY status configuration register, offset: 0xC20 */ 254 __IO uint32_t PPSCTRLR; /**< Port PHY status control register, offset: 0xC24 */ 255 __I uint32_t PPSDR; /**< Port PHY status data register, offset: 0xC28 */ 256 __IO uint32_t PPSRAR; /**< Port PHY status register address register, offset: 0xC2C */ 257 __IO uint32_t PPSER; /**< Port PHY status event register, offset: 0xC30 */ 258 __IO uint32_t PPSMR; /**< Port PHY status mask register, offset: 0xC34 */ 259 } SW_ETH_MAC_PORT0_Type, *SW_ETH_MAC_PORT0_MemMapPtr; 260 261 /** Number of instances of the SW_ETH_MAC_PORT0 module. */ 262 #define SW_ETH_MAC_PORT0_INSTANCE_COUNT (1u) 263 264 /* SW_ETH_MAC_PORT0 - Peripheral instance base addresses */ 265 /** Peripheral NETC__SW0_ETH_MAC_PORT0 base address */ 266 #define IP_NETC__SW0_ETH_MAC_PORT0_BASE (0x74A05000u) 267 /** Peripheral NETC__SW0_ETH_MAC_PORT0 base pointer */ 268 #define IP_NETC__SW0_ETH_MAC_PORT0 ((SW_ETH_MAC_PORT0_Type *)IP_NETC__SW0_ETH_MAC_PORT0_BASE) 269 /** Array initializer of SW_ETH_MAC_PORT0 peripheral base addresses */ 270 #define IP_SW_ETH_MAC_PORT0_BASE_ADDRS { IP_NETC__SW0_ETH_MAC_PORT0_BASE } 271 /** Array initializer of SW_ETH_MAC_PORT0 peripheral base pointers */ 272 #define IP_SW_ETH_MAC_PORT0_BASE_PTRS { IP_NETC__SW0_ETH_MAC_PORT0 } 273 274 /* ---------------------------------------------------------------------------- 275 -- SW_ETH_MAC_PORT0 Register Masks 276 ---------------------------------------------------------------------------- */ 277 278 /*! 279 * @addtogroup SW_ETH_MAC_PORT0_Register_Masks SW_ETH_MAC_PORT0 Register Masks 280 * @{ 281 */ 282 283 /*! @name PM0_COMMAND_CONFIG - Port MAC 0 Command and Configuration Register */ 284 /*! @{ */ 285 286 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TX_EN_MASK (0x1U) 287 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TX_EN_SHIFT (0U) 288 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TX_EN_WIDTH (1U) 289 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TX_EN_SHIFT)) & SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TX_EN_MASK) 290 291 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_RX_EN_MASK (0x2U) 292 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_RX_EN_SHIFT (1U) 293 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_RX_EN_WIDTH (1U) 294 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_RX_EN_SHIFT)) & SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_RX_EN_MASK) 295 296 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_PAUSE_FWD_MASK (0x80U) 297 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_PAUSE_FWD_SHIFT (7U) 298 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_PAUSE_FWD_WIDTH (1U) 299 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_PAUSE_FWD(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_PAUSE_FWD_SHIFT)) & SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_PAUSE_FWD_MASK) 300 301 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_PAUSE_IGN_MASK (0x100U) 302 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_PAUSE_IGN_SHIFT (8U) 303 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_PAUSE_IGN_WIDTH (1U) 304 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_PAUSE_IGN(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_PAUSE_IGN_SHIFT)) & SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_PAUSE_IGN_MASK) 305 306 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TX_ADDR_INS_MASK (0x200U) 307 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TX_ADDR_INS_SHIFT (9U) 308 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TX_ADDR_INS_WIDTH (1U) 309 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TX_ADDR_INS(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TX_ADDR_INS_SHIFT)) & SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TX_ADDR_INS_MASK) 310 311 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_LOOP_ENA_MASK (0x400U) 312 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_LOOP_ENA_SHIFT (10U) 313 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_LOOP_ENA_WIDTH (1U) 314 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_LOOP_ENA(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_LOOP_ENA_SHIFT)) & SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_LOOP_ENA_MASK) 315 316 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_CNT_FRM_EN_MASK (0x2000U) 317 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_CNT_FRM_EN_SHIFT (13U) 318 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_CNT_FRM_EN_WIDTH (1U) 319 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_CNT_FRM_EN(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_CNT_FRM_EN_SHIFT)) & SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_CNT_FRM_EN_MASK) 320 321 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TXP_MASK (0x8000U) 322 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TXP_SHIFT (15U) 323 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TXP_WIDTH (1U) 324 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TXP(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TXP_SHIFT)) & SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TXP_MASK) 325 326 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TX_FLUSH_MASK (0x400000U) 327 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TX_FLUSH_SHIFT (22U) 328 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TX_FLUSH_WIDTH (1U) 329 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TX_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TX_FLUSH_SHIFT)) & SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TX_FLUSH_MASK) 330 331 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TX_LOWP_ENA_MASK (0x800000U) 332 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TX_LOWP_ENA_SHIFT (23U) 333 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TX_LOWP_ENA_WIDTH (1U) 334 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TX_LOWP_ENA(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TX_LOWP_ENA_SHIFT)) & SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TX_LOWP_ENA_MASK) 335 336 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_SWR_MASK (0x4000000U) 337 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_SWR_SHIFT (26U) 338 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_SWR_WIDTH (1U) 339 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_SWR(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_SWR_SHIFT)) & SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_SWR_MASK) 340 341 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TS_MODE_MASK (0x40000000U) 342 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TS_MODE_SHIFT (30U) 343 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TS_MODE_WIDTH (1U) 344 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TS_MODE(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TS_MODE_SHIFT)) & SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TS_MODE_MASK) 345 346 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_MG_MASK (0x80000000U) 347 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_MG_SHIFT (31U) 348 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_MG_WIDTH (1U) 349 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_MG(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_MG_SHIFT)) & SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_MG_MASK) 350 /*! @} */ 351 352 /*! @name PM0_MAC_ADDR_0 - Port MAC 0 MAC Address Register 0 */ 353 /*! @{ */ 354 355 #define SW_ETH_MAC_PORT0_PM0_MAC_ADDR_0_MAC_ADDR_0_MASK (0xFFFFFFFFU) 356 #define SW_ETH_MAC_PORT0_PM0_MAC_ADDR_0_MAC_ADDR_0_SHIFT (0U) 357 #define SW_ETH_MAC_PORT0_PM0_MAC_ADDR_0_MAC_ADDR_0_WIDTH (32U) 358 #define SW_ETH_MAC_PORT0_PM0_MAC_ADDR_0_MAC_ADDR_0(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_MAC_ADDR_0_MAC_ADDR_0_SHIFT)) & SW_ETH_MAC_PORT0_PM0_MAC_ADDR_0_MAC_ADDR_0_MASK) 359 /*! @} */ 360 361 /*! @name PM0_MAC_ADDR_1 - Port MAC 0 MAC Address Register 1 */ 362 /*! @{ */ 363 364 #define SW_ETH_MAC_PORT0_PM0_MAC_ADDR_1_MAC_ADDR_1_MASK (0xFFFFU) 365 #define SW_ETH_MAC_PORT0_PM0_MAC_ADDR_1_MAC_ADDR_1_SHIFT (0U) 366 #define SW_ETH_MAC_PORT0_PM0_MAC_ADDR_1_MAC_ADDR_1_WIDTH (16U) 367 #define SW_ETH_MAC_PORT0_PM0_MAC_ADDR_1_MAC_ADDR_1(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_MAC_ADDR_1_MAC_ADDR_1_SHIFT)) & SW_ETH_MAC_PORT0_PM0_MAC_ADDR_1_MAC_ADDR_1_MASK) 368 /*! @} */ 369 370 /*! @name PM0_MAXFRM - Port MAC 0 Maximum Frame Length Register */ 371 /*! @{ */ 372 373 #define SW_ETH_MAC_PORT0_PM0_MAXFRM_MAXFRM_MASK (0xFFFFU) 374 #define SW_ETH_MAC_PORT0_PM0_MAXFRM_MAXFRM_SHIFT (0U) 375 #define SW_ETH_MAC_PORT0_PM0_MAXFRM_MAXFRM_WIDTH (16U) 376 #define SW_ETH_MAC_PORT0_PM0_MAXFRM_MAXFRM(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_MAXFRM_MAXFRM_SHIFT)) & SW_ETH_MAC_PORT0_PM0_MAXFRM_MAXFRM_MASK) 377 378 #define SW_ETH_MAC_PORT0_PM0_MAXFRM_TX_MTU_MASK (0xFFFF0000U) 379 #define SW_ETH_MAC_PORT0_PM0_MAXFRM_TX_MTU_SHIFT (16U) 380 #define SW_ETH_MAC_PORT0_PM0_MAXFRM_TX_MTU_WIDTH (16U) 381 #define SW_ETH_MAC_PORT0_PM0_MAXFRM_TX_MTU(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_MAXFRM_TX_MTU_SHIFT)) & SW_ETH_MAC_PORT0_PM0_MAXFRM_TX_MTU_MASK) 382 /*! @} */ 383 384 /*! @name PM0_IEVENT - Port MAC 0 Interrupt Event Register */ 385 /*! @{ */ 386 387 #define SW_ETH_MAC_PORT0_PM0_IEVENT_TX_EMPTY_MASK (0x20U) 388 #define SW_ETH_MAC_PORT0_PM0_IEVENT_TX_EMPTY_SHIFT (5U) 389 #define SW_ETH_MAC_PORT0_PM0_IEVENT_TX_EMPTY_WIDTH (1U) 390 #define SW_ETH_MAC_PORT0_PM0_IEVENT_TX_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_IEVENT_TX_EMPTY_SHIFT)) & SW_ETH_MAC_PORT0_PM0_IEVENT_TX_EMPTY_MASK) 391 392 #define SW_ETH_MAC_PORT0_PM0_IEVENT_RX_EMPTY_MASK (0x40U) 393 #define SW_ETH_MAC_PORT0_PM0_IEVENT_RX_EMPTY_SHIFT (6U) 394 #define SW_ETH_MAC_PORT0_PM0_IEVENT_RX_EMPTY_WIDTH (1U) 395 #define SW_ETH_MAC_PORT0_PM0_IEVENT_RX_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_IEVENT_RX_EMPTY_SHIFT)) & SW_ETH_MAC_PORT0_PM0_IEVENT_RX_EMPTY_MASK) 396 397 #define SW_ETH_MAC_PORT0_PM0_IEVENT_TX_OVFL_MASK (0x400U) 398 #define SW_ETH_MAC_PORT0_PM0_IEVENT_TX_OVFL_SHIFT (10U) 399 #define SW_ETH_MAC_PORT0_PM0_IEVENT_TX_OVFL_WIDTH (1U) 400 #define SW_ETH_MAC_PORT0_PM0_IEVENT_TX_OVFL(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_IEVENT_TX_OVFL_SHIFT)) & SW_ETH_MAC_PORT0_PM0_IEVENT_TX_OVFL_MASK) 401 402 #define SW_ETH_MAC_PORT0_PM0_IEVENT_TX_UNFL_MASK (0x800U) 403 #define SW_ETH_MAC_PORT0_PM0_IEVENT_TX_UNFL_SHIFT (11U) 404 #define SW_ETH_MAC_PORT0_PM0_IEVENT_TX_UNFL_WIDTH (1U) 405 #define SW_ETH_MAC_PORT0_PM0_IEVENT_TX_UNFL(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_IEVENT_TX_UNFL_SHIFT)) & SW_ETH_MAC_PORT0_PM0_IEVENT_TX_UNFL_MASK) 406 407 #define SW_ETH_MAC_PORT0_PM0_IEVENT_RX_OVFL_MASK (0x1000U) 408 #define SW_ETH_MAC_PORT0_PM0_IEVENT_RX_OVFL_SHIFT (12U) 409 #define SW_ETH_MAC_PORT0_PM0_IEVENT_RX_OVFL_WIDTH (1U) 410 #define SW_ETH_MAC_PORT0_PM0_IEVENT_RX_OVFL(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_IEVENT_RX_OVFL_SHIFT)) & SW_ETH_MAC_PORT0_PM0_IEVENT_RX_OVFL_MASK) 411 412 #define SW_ETH_MAC_PORT0_PM0_IEVENT_MGI_MASK (0x4000U) 413 #define SW_ETH_MAC_PORT0_PM0_IEVENT_MGI_SHIFT (14U) 414 #define SW_ETH_MAC_PORT0_PM0_IEVENT_MGI_WIDTH (1U) 415 #define SW_ETH_MAC_PORT0_PM0_IEVENT_MGI(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_IEVENT_MGI_SHIFT)) & SW_ETH_MAC_PORT0_PM0_IEVENT_MGI_MASK) 416 /*! @} */ 417 418 /*! @name PM0_IMASK - Port MAC 0 Interrupt Mask Register(INT_MASK) */ 419 /*! @{ */ 420 421 #define SW_ETH_MAC_PORT0_PM0_IMASK_MGI_MASK (0x4000U) 422 #define SW_ETH_MAC_PORT0_PM0_IMASK_MGI_SHIFT (14U) 423 #define SW_ETH_MAC_PORT0_PM0_IMASK_MGI_WIDTH (1U) 424 #define SW_ETH_MAC_PORT0_PM0_IMASK_MGI(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_IMASK_MGI_SHIFT)) & SW_ETH_MAC_PORT0_PM0_IMASK_MGI_MASK) 425 /*! @} */ 426 427 /*! @name PM0_PAUSE_QUANTA - Port MAC 0 Pause Quanta Register */ 428 /*! @{ */ 429 430 #define SW_ETH_MAC_PORT0_PM0_PAUSE_QUANTA_PQNT_MASK (0xFFFFU) 431 #define SW_ETH_MAC_PORT0_PM0_PAUSE_QUANTA_PQNT_SHIFT (0U) 432 #define SW_ETH_MAC_PORT0_PM0_PAUSE_QUANTA_PQNT_WIDTH (16U) 433 #define SW_ETH_MAC_PORT0_PM0_PAUSE_QUANTA_PQNT(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_PAUSE_QUANTA_PQNT_SHIFT)) & SW_ETH_MAC_PORT0_PM0_PAUSE_QUANTA_PQNT_MASK) 434 /*! @} */ 435 436 /*! @name PM0_PAUSE_THRESH - Port MAC 0 Pause Quanta Threshold Register */ 437 /*! @{ */ 438 439 #define SW_ETH_MAC_PORT0_PM0_PAUSE_THRESH_QTH_MASK (0xFFFFU) 440 #define SW_ETH_MAC_PORT0_PM0_PAUSE_THRESH_QTH_SHIFT (0U) 441 #define SW_ETH_MAC_PORT0_PM0_PAUSE_THRESH_QTH_WIDTH (16U) 442 #define SW_ETH_MAC_PORT0_PM0_PAUSE_THRESH_QTH(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_PAUSE_THRESH_QTH_SHIFT)) & SW_ETH_MAC_PORT0_PM0_PAUSE_THRESH_QTH_MASK) 443 /*! @} */ 444 445 /*! @name PM0_RX_PAUSE_STATUS - Port MAC 0 Receive Pause Status Register */ 446 /*! @{ */ 447 448 #define SW_ETH_MAC_PORT0_PM0_RX_PAUSE_STATUS_PSTAT_MASK (0x1U) 449 #define SW_ETH_MAC_PORT0_PM0_RX_PAUSE_STATUS_PSTAT_SHIFT (0U) 450 #define SW_ETH_MAC_PORT0_PM0_RX_PAUSE_STATUS_PSTAT_WIDTH (1U) 451 #define SW_ETH_MAC_PORT0_PM0_RX_PAUSE_STATUS_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_RX_PAUSE_STATUS_PSTAT_SHIFT)) & SW_ETH_MAC_PORT0_PM0_RX_PAUSE_STATUS_PSTAT_MASK) 452 /*! @} */ 453 454 /*! @name PM0_LPWAKE_TIMER - Port MAC 0 EEE Low Power Wakeup Timer Register */ 455 /*! @{ */ 456 457 #define SW_ETH_MAC_PORT0_PM0_LPWAKE_TIMER_TW_SYS_TX_MASK (0xFFFFFFU) 458 #define SW_ETH_MAC_PORT0_PM0_LPWAKE_TIMER_TW_SYS_TX_SHIFT (0U) 459 #define SW_ETH_MAC_PORT0_PM0_LPWAKE_TIMER_TW_SYS_TX_WIDTH (24U) 460 #define SW_ETH_MAC_PORT0_PM0_LPWAKE_TIMER_TW_SYS_TX(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_LPWAKE_TIMER_TW_SYS_TX_SHIFT)) & SW_ETH_MAC_PORT0_PM0_LPWAKE_TIMER_TW_SYS_TX_MASK) 461 /*! @} */ 462 463 /*! @name PM0_SLEEP_TIMER - Port MAC 0 Transmit EEE Low Power Timer Register */ 464 /*! @{ */ 465 466 #define SW_ETH_MAC_PORT0_PM0_SLEEP_TIMER_SLEEPT_MASK (0xFFFFFFU) 467 #define SW_ETH_MAC_PORT0_PM0_SLEEP_TIMER_SLEEPT_SHIFT (0U) 468 #define SW_ETH_MAC_PORT0_PM0_SLEEP_TIMER_SLEEPT_WIDTH (24U) 469 #define SW_ETH_MAC_PORT0_PM0_SLEEP_TIMER_SLEEPT(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_SLEEP_TIMER_SLEEPT_SHIFT)) & SW_ETH_MAC_PORT0_PM0_SLEEP_TIMER_SLEEPT_MASK) 470 /*! @} */ 471 472 /*! @name PM0_SINGLE_STEP - Port MAC 0 IEEE1588 Single-Step Control Register */ 473 /*! @{ */ 474 475 #define SW_ETH_MAC_PORT0_PM0_SINGLE_STEP_OFFSET_MASK (0xFF80U) 476 #define SW_ETH_MAC_PORT0_PM0_SINGLE_STEP_OFFSET_SHIFT (7U) 477 #define SW_ETH_MAC_PORT0_PM0_SINGLE_STEP_OFFSET_WIDTH (9U) 478 #define SW_ETH_MAC_PORT0_PM0_SINGLE_STEP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_SINGLE_STEP_OFFSET_SHIFT)) & SW_ETH_MAC_PORT0_PM0_SINGLE_STEP_OFFSET_MASK) 479 480 #define SW_ETH_MAC_PORT0_PM0_SINGLE_STEP_EN_MASK (0x80000000U) 481 #define SW_ETH_MAC_PORT0_PM0_SINGLE_STEP_EN_SHIFT (31U) 482 #define SW_ETH_MAC_PORT0_PM0_SINGLE_STEP_EN_WIDTH (1U) 483 #define SW_ETH_MAC_PORT0_PM0_SINGLE_STEP_EN(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_SINGLE_STEP_EN_SHIFT)) & SW_ETH_MAC_PORT0_PM0_SINGLE_STEP_EN_MASK) 484 /*! @} */ 485 486 /*! @name PM0_HD_BACKOFF_ENTROPY - Port MAC 0 half-duplex backoff entropy register */ 487 /*! @{ */ 488 489 #define SW_ETH_MAC_PORT0_PM0_HD_BACKOFF_ENTROPY_HD_BACKOFF_ENTROPY_MASK (0x3FFU) 490 #define SW_ETH_MAC_PORT0_PM0_HD_BACKOFF_ENTROPY_HD_BACKOFF_ENTROPY_SHIFT (0U) 491 #define SW_ETH_MAC_PORT0_PM0_HD_BACKOFF_ENTROPY_HD_BACKOFF_ENTROPY_WIDTH (10U) 492 #define SW_ETH_MAC_PORT0_PM0_HD_BACKOFF_ENTROPY_HD_BACKOFF_ENTROPY(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_HD_BACKOFF_ENTROPY_HD_BACKOFF_ENTROPY_SHIFT)) & SW_ETH_MAC_PORT0_PM0_HD_BACKOFF_ENTROPY_HD_BACKOFF_ENTROPY_MASK) 493 494 #define SW_ETH_MAC_PORT0_PM0_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID_MASK (0x80000000U) 495 #define SW_ETH_MAC_PORT0_PM0_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID_SHIFT (31U) 496 #define SW_ETH_MAC_PORT0_PM0_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID_WIDTH (1U) 497 #define SW_ETH_MAC_PORT0_PM0_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID_SHIFT)) & SW_ETH_MAC_PORT0_PM0_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID_MASK) 498 /*! @} */ 499 500 /*! @name PM0_STATN_CONFIG - Port MAC 0 Statistics Configuration Register */ 501 /*! @{ */ 502 503 #define SW_ETH_MAC_PORT0_PM0_STATN_CONFIG_SAT_MASK (0x1U) 504 #define SW_ETH_MAC_PORT0_PM0_STATN_CONFIG_SAT_SHIFT (0U) 505 #define SW_ETH_MAC_PORT0_PM0_STATN_CONFIG_SAT_WIDTH (1U) 506 #define SW_ETH_MAC_PORT0_PM0_STATN_CONFIG_SAT(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_STATN_CONFIG_SAT_SHIFT)) & SW_ETH_MAC_PORT0_PM0_STATN_CONFIG_SAT_MASK) 507 508 #define SW_ETH_MAC_PORT0_PM0_STATN_CONFIG_COD_MASK (0x2U) 509 #define SW_ETH_MAC_PORT0_PM0_STATN_CONFIG_COD_SHIFT (1U) 510 #define SW_ETH_MAC_PORT0_PM0_STATN_CONFIG_COD_WIDTH (1U) 511 #define SW_ETH_MAC_PORT0_PM0_STATN_CONFIG_COD(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_STATN_CONFIG_COD_SHIFT)) & SW_ETH_MAC_PORT0_PM0_STATN_CONFIG_COD_MASK) 512 513 #define SW_ETH_MAC_PORT0_PM0_STATN_CONFIG_CLR_MASK (0x4U) 514 #define SW_ETH_MAC_PORT0_PM0_STATN_CONFIG_CLR_SHIFT (2U) 515 #define SW_ETH_MAC_PORT0_PM0_STATN_CONFIG_CLR_WIDTH (1U) 516 #define SW_ETH_MAC_PORT0_PM0_STATN_CONFIG_CLR(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_STATN_CONFIG_CLR_SHIFT)) & SW_ETH_MAC_PORT0_PM0_STATN_CONFIG_CLR_MASK) 517 /*! @} */ 518 519 /*! @name PM0_REOCTN - Port MAC 0 Receive Ethernet Octets Counter(etherStatsOctetsn) */ 520 /*! @{ */ 521 522 #define SW_ETH_MAC_PORT0_PM0_REOCTN_REOCTn_MASK (0xFFFFFFFFFFFFFFFFU) 523 #define SW_ETH_MAC_PORT0_PM0_REOCTN_REOCTn_SHIFT (0U) 524 #define SW_ETH_MAC_PORT0_PM0_REOCTN_REOCTn_WIDTH (64U) 525 #define SW_ETH_MAC_PORT0_PM0_REOCTN_REOCTn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_REOCTN_REOCTn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_REOCTN_REOCTn_MASK) 526 /*! @} */ 527 528 /*! @name PM0_ROCTN - Port MAC 0 Receive Octets Counter(iflnOctetsn) */ 529 /*! @{ */ 530 531 #define SW_ETH_MAC_PORT0_PM0_ROCTN_ROCTn_MASK (0xFFFFFFFFFFFFFFFFU) 532 #define SW_ETH_MAC_PORT0_PM0_ROCTN_ROCTn_SHIFT (0U) 533 #define SW_ETH_MAC_PORT0_PM0_ROCTN_ROCTn_WIDTH (64U) 534 #define SW_ETH_MAC_PORT0_PM0_ROCTN_ROCTn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_ROCTN_ROCTn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_ROCTN_ROCTn_MASK) 535 /*! @} */ 536 537 /*! @name PM0_RXPFN - Port MAC 0 Receive Valid Pause Frame Counter Register(aPAUSEMACCtrlFramesReceivedn) */ 538 /*! @{ */ 539 540 #define SW_ETH_MAC_PORT0_PM0_RXPFN_RXPFn_MASK (0xFFFFFFFFFFFFFFFFU) 541 #define SW_ETH_MAC_PORT0_PM0_RXPFN_RXPFn_SHIFT (0U) 542 #define SW_ETH_MAC_PORT0_PM0_RXPFN_RXPFn_WIDTH (64U) 543 #define SW_ETH_MAC_PORT0_PM0_RXPFN_RXPFn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_RXPFN_RXPFn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_RXPFN_RXPFn_MASK) 544 /*! @} */ 545 546 /*! @name PM0_RFRMN - Port MAC 0 Receive Frame Counter Register(aFramesReceivedOKn) */ 547 /*! @{ */ 548 549 #define SW_ETH_MAC_PORT0_PM0_RFRMN_RFRMn_MASK (0xFFFFFFFFFFFFFFFFU) 550 #define SW_ETH_MAC_PORT0_PM0_RFRMN_RFRMn_SHIFT (0U) 551 #define SW_ETH_MAC_PORT0_PM0_RFRMN_RFRMn_WIDTH (64U) 552 #define SW_ETH_MAC_PORT0_PM0_RFRMN_RFRMn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_RFRMN_RFRMn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_RFRMN_RFRMn_MASK) 553 /*! @} */ 554 555 /*! @name PM0_RFCSN - Port MAC 0 Receive Frame Check Sequence Error Counter Register() */ 556 /*! @{ */ 557 558 #define SW_ETH_MAC_PORT0_PM0_RFCSN_RFCSn_MASK (0xFFFFFFFFFFFFFFFFU) 559 #define SW_ETH_MAC_PORT0_PM0_RFCSN_RFCSn_SHIFT (0U) 560 #define SW_ETH_MAC_PORT0_PM0_RFCSN_RFCSn_WIDTH (64U) 561 #define SW_ETH_MAC_PORT0_PM0_RFCSN_RFCSn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_RFCSN_RFCSn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_RFCSN_RFCSn_MASK) 562 /*! @} */ 563 564 /*! @name PM0_RVLANN - Port MAC 0 Receive VLAN Frame Counter Register(VLANReceivedOKn) */ 565 /*! @{ */ 566 567 #define SW_ETH_MAC_PORT0_PM0_RVLANN_RVLANn_MASK (0xFFFFFFFFFFFFFFFFU) 568 #define SW_ETH_MAC_PORT0_PM0_RVLANN_RVLANn_SHIFT (0U) 569 #define SW_ETH_MAC_PORT0_PM0_RVLANN_RVLANn_WIDTH (64U) 570 #define SW_ETH_MAC_PORT0_PM0_RVLANN_RVLANn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_RVLANN_RVLANn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_RVLANN_RVLANn_MASK) 571 /*! @} */ 572 573 /*! @name PM0_RERRN - Port MAC 0 Receive Frame Error Counter Register(ifInErrorsn) */ 574 /*! @{ */ 575 576 #define SW_ETH_MAC_PORT0_PM0_RERRN_RERRn_MASK (0xFFFFFFFFFFFFFFFFU) 577 #define SW_ETH_MAC_PORT0_PM0_RERRN_RERRn_SHIFT (0U) 578 #define SW_ETH_MAC_PORT0_PM0_RERRN_RERRn_WIDTH (64U) 579 #define SW_ETH_MAC_PORT0_PM0_RERRN_RERRn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_RERRN_RERRn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_RERRN_RERRn_MASK) 580 /*! @} */ 581 582 /*! @name PM0_RUCAN - Port MAC 0 Receive Unicast Frame Counter Register(ifInUcastPktsn) */ 583 /*! @{ */ 584 585 #define SW_ETH_MAC_PORT0_PM0_RUCAN_RUCAn_MASK (0xFFFFFFFFFFFFFFFFU) 586 #define SW_ETH_MAC_PORT0_PM0_RUCAN_RUCAn_SHIFT (0U) 587 #define SW_ETH_MAC_PORT0_PM0_RUCAN_RUCAn_WIDTH (64U) 588 #define SW_ETH_MAC_PORT0_PM0_RUCAN_RUCAn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_RUCAN_RUCAn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_RUCAN_RUCAn_MASK) 589 /*! @} */ 590 591 /*! @name PM0_RMCAN - Port MAC 0 Receive Multicast Frame Counter Register(ifInMulticastPktsn) */ 592 /*! @{ */ 593 594 #define SW_ETH_MAC_PORT0_PM0_RMCAN_RMCAn_MASK (0xFFFFFFFFFFFFFFFFU) 595 #define SW_ETH_MAC_PORT0_PM0_RMCAN_RMCAn_SHIFT (0U) 596 #define SW_ETH_MAC_PORT0_PM0_RMCAN_RMCAn_WIDTH (64U) 597 #define SW_ETH_MAC_PORT0_PM0_RMCAN_RMCAn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_RMCAN_RMCAn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_RMCAN_RMCAn_MASK) 598 /*! @} */ 599 600 /*! @name PM0_RBCAN - Port MAC 0 Receive Broadcast Frame Counter Register(ifInBroadcastPktsn) */ 601 /*! @{ */ 602 603 #define SW_ETH_MAC_PORT0_PM0_RBCAN_RBCAn_MASK (0xFFFFFFFFFFFFFFFFU) 604 #define SW_ETH_MAC_PORT0_PM0_RBCAN_RBCAn_SHIFT (0U) 605 #define SW_ETH_MAC_PORT0_PM0_RBCAN_RBCAn_WIDTH (64U) 606 #define SW_ETH_MAC_PORT0_PM0_RBCAN_RBCAn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_RBCAN_RBCAn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_RBCAN_RBCAn_MASK) 607 /*! @} */ 608 609 /*! @name PM0_RDRPN - Port MAC 0 Receive Dropped Packets Counter Register(etherStatsDropEventsn) */ 610 /*! @{ */ 611 612 #define SW_ETH_MAC_PORT0_PM0_RDRPN_RDRPn_MASK (0xFFFFFFFFFFFFFFFFU) 613 #define SW_ETH_MAC_PORT0_PM0_RDRPN_RDRPn_SHIFT (0U) 614 #define SW_ETH_MAC_PORT0_PM0_RDRPN_RDRPn_WIDTH (64U) 615 #define SW_ETH_MAC_PORT0_PM0_RDRPN_RDRPn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_RDRPN_RDRPn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_RDRPN_RDRPn_MASK) 616 /*! @} */ 617 618 /*! @name PM0_RPKTN - Port MAC 0 Receive Packets Counter Register(etherStatsPktsn) */ 619 /*! @{ */ 620 621 #define SW_ETH_MAC_PORT0_PM0_RPKTN_RPKTn_MASK (0xFFFFFFFFFFFFFFFFU) 622 #define SW_ETH_MAC_PORT0_PM0_RPKTN_RPKTn_SHIFT (0U) 623 #define SW_ETH_MAC_PORT0_PM0_RPKTN_RPKTn_WIDTH (64U) 624 #define SW_ETH_MAC_PORT0_PM0_RPKTN_RPKTn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_RPKTN_RPKTn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_RPKTN_RPKTn_MASK) 625 /*! @} */ 626 627 /*! @name PM0_RUNDN - Port MAC 0 Receive Undersized Packet Counter Register(etherStatsUndersizePktsn) */ 628 /*! @{ */ 629 630 #define SW_ETH_MAC_PORT0_PM0_RUNDN_RUNDn_MASK (0xFFFFFFFFFFFFFFFFU) 631 #define SW_ETH_MAC_PORT0_PM0_RUNDN_RUNDn_SHIFT (0U) 632 #define SW_ETH_MAC_PORT0_PM0_RUNDN_RUNDn_WIDTH (64U) 633 #define SW_ETH_MAC_PORT0_PM0_RUNDN_RUNDn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_RUNDN_RUNDn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_RUNDN_RUNDn_MASK) 634 /*! @} */ 635 636 /*! @name PM0_R64N - Port MAC 0 Receive 64-Octet Packet Counter Register(etherStatsPkts64OctetsN) */ 637 /*! @{ */ 638 639 #define SW_ETH_MAC_PORT0_PM0_R64N_R64n_MASK (0xFFFFFFFFFFFFFFFFU) 640 #define SW_ETH_MAC_PORT0_PM0_R64N_R64n_SHIFT (0U) 641 #define SW_ETH_MAC_PORT0_PM0_R64N_R64n_WIDTH (64U) 642 #define SW_ETH_MAC_PORT0_PM0_R64N_R64n(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_R64N_R64n_SHIFT)) & SW_ETH_MAC_PORT0_PM0_R64N_R64n_MASK) 643 /*! @} */ 644 645 /*! @name PM0_R127N - Port MAC 0 Receive 65 to 127-Octet Packet Counter Register(etherStatsPkts65to127OctetsN) */ 646 /*! @{ */ 647 648 #define SW_ETH_MAC_PORT0_PM0_R127N_R127n_MASK (0xFFFFFFFFFFFFFFFFU) 649 #define SW_ETH_MAC_PORT0_PM0_R127N_R127n_SHIFT (0U) 650 #define SW_ETH_MAC_PORT0_PM0_R127N_R127n_WIDTH (64U) 651 #define SW_ETH_MAC_PORT0_PM0_R127N_R127n(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_R127N_R127n_SHIFT)) & SW_ETH_MAC_PORT0_PM0_R127N_R127n_MASK) 652 /*! @} */ 653 654 /*! @name PM0_R255N - Port MAC 0 Receive 128 to 255-Octet Packet Counter Register(etherStatsPkts128to255OctetsN) */ 655 /*! @{ */ 656 657 #define SW_ETH_MAC_PORT0_PM0_R255N_R255n_MASK (0xFFFFFFFFFFFFFFFFU) 658 #define SW_ETH_MAC_PORT0_PM0_R255N_R255n_SHIFT (0U) 659 #define SW_ETH_MAC_PORT0_PM0_R255N_R255n_WIDTH (64U) 660 #define SW_ETH_MAC_PORT0_PM0_R255N_R255n(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_R255N_R255n_SHIFT)) & SW_ETH_MAC_PORT0_PM0_R255N_R255n_MASK) 661 /*! @} */ 662 663 /*! @name PM0_R511N - Port MAC 0 Receive 256 to 511-Octet Packet Counter Register(etherStatsPkts256to511OctetsN) */ 664 /*! @{ */ 665 666 #define SW_ETH_MAC_PORT0_PM0_R511N_R511n_MASK (0xFFFFFFFFFFFFFFFFU) 667 #define SW_ETH_MAC_PORT0_PM0_R511N_R511n_SHIFT (0U) 668 #define SW_ETH_MAC_PORT0_PM0_R511N_R511n_WIDTH (64U) 669 #define SW_ETH_MAC_PORT0_PM0_R511N_R511n(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_R511N_R511n_SHIFT)) & SW_ETH_MAC_PORT0_PM0_R511N_R511n_MASK) 670 /*! @} */ 671 672 /*! @name PM0_R1023N - Port MAC 0 Receive 512 to 1023-Octet Packet Counter Register(etherStatsPkts512to1023OctetsN) */ 673 /*! @{ */ 674 675 #define SW_ETH_MAC_PORT0_PM0_R1023N_R1023n_MASK (0xFFFFFFFFFFFFFFFFU) 676 #define SW_ETH_MAC_PORT0_PM0_R1023N_R1023n_SHIFT (0U) 677 #define SW_ETH_MAC_PORT0_PM0_R1023N_R1023n_WIDTH (64U) 678 #define SW_ETH_MAC_PORT0_PM0_R1023N_R1023n(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_R1023N_R1023n_SHIFT)) & SW_ETH_MAC_PORT0_PM0_R1023N_R1023n_MASK) 679 /*! @} */ 680 681 /*! @name PM0_R1522N - Port MAC 0 Receive 1024 to 1522-Octet Packet Counter Register(etherStatsPkts1024to1522OctetsN) */ 682 /*! @{ */ 683 684 #define SW_ETH_MAC_PORT0_PM0_R1522N_R1522n_MASK (0xFFFFFFFFFFFFFFFFU) 685 #define SW_ETH_MAC_PORT0_PM0_R1522N_R1522n_SHIFT (0U) 686 #define SW_ETH_MAC_PORT0_PM0_R1522N_R1522n_WIDTH (64U) 687 #define SW_ETH_MAC_PORT0_PM0_R1522N_R1522n(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_R1522N_R1522n_SHIFT)) & SW_ETH_MAC_PORT0_PM0_R1522N_R1522n_MASK) 688 /*! @} */ 689 690 /*! @name PM0_R1523XN - Port MAC 0 Receive 1523 to Max-Octet Packet Counter Register(etherStatsPkts1523toMaxOctetsN) */ 691 /*! @{ */ 692 693 #define SW_ETH_MAC_PORT0_PM0_R1523XN_R1523Xn_MASK (0xFFFFFFFFFFFFFFFFU) 694 #define SW_ETH_MAC_PORT0_PM0_R1523XN_R1523Xn_SHIFT (0U) 695 #define SW_ETH_MAC_PORT0_PM0_R1523XN_R1523Xn_WIDTH (64U) 696 #define SW_ETH_MAC_PORT0_PM0_R1523XN_R1523Xn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_R1523XN_R1523Xn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_R1523XN_R1523Xn_MASK) 697 /*! @} */ 698 699 /*! @name PM0_ROVRN - Port MAC 0 Receive Oversized Packet Counter Register(etherStatsOversizePktsn) */ 700 /*! @{ */ 701 702 #define SW_ETH_MAC_PORT0_PM0_ROVRN_ROVRn_MASK (0xFFFFFFFFFFFFFFFFU) 703 #define SW_ETH_MAC_PORT0_PM0_ROVRN_ROVRn_SHIFT (0U) 704 #define SW_ETH_MAC_PORT0_PM0_ROVRN_ROVRn_WIDTH (64U) 705 #define SW_ETH_MAC_PORT0_PM0_ROVRN_ROVRn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_ROVRN_ROVRn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_ROVRN_ROVRn_MASK) 706 /*! @} */ 707 708 /*! @name PM0_RJBRN - Port MAC 0 Receive Jabber Packet Counter Register(etherStatsJabbersn) */ 709 /*! @{ */ 710 711 #define SW_ETH_MAC_PORT0_PM0_RJBRN_RJBRn_MASK (0xFFFFFFFFFFFFFFFFU) 712 #define SW_ETH_MAC_PORT0_PM0_RJBRN_RJBRn_SHIFT (0U) 713 #define SW_ETH_MAC_PORT0_PM0_RJBRN_RJBRn_WIDTH (64U) 714 #define SW_ETH_MAC_PORT0_PM0_RJBRN_RJBRn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_RJBRN_RJBRn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_RJBRN_RJBRn_MASK) 715 /*! @} */ 716 717 /*! @name PM0_RFRGN - Port MAC 0 Receive Fragment Packet Counter Register(etherStatsFragmentsn */ 718 /*! @{ */ 719 720 #define SW_ETH_MAC_PORT0_PM0_RFRGN_RFRGn_MASK (0xFFFFFFFFFFFFFFFFU) 721 #define SW_ETH_MAC_PORT0_PM0_RFRGN_RFRGn_SHIFT (0U) 722 #define SW_ETH_MAC_PORT0_PM0_RFRGN_RFRGn_WIDTH (64U) 723 #define SW_ETH_MAC_PORT0_PM0_RFRGN_RFRGn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_RFRGN_RFRGn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_RFRGN_RFRGn_MASK) 724 /*! @} */ 725 726 /*! @name PM0_RCNPN - Port MAC 0 Receive Control Packet Counter Register */ 727 /*! @{ */ 728 729 #define SW_ETH_MAC_PORT0_PM0_RCNPN_RCNPn_MASK (0xFFFFFFFFFFFFFFFFU) 730 #define SW_ETH_MAC_PORT0_PM0_RCNPN_RCNPn_SHIFT (0U) 731 #define SW_ETH_MAC_PORT0_PM0_RCNPN_RCNPn_WIDTH (64U) 732 #define SW_ETH_MAC_PORT0_PM0_RCNPN_RCNPn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_RCNPN_RCNPn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_RCNPN_RCNPn_MASK) 733 /*! @} */ 734 735 /*! @name PM0_RDRNTPN - Port MAC 0 Receive Dropped Not Truncated Packets Counter Register(etherStatsDropEventsn) */ 736 /*! @{ */ 737 738 #define SW_ETH_MAC_PORT0_PM0_RDRNTPN_RDRNTPn_MASK (0xFFFFFFFFFFFFFFFFU) 739 #define SW_ETH_MAC_PORT0_PM0_RDRNTPN_RDRNTPn_SHIFT (0U) 740 #define SW_ETH_MAC_PORT0_PM0_RDRNTPN_RDRNTPn_WIDTH (64U) 741 #define SW_ETH_MAC_PORT0_PM0_RDRNTPN_RDRNTPn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_RDRNTPN_RDRNTPn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_RDRNTPN_RDRNTPn_MASK) 742 /*! @} */ 743 744 /*! @name PM0_TEOCTN - Port MAC 0 Transmit Ethernet Octets Counter(etherStatsOctetsn) */ 745 /*! @{ */ 746 747 #define SW_ETH_MAC_PORT0_PM0_TEOCTN_TEOCTn_MASK (0xFFFFFFFFFFFFFFFFU) 748 #define SW_ETH_MAC_PORT0_PM0_TEOCTN_TEOCTn_SHIFT (0U) 749 #define SW_ETH_MAC_PORT0_PM0_TEOCTN_TEOCTn_WIDTH (64U) 750 #define SW_ETH_MAC_PORT0_PM0_TEOCTN_TEOCTn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_TEOCTN_TEOCTn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_TEOCTN_TEOCTn_MASK) 751 /*! @} */ 752 753 /*! @name PM0_TOCTN - Port MAC 0 Transmit Octets Counter Register(ifOutOctetsn) */ 754 /*! @{ */ 755 756 #define SW_ETH_MAC_PORT0_PM0_TOCTN_TOCTn_MASK (0xFFFFFFFFFFFFFFFFU) 757 #define SW_ETH_MAC_PORT0_PM0_TOCTN_TOCTn_SHIFT (0U) 758 #define SW_ETH_MAC_PORT0_PM0_TOCTN_TOCTn_WIDTH (64U) 759 #define SW_ETH_MAC_PORT0_PM0_TOCTN_TOCTn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_TOCTN_TOCTn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_TOCTN_TOCTn_MASK) 760 /*! @} */ 761 762 /*! @name PM0_TXPFN - Port MAC 0 Transmit Valid Pause Frame Counter Register(aPAUSEMACCtrlFramesReceivedn) */ 763 /*! @{ */ 764 765 #define SW_ETH_MAC_PORT0_PM0_TXPFN_TXPFn_MASK (0xFFFFFFFFFFFFFFFFU) 766 #define SW_ETH_MAC_PORT0_PM0_TXPFN_TXPFn_SHIFT (0U) 767 #define SW_ETH_MAC_PORT0_PM0_TXPFN_TXPFn_WIDTH (64U) 768 #define SW_ETH_MAC_PORT0_PM0_TXPFN_TXPFn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_TXPFN_TXPFn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_TXPFN_TXPFn_MASK) 769 /*! @} */ 770 771 /*! @name PM0_TFRMN - Port MAC 0 Transmit Frame Counter Register(aFramesTransmittedOKn) */ 772 /*! @{ */ 773 774 #define SW_ETH_MAC_PORT0_PM0_TFRMN_TFRMn_MASK (0xFFFFFFFFFFFFFFFFU) 775 #define SW_ETH_MAC_PORT0_PM0_TFRMN_TFRMn_SHIFT (0U) 776 #define SW_ETH_MAC_PORT0_PM0_TFRMN_TFRMn_WIDTH (64U) 777 #define SW_ETH_MAC_PORT0_PM0_TFRMN_TFRMn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_TFRMN_TFRMn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_TFRMN_TFRMn_MASK) 778 /*! @} */ 779 780 /*! @name PM0_TFCSN - Port MAC 0 Transmit Frame Check Sequence Error Counter Register() */ 781 /*! @{ */ 782 783 #define SW_ETH_MAC_PORT0_PM0_TFCSN_TFCSn_MASK (0xFFFFFFFFFFFFFFFFU) 784 #define SW_ETH_MAC_PORT0_PM0_TFCSN_TFCSn_SHIFT (0U) 785 #define SW_ETH_MAC_PORT0_PM0_TFCSN_TFCSn_WIDTH (64U) 786 #define SW_ETH_MAC_PORT0_PM0_TFCSN_TFCSn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_TFCSN_TFCSn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_TFCSN_TFCSn_MASK) 787 /*! @} */ 788 789 /*! @name PM0_TVLANN - Port MAC 0 Transmit VLAN Frame Counter Register(VLANTransmittedOKn) */ 790 /*! @{ */ 791 792 #define SW_ETH_MAC_PORT0_PM0_TVLANN_TVLANn_MASK (0xFFFFFFFFFFFFFFFFU) 793 #define SW_ETH_MAC_PORT0_PM0_TVLANN_TVLANn_SHIFT (0U) 794 #define SW_ETH_MAC_PORT0_PM0_TVLANN_TVLANn_WIDTH (64U) 795 #define SW_ETH_MAC_PORT0_PM0_TVLANN_TVLANn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_TVLANN_TVLANn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_TVLANN_TVLANn_MASK) 796 /*! @} */ 797 798 /*! @name PM0_TERRN - Port MAC 0 Transmit Frame Error Counter Register(ifOutErrorsn) */ 799 /*! @{ */ 800 801 #define SW_ETH_MAC_PORT0_PM0_TERRN_TERRn_MASK (0xFFFFFFFFFFFFFFFFU) 802 #define SW_ETH_MAC_PORT0_PM0_TERRN_TERRn_SHIFT (0U) 803 #define SW_ETH_MAC_PORT0_PM0_TERRN_TERRn_WIDTH (64U) 804 #define SW_ETH_MAC_PORT0_PM0_TERRN_TERRn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_TERRN_TERRn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_TERRN_TERRn_MASK) 805 /*! @} */ 806 807 /*! @name PM0_TUCAN - Port MAC 0 Transmit Unicast Frame Counter Register(ifOutUcastPktsn) */ 808 /*! @{ */ 809 810 #define SW_ETH_MAC_PORT0_PM0_TUCAN_TUCAn_MASK (0xFFFFFFFFFFFFFFFFU) 811 #define SW_ETH_MAC_PORT0_PM0_TUCAN_TUCAn_SHIFT (0U) 812 #define SW_ETH_MAC_PORT0_PM0_TUCAN_TUCAn_WIDTH (64U) 813 #define SW_ETH_MAC_PORT0_PM0_TUCAN_TUCAn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_TUCAN_TUCAn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_TUCAN_TUCAn_MASK) 814 /*! @} */ 815 816 /*! @name PM0_TMCAN - Port MAC 0 Transmit Multicast Frame Counter Register(ifOutMulticastPktsn) */ 817 /*! @{ */ 818 819 #define SW_ETH_MAC_PORT0_PM0_TMCAN_TMCAn_MASK (0xFFFFFFFFFFFFFFFFU) 820 #define SW_ETH_MAC_PORT0_PM0_TMCAN_TMCAn_SHIFT (0U) 821 #define SW_ETH_MAC_PORT0_PM0_TMCAN_TMCAn_WIDTH (64U) 822 #define SW_ETH_MAC_PORT0_PM0_TMCAN_TMCAn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_TMCAN_TMCAn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_TMCAN_TMCAn_MASK) 823 /*! @} */ 824 825 /*! @name PM0_TBCAN - Port MAC 0 Transmit Broadcast Frame Counter Register(ifOutBroadcastPktsn) */ 826 /*! @{ */ 827 828 #define SW_ETH_MAC_PORT0_PM0_TBCAN_TBCAn_MASK (0xFFFFFFFFFFFFFFFFU) 829 #define SW_ETH_MAC_PORT0_PM0_TBCAN_TBCAn_SHIFT (0U) 830 #define SW_ETH_MAC_PORT0_PM0_TBCAN_TBCAn_WIDTH (64U) 831 #define SW_ETH_MAC_PORT0_PM0_TBCAN_TBCAn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_TBCAN_TBCAn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_TBCAN_TBCAn_MASK) 832 /*! @} */ 833 834 /*! @name PM0_TPKTN - Port MAC 0 Transmit Packets Counter Register(etherStatsPktsn) */ 835 /*! @{ */ 836 837 #define SW_ETH_MAC_PORT0_PM0_TPKTN_TPKTn_MASK (0xFFFFFFFFFFFFFFFFU) 838 #define SW_ETH_MAC_PORT0_PM0_TPKTN_TPKTn_SHIFT (0U) 839 #define SW_ETH_MAC_PORT0_PM0_TPKTN_TPKTn_WIDTH (64U) 840 #define SW_ETH_MAC_PORT0_PM0_TPKTN_TPKTn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_TPKTN_TPKTn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_TPKTN_TPKTn_MASK) 841 /*! @} */ 842 843 /*! @name PM0_TUNDN - Port MAC 0 Transmit Undersized Packet Counter Register(etherStatsUndersizePktsn) */ 844 /*! @{ */ 845 846 #define SW_ETH_MAC_PORT0_PM0_TUNDN_TUNDn_MASK (0xFFFFFFFFFFFFFFFFU) 847 #define SW_ETH_MAC_PORT0_PM0_TUNDN_TUNDn_SHIFT (0U) 848 #define SW_ETH_MAC_PORT0_PM0_TUNDN_TUNDn_WIDTH (64U) 849 #define SW_ETH_MAC_PORT0_PM0_TUNDN_TUNDn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_TUNDN_TUNDn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_TUNDN_TUNDn_MASK) 850 /*! @} */ 851 852 /*! @name PM0_T64N - Port MAC 0 Transmit 64-Octet Packet Counter Register (etherStatsPkts64OctetsN) */ 853 /*! @{ */ 854 855 #define SW_ETH_MAC_PORT0_PM0_T64N_T64n_MASK (0xFFFFFFFFFFFFFFFFU) 856 #define SW_ETH_MAC_PORT0_PM0_T64N_T64n_SHIFT (0U) 857 #define SW_ETH_MAC_PORT0_PM0_T64N_T64n_WIDTH (64U) 858 #define SW_ETH_MAC_PORT0_PM0_T64N_T64n(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_T64N_T64n_SHIFT)) & SW_ETH_MAC_PORT0_PM0_T64N_T64n_MASK) 859 /*! @} */ 860 861 /*! @name PM0_T127N - Port MAC 0 Transmit 65 to 127-Octet Packet Counter Register (etherStatsPkts65to127OctetsN) */ 862 /*! @{ */ 863 864 #define SW_ETH_MAC_PORT0_PM0_T127N_T127n_MASK (0xFFFFFFFFFFFFFFFFU) 865 #define SW_ETH_MAC_PORT0_PM0_T127N_T127n_SHIFT (0U) 866 #define SW_ETH_MAC_PORT0_PM0_T127N_T127n_WIDTH (64U) 867 #define SW_ETH_MAC_PORT0_PM0_T127N_T127n(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_T127N_T127n_SHIFT)) & SW_ETH_MAC_PORT0_PM0_T127N_T127n_MASK) 868 /*! @} */ 869 870 /*! @name PM0_T255N - Port MAC 0 Transmit 128 to 255-Octet Packet Counter Register (etherStatsPkts128to255OctetsN) */ 871 /*! @{ */ 872 873 #define SW_ETH_MAC_PORT0_PM0_T255N_T255n_MASK (0xFFFFFFFFFFFFFFFFU) 874 #define SW_ETH_MAC_PORT0_PM0_T255N_T255n_SHIFT (0U) 875 #define SW_ETH_MAC_PORT0_PM0_T255N_T255n_WIDTH (64U) 876 #define SW_ETH_MAC_PORT0_PM0_T255N_T255n(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_T255N_T255n_SHIFT)) & SW_ETH_MAC_PORT0_PM0_T255N_T255n_MASK) 877 /*! @} */ 878 879 /*! @name PM0_T511N - Port MAC 0 Transmit 256 to 511-Octet Packet Counter Register (etherStatsPkts256to511OctetsN) */ 880 /*! @{ */ 881 882 #define SW_ETH_MAC_PORT0_PM0_T511N_T511n_MASK (0xFFFFFFFFFFFFFFFFU) 883 #define SW_ETH_MAC_PORT0_PM0_T511N_T511n_SHIFT (0U) 884 #define SW_ETH_MAC_PORT0_PM0_T511N_T511n_WIDTH (64U) 885 #define SW_ETH_MAC_PORT0_PM0_T511N_T511n(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_T511N_T511n_SHIFT)) & SW_ETH_MAC_PORT0_PM0_T511N_T511n_MASK) 886 /*! @} */ 887 888 /*! @name PM0_T1023N - Port MAC 0 Transmit 512 to 1023-Octet Packet Counter Register (etherStatsPkts512to1023OctetsN) */ 889 /*! @{ */ 890 891 #define SW_ETH_MAC_PORT0_PM0_T1023N_T1023n_MASK (0xFFFFFFFFFFFFFFFFU) 892 #define SW_ETH_MAC_PORT0_PM0_T1023N_T1023n_SHIFT (0U) 893 #define SW_ETH_MAC_PORT0_PM0_T1023N_T1023n_WIDTH (64U) 894 #define SW_ETH_MAC_PORT0_PM0_T1023N_T1023n(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_T1023N_T1023n_SHIFT)) & SW_ETH_MAC_PORT0_PM0_T1023N_T1023n_MASK) 895 /*! @} */ 896 897 /*! @name PM0_T1522N - Port MAC 0 Transmit 1024 to 1522-Octet Packet Counter Register (etherStatsPkts1024to1522OctetsN) */ 898 /*! @{ */ 899 900 #define SW_ETH_MAC_PORT0_PM0_T1522N_T1522n_MASK (0xFFFFFFFFFFFFFFFFU) 901 #define SW_ETH_MAC_PORT0_PM0_T1522N_T1522n_SHIFT (0U) 902 #define SW_ETH_MAC_PORT0_PM0_T1522N_T1522n_WIDTH (64U) 903 #define SW_ETH_MAC_PORT0_PM0_T1522N_T1522n(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_T1522N_T1522n_SHIFT)) & SW_ETH_MAC_PORT0_PM0_T1522N_T1522n_MASK) 904 /*! @} */ 905 906 /*! @name PM0_T1523XN - Port MAC 0 Transmit 1523 to TX_MTU-Octet Packet Counter Register (etherStatsPkts1523toMaxOctetsN) */ 907 /*! @{ */ 908 909 #define SW_ETH_MAC_PORT0_PM0_T1523XN_T1523Xn_MASK (0xFFFFFFFFFFFFFFFFU) 910 #define SW_ETH_MAC_PORT0_PM0_T1523XN_T1523Xn_SHIFT (0U) 911 #define SW_ETH_MAC_PORT0_PM0_T1523XN_T1523Xn_WIDTH (64U) 912 #define SW_ETH_MAC_PORT0_PM0_T1523XN_T1523Xn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_T1523XN_T1523Xn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_T1523XN_T1523Xn_MASK) 913 /*! @} */ 914 915 /*! @name PM0_TCNPN - Port MAC 0 Transmit Control Packet Counter Register */ 916 /*! @{ */ 917 918 #define SW_ETH_MAC_PORT0_PM0_TCNPN_TCNPn_MASK (0xFFFFFFFFFFFFFFFFU) 919 #define SW_ETH_MAC_PORT0_PM0_TCNPN_TCNPn_SHIFT (0U) 920 #define SW_ETH_MAC_PORT0_PM0_TCNPN_TCNPn_WIDTH (64U) 921 #define SW_ETH_MAC_PORT0_PM0_TCNPN_TCNPn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_TCNPN_TCNPn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_TCNPN_TCNPn_MASK) 922 /*! @} */ 923 924 /*! @name PM0_TDFRN - Port MAC 0 Transmit Deferred Packet Counter Register(aFramesWithDeferredXmissions) */ 925 /*! @{ */ 926 927 #define SW_ETH_MAC_PORT0_PM0_TDFRN_TDFRn_MASK (0xFFFFFFFFFFFFFFFFU) 928 #define SW_ETH_MAC_PORT0_PM0_TDFRN_TDFRn_SHIFT (0U) 929 #define SW_ETH_MAC_PORT0_PM0_TDFRN_TDFRn_WIDTH (64U) 930 #define SW_ETH_MAC_PORT0_PM0_TDFRN_TDFRn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_TDFRN_TDFRn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_TDFRN_TDFRn_MASK) 931 /*! @} */ 932 933 /*! @name PM0_TMCOLN - Port MAC 0 Transmit Multiple Collisions Counter Register(aMultipleCollisionFrames) */ 934 /*! @{ */ 935 936 #define SW_ETH_MAC_PORT0_PM0_TMCOLN_TMCOLn_MASK (0xFFFFFFFFFFFFFFFFU) 937 #define SW_ETH_MAC_PORT0_PM0_TMCOLN_TMCOLn_SHIFT (0U) 938 #define SW_ETH_MAC_PORT0_PM0_TMCOLN_TMCOLn_WIDTH (64U) 939 #define SW_ETH_MAC_PORT0_PM0_TMCOLN_TMCOLn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_TMCOLN_TMCOLn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_TMCOLN_TMCOLn_MASK) 940 /*! @} */ 941 942 /*! @name PM0_TSCOLN - Port MAC 0 Transmit Single Collision Counter(aSingleCollisionFrames) Register */ 943 /*! @{ */ 944 945 #define SW_ETH_MAC_PORT0_PM0_TSCOLN_TSCOLn_MASK (0xFFFFFFFFFFFFFFFFU) 946 #define SW_ETH_MAC_PORT0_PM0_TSCOLN_TSCOLn_SHIFT (0U) 947 #define SW_ETH_MAC_PORT0_PM0_TSCOLN_TSCOLn_WIDTH (64U) 948 #define SW_ETH_MAC_PORT0_PM0_TSCOLN_TSCOLn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_TSCOLN_TSCOLn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_TSCOLN_TSCOLn_MASK) 949 /*! @} */ 950 951 /*! @name PM0_TLCOLN - Port MAC 0 Transmit Late Collision Counter(aLateCollisions) Register */ 952 /*! @{ */ 953 954 #define SW_ETH_MAC_PORT0_PM0_TLCOLN_TLCOLn_MASK (0xFFFFFFFFFFFFFFFFU) 955 #define SW_ETH_MAC_PORT0_PM0_TLCOLN_TLCOLn_SHIFT (0U) 956 #define SW_ETH_MAC_PORT0_PM0_TLCOLN_TLCOLn_WIDTH (64U) 957 #define SW_ETH_MAC_PORT0_PM0_TLCOLN_TLCOLn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_TLCOLN_TLCOLn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_TLCOLN_TLCOLn_MASK) 958 /*! @} */ 959 960 /*! @name PM0_TECOLN - Port MAC 0 Transmit Excessive Collisions Counter Register */ 961 /*! @{ */ 962 963 #define SW_ETH_MAC_PORT0_PM0_TECOLN_TECOLn_MASK (0xFFFFFFFFFFFFFFFFU) 964 #define SW_ETH_MAC_PORT0_PM0_TECOLN_TECOLn_SHIFT (0U) 965 #define SW_ETH_MAC_PORT0_PM0_TECOLN_TECOLn_WIDTH (64U) 966 #define SW_ETH_MAC_PORT0_PM0_TECOLN_TECOLn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_TECOLN_TECOLn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_TECOLN_TECOLn_MASK) 967 /*! @} */ 968 969 /*! @name PM0_IF_MODE - Port MAC 0 Interface Mode Control Register */ 970 /*! @{ */ 971 972 #define SW_ETH_MAC_PORT0_PM0_IF_MODE_IFMODE_MASK (0x7U) 973 #define SW_ETH_MAC_PORT0_PM0_IF_MODE_IFMODE_SHIFT (0U) 974 #define SW_ETH_MAC_PORT0_PM0_IF_MODE_IFMODE_WIDTH (3U) 975 #define SW_ETH_MAC_PORT0_PM0_IF_MODE_IFMODE(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_IF_MODE_IFMODE_SHIFT)) & SW_ETH_MAC_PORT0_PM0_IF_MODE_IFMODE_MASK) 976 977 #define SW_ETH_MAC_PORT0_PM0_IF_MODE_REVMII_MASK (0x8U) 978 #define SW_ETH_MAC_PORT0_PM0_IF_MODE_REVMII_SHIFT (3U) 979 #define SW_ETH_MAC_PORT0_PM0_IF_MODE_REVMII_WIDTH (1U) 980 #define SW_ETH_MAC_PORT0_PM0_IF_MODE_REVMII(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_IF_MODE_REVMII_SHIFT)) & SW_ETH_MAC_PORT0_PM0_IF_MODE_REVMII_MASK) 981 982 #define SW_ETH_MAC_PORT0_PM0_IF_MODE_M10_MASK (0x10U) 983 #define SW_ETH_MAC_PORT0_PM0_IF_MODE_M10_SHIFT (4U) 984 #define SW_ETH_MAC_PORT0_PM0_IF_MODE_M10_WIDTH (1U) 985 #define SW_ETH_MAC_PORT0_PM0_IF_MODE_M10(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_IF_MODE_M10_SHIFT)) & SW_ETH_MAC_PORT0_PM0_IF_MODE_M10_MASK) 986 987 #define SW_ETH_MAC_PORT0_PM0_IF_MODE_HD_MASK (0x40U) 988 #define SW_ETH_MAC_PORT0_PM0_IF_MODE_HD_SHIFT (6U) 989 #define SW_ETH_MAC_PORT0_PM0_IF_MODE_HD_WIDTH (1U) 990 #define SW_ETH_MAC_PORT0_PM0_IF_MODE_HD(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_IF_MODE_HD_SHIFT)) & SW_ETH_MAC_PORT0_PM0_IF_MODE_HD_MASK) 991 992 #define SW_ETH_MAC_PORT0_PM0_IF_MODE_SSP_MASK (0x6000U) 993 #define SW_ETH_MAC_PORT0_PM0_IF_MODE_SSP_SHIFT (13U) 994 #define SW_ETH_MAC_PORT0_PM0_IF_MODE_SSP_WIDTH (2U) 995 #define SW_ETH_MAC_PORT0_PM0_IF_MODE_SSP(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_IF_MODE_SSP_SHIFT)) & SW_ETH_MAC_PORT0_PM0_IF_MODE_SSP_MASK) 996 /*! @} */ 997 998 /*! @name PM1_COMMAND_CONFIG - Port MAC 1 Command and Configuration Register */ 999 /*! @{ */ 1000 1001 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TX_EN_MASK (0x1U) 1002 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TX_EN_SHIFT (0U) 1003 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TX_EN_WIDTH (1U) 1004 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TX_EN_SHIFT)) & SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TX_EN_MASK) 1005 1006 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_RX_EN_MASK (0x2U) 1007 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_RX_EN_SHIFT (1U) 1008 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_RX_EN_WIDTH (1U) 1009 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_RX_EN_SHIFT)) & SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_RX_EN_MASK) 1010 1011 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_PAUSE_FWD_MASK (0x80U) 1012 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_PAUSE_FWD_SHIFT (7U) 1013 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_PAUSE_FWD_WIDTH (1U) 1014 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_PAUSE_FWD(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_PAUSE_FWD_SHIFT)) & SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_PAUSE_FWD_MASK) 1015 1016 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_PAUSE_IGN_MASK (0x100U) 1017 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_PAUSE_IGN_SHIFT (8U) 1018 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_PAUSE_IGN_WIDTH (1U) 1019 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_PAUSE_IGN(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_PAUSE_IGN_SHIFT)) & SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_PAUSE_IGN_MASK) 1020 1021 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TX_ADDR_INS_MASK (0x200U) 1022 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TX_ADDR_INS_SHIFT (9U) 1023 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TX_ADDR_INS_WIDTH (1U) 1024 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TX_ADDR_INS(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TX_ADDR_INS_SHIFT)) & SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TX_ADDR_INS_MASK) 1025 1026 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_LOOP_ENA_MASK (0x400U) 1027 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_LOOP_ENA_SHIFT (10U) 1028 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_LOOP_ENA_WIDTH (1U) 1029 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_LOOP_ENA(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_LOOP_ENA_SHIFT)) & SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_LOOP_ENA_MASK) 1030 1031 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_CNT_FRM_EN_MASK (0x2000U) 1032 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_CNT_FRM_EN_SHIFT (13U) 1033 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_CNT_FRM_EN_WIDTH (1U) 1034 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_CNT_FRM_EN(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_CNT_FRM_EN_SHIFT)) & SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_CNT_FRM_EN_MASK) 1035 1036 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TXP_MASK (0x8000U) 1037 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TXP_SHIFT (15U) 1038 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TXP_WIDTH (1U) 1039 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TXP(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TXP_SHIFT)) & SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TXP_MASK) 1040 1041 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TX_FLUSH_MASK (0x400000U) 1042 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TX_FLUSH_SHIFT (22U) 1043 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TX_FLUSH_WIDTH (1U) 1044 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TX_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TX_FLUSH_SHIFT)) & SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TX_FLUSH_MASK) 1045 1046 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TX_LOWP_ENA_MASK (0x800000U) 1047 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TX_LOWP_ENA_SHIFT (23U) 1048 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TX_LOWP_ENA_WIDTH (1U) 1049 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TX_LOWP_ENA(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TX_LOWP_ENA_SHIFT)) & SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TX_LOWP_ENA_MASK) 1050 1051 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_SWR_MASK (0x4000000U) 1052 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_SWR_SHIFT (26U) 1053 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_SWR_WIDTH (1U) 1054 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_SWR(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_SWR_SHIFT)) & SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_SWR_MASK) 1055 1056 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TS_MODE_MASK (0x40000000U) 1057 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TS_MODE_SHIFT (30U) 1058 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TS_MODE_WIDTH (1U) 1059 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TS_MODE(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TS_MODE_SHIFT)) & SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TS_MODE_MASK) 1060 1061 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_MG_MASK (0x80000000U) 1062 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_MG_SHIFT (31U) 1063 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_MG_WIDTH (1U) 1064 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_MG(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_MG_SHIFT)) & SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_MG_MASK) 1065 /*! @} */ 1066 1067 /*! @name PM1_MAC_ADDR_0 - Port MAC 1 MAC Address Register 0 */ 1068 /*! @{ */ 1069 1070 #define SW_ETH_MAC_PORT0_PM1_MAC_ADDR_0_MAC_ADDR_0_MASK (0xFFFFFFFFU) 1071 #define SW_ETH_MAC_PORT0_PM1_MAC_ADDR_0_MAC_ADDR_0_SHIFT (0U) 1072 #define SW_ETH_MAC_PORT0_PM1_MAC_ADDR_0_MAC_ADDR_0_WIDTH (32U) 1073 #define SW_ETH_MAC_PORT0_PM1_MAC_ADDR_0_MAC_ADDR_0(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_MAC_ADDR_0_MAC_ADDR_0_SHIFT)) & SW_ETH_MAC_PORT0_PM1_MAC_ADDR_0_MAC_ADDR_0_MASK) 1074 /*! @} */ 1075 1076 /*! @name PM1_MAC_ADDR_1 - Port MAC 1 MAC Address Register 1 */ 1077 /*! @{ */ 1078 1079 #define SW_ETH_MAC_PORT0_PM1_MAC_ADDR_1_MAC_ADDR_1_MASK (0xFFFFU) 1080 #define SW_ETH_MAC_PORT0_PM1_MAC_ADDR_1_MAC_ADDR_1_SHIFT (0U) 1081 #define SW_ETH_MAC_PORT0_PM1_MAC_ADDR_1_MAC_ADDR_1_WIDTH (16U) 1082 #define SW_ETH_MAC_PORT0_PM1_MAC_ADDR_1_MAC_ADDR_1(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_MAC_ADDR_1_MAC_ADDR_1_SHIFT)) & SW_ETH_MAC_PORT0_PM1_MAC_ADDR_1_MAC_ADDR_1_MASK) 1083 /*! @} */ 1084 1085 /*! @name PM1_MAXFRM - Port MAC 1 Maximum Frame Length Register */ 1086 /*! @{ */ 1087 1088 #define SW_ETH_MAC_PORT0_PM1_MAXFRM_MAXFRM_MASK (0xFFFFU) 1089 #define SW_ETH_MAC_PORT0_PM1_MAXFRM_MAXFRM_SHIFT (0U) 1090 #define SW_ETH_MAC_PORT0_PM1_MAXFRM_MAXFRM_WIDTH (16U) 1091 #define SW_ETH_MAC_PORT0_PM1_MAXFRM_MAXFRM(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_MAXFRM_MAXFRM_SHIFT)) & SW_ETH_MAC_PORT0_PM1_MAXFRM_MAXFRM_MASK) 1092 1093 #define SW_ETH_MAC_PORT0_PM1_MAXFRM_TX_MTU_MASK (0xFFFF0000U) 1094 #define SW_ETH_MAC_PORT0_PM1_MAXFRM_TX_MTU_SHIFT (16U) 1095 #define SW_ETH_MAC_PORT0_PM1_MAXFRM_TX_MTU_WIDTH (16U) 1096 #define SW_ETH_MAC_PORT0_PM1_MAXFRM_TX_MTU(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_MAXFRM_TX_MTU_SHIFT)) & SW_ETH_MAC_PORT0_PM1_MAXFRM_TX_MTU_MASK) 1097 /*! @} */ 1098 1099 /*! @name PM1_IEVENT - Port MAC 1 Interrupt Event Register */ 1100 /*! @{ */ 1101 1102 #define SW_ETH_MAC_PORT0_PM1_IEVENT_TX_EMPTY_MASK (0x20U) 1103 #define SW_ETH_MAC_PORT0_PM1_IEVENT_TX_EMPTY_SHIFT (5U) 1104 #define SW_ETH_MAC_PORT0_PM1_IEVENT_TX_EMPTY_WIDTH (1U) 1105 #define SW_ETH_MAC_PORT0_PM1_IEVENT_TX_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_IEVENT_TX_EMPTY_SHIFT)) & SW_ETH_MAC_PORT0_PM1_IEVENT_TX_EMPTY_MASK) 1106 1107 #define SW_ETH_MAC_PORT0_PM1_IEVENT_RX_EMPTY_MASK (0x40U) 1108 #define SW_ETH_MAC_PORT0_PM1_IEVENT_RX_EMPTY_SHIFT (6U) 1109 #define SW_ETH_MAC_PORT0_PM1_IEVENT_RX_EMPTY_WIDTH (1U) 1110 #define SW_ETH_MAC_PORT0_PM1_IEVENT_RX_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_IEVENT_RX_EMPTY_SHIFT)) & SW_ETH_MAC_PORT0_PM1_IEVENT_RX_EMPTY_MASK) 1111 1112 #define SW_ETH_MAC_PORT0_PM1_IEVENT_TX_OVFL_MASK (0x400U) 1113 #define SW_ETH_MAC_PORT0_PM1_IEVENT_TX_OVFL_SHIFT (10U) 1114 #define SW_ETH_MAC_PORT0_PM1_IEVENT_TX_OVFL_WIDTH (1U) 1115 #define SW_ETH_MAC_PORT0_PM1_IEVENT_TX_OVFL(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_IEVENT_TX_OVFL_SHIFT)) & SW_ETH_MAC_PORT0_PM1_IEVENT_TX_OVFL_MASK) 1116 1117 #define SW_ETH_MAC_PORT0_PM1_IEVENT_TX_UNFL_MASK (0x800U) 1118 #define SW_ETH_MAC_PORT0_PM1_IEVENT_TX_UNFL_SHIFT (11U) 1119 #define SW_ETH_MAC_PORT0_PM1_IEVENT_TX_UNFL_WIDTH (1U) 1120 #define SW_ETH_MAC_PORT0_PM1_IEVENT_TX_UNFL(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_IEVENT_TX_UNFL_SHIFT)) & SW_ETH_MAC_PORT0_PM1_IEVENT_TX_UNFL_MASK) 1121 1122 #define SW_ETH_MAC_PORT0_PM1_IEVENT_RX_OVFL_MASK (0x1000U) 1123 #define SW_ETH_MAC_PORT0_PM1_IEVENT_RX_OVFL_SHIFT (12U) 1124 #define SW_ETH_MAC_PORT0_PM1_IEVENT_RX_OVFL_WIDTH (1U) 1125 #define SW_ETH_MAC_PORT0_PM1_IEVENT_RX_OVFL(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_IEVENT_RX_OVFL_SHIFT)) & SW_ETH_MAC_PORT0_PM1_IEVENT_RX_OVFL_MASK) 1126 1127 #define SW_ETH_MAC_PORT0_PM1_IEVENT_MGI_MASK (0x4000U) 1128 #define SW_ETH_MAC_PORT0_PM1_IEVENT_MGI_SHIFT (14U) 1129 #define SW_ETH_MAC_PORT0_PM1_IEVENT_MGI_WIDTH (1U) 1130 #define SW_ETH_MAC_PORT0_PM1_IEVENT_MGI(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_IEVENT_MGI_SHIFT)) & SW_ETH_MAC_PORT0_PM1_IEVENT_MGI_MASK) 1131 /*! @} */ 1132 1133 /*! @name PM1_IMASK - Port MAC 1 Interrupt Mask Register(INT_MASK) */ 1134 /*! @{ */ 1135 1136 #define SW_ETH_MAC_PORT0_PM1_IMASK_MGI_MASK (0x4000U) 1137 #define SW_ETH_MAC_PORT0_PM1_IMASK_MGI_SHIFT (14U) 1138 #define SW_ETH_MAC_PORT0_PM1_IMASK_MGI_WIDTH (1U) 1139 #define SW_ETH_MAC_PORT0_PM1_IMASK_MGI(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_IMASK_MGI_SHIFT)) & SW_ETH_MAC_PORT0_PM1_IMASK_MGI_MASK) 1140 /*! @} */ 1141 1142 /*! @name PM1_PAUSE_QUANTA - Port MAC 1 Pause Quanta Register */ 1143 /*! @{ */ 1144 1145 #define SW_ETH_MAC_PORT0_PM1_PAUSE_QUANTA_PQNT_MASK (0xFFFFU) 1146 #define SW_ETH_MAC_PORT0_PM1_PAUSE_QUANTA_PQNT_SHIFT (0U) 1147 #define SW_ETH_MAC_PORT0_PM1_PAUSE_QUANTA_PQNT_WIDTH (16U) 1148 #define SW_ETH_MAC_PORT0_PM1_PAUSE_QUANTA_PQNT(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_PAUSE_QUANTA_PQNT_SHIFT)) & SW_ETH_MAC_PORT0_PM1_PAUSE_QUANTA_PQNT_MASK) 1149 /*! @} */ 1150 1151 /*! @name PM1_PAUSE_THRESH - Port MAC 1 Pause Quanta Threshold Register */ 1152 /*! @{ */ 1153 1154 #define SW_ETH_MAC_PORT0_PM1_PAUSE_THRESH_QTH_MASK (0xFFFFU) 1155 #define SW_ETH_MAC_PORT0_PM1_PAUSE_THRESH_QTH_SHIFT (0U) 1156 #define SW_ETH_MAC_PORT0_PM1_PAUSE_THRESH_QTH_WIDTH (16U) 1157 #define SW_ETH_MAC_PORT0_PM1_PAUSE_THRESH_QTH(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_PAUSE_THRESH_QTH_SHIFT)) & SW_ETH_MAC_PORT0_PM1_PAUSE_THRESH_QTH_MASK) 1158 /*! @} */ 1159 1160 /*! @name PM1_RX_PAUSE_STATUS - Port MAC 1 Receive Pause Status Register */ 1161 /*! @{ */ 1162 1163 #define SW_ETH_MAC_PORT0_PM1_RX_PAUSE_STATUS_PSTAT_MASK (0x1U) 1164 #define SW_ETH_MAC_PORT0_PM1_RX_PAUSE_STATUS_PSTAT_SHIFT (0U) 1165 #define SW_ETH_MAC_PORT0_PM1_RX_PAUSE_STATUS_PSTAT_WIDTH (1U) 1166 #define SW_ETH_MAC_PORT0_PM1_RX_PAUSE_STATUS_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_RX_PAUSE_STATUS_PSTAT_SHIFT)) & SW_ETH_MAC_PORT0_PM1_RX_PAUSE_STATUS_PSTAT_MASK) 1167 /*! @} */ 1168 1169 /*! @name PM1_LPWAKE_TIMER - Port MAC 1 EEE Low Power Wakeup Timer Register */ 1170 /*! @{ */ 1171 1172 #define SW_ETH_MAC_PORT0_PM1_LPWAKE_TIMER_TW_SYS_TX_MASK (0xFFFFFFU) 1173 #define SW_ETH_MAC_PORT0_PM1_LPWAKE_TIMER_TW_SYS_TX_SHIFT (0U) 1174 #define SW_ETH_MAC_PORT0_PM1_LPWAKE_TIMER_TW_SYS_TX_WIDTH (24U) 1175 #define SW_ETH_MAC_PORT0_PM1_LPWAKE_TIMER_TW_SYS_TX(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_LPWAKE_TIMER_TW_SYS_TX_SHIFT)) & SW_ETH_MAC_PORT0_PM1_LPWAKE_TIMER_TW_SYS_TX_MASK) 1176 /*! @} */ 1177 1178 /*! @name PM1_SLEEP_TIMER - Port MAC 1 Transmit EEE Low Power Timer Register */ 1179 /*! @{ */ 1180 1181 #define SW_ETH_MAC_PORT0_PM1_SLEEP_TIMER_SLEEPT_MASK (0xFFFFFFU) 1182 #define SW_ETH_MAC_PORT0_PM1_SLEEP_TIMER_SLEEPT_SHIFT (0U) 1183 #define SW_ETH_MAC_PORT0_PM1_SLEEP_TIMER_SLEEPT_WIDTH (24U) 1184 #define SW_ETH_MAC_PORT0_PM1_SLEEP_TIMER_SLEEPT(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_SLEEP_TIMER_SLEEPT_SHIFT)) & SW_ETH_MAC_PORT0_PM1_SLEEP_TIMER_SLEEPT_MASK) 1185 /*! @} */ 1186 1187 /*! @name PM1_SINGLE_STEP - Port MAC 1 IEEE1588 Single-Step Control Register */ 1188 /*! @{ */ 1189 1190 #define SW_ETH_MAC_PORT0_PM1_SINGLE_STEP_OFFSET_MASK (0xFF80U) 1191 #define SW_ETH_MAC_PORT0_PM1_SINGLE_STEP_OFFSET_SHIFT (7U) 1192 #define SW_ETH_MAC_PORT0_PM1_SINGLE_STEP_OFFSET_WIDTH (9U) 1193 #define SW_ETH_MAC_PORT0_PM1_SINGLE_STEP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_SINGLE_STEP_OFFSET_SHIFT)) & SW_ETH_MAC_PORT0_PM1_SINGLE_STEP_OFFSET_MASK) 1194 1195 #define SW_ETH_MAC_PORT0_PM1_SINGLE_STEP_EN_MASK (0x80000000U) 1196 #define SW_ETH_MAC_PORT0_PM1_SINGLE_STEP_EN_SHIFT (31U) 1197 #define SW_ETH_MAC_PORT0_PM1_SINGLE_STEP_EN_WIDTH (1U) 1198 #define SW_ETH_MAC_PORT0_PM1_SINGLE_STEP_EN(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_SINGLE_STEP_EN_SHIFT)) & SW_ETH_MAC_PORT0_PM1_SINGLE_STEP_EN_MASK) 1199 /*! @} */ 1200 1201 /*! @name PM1_HD_BACKOFF_ENTROPY - Port MAC 1 half-duplex backoff entropy register */ 1202 /*! @{ */ 1203 1204 #define SW_ETH_MAC_PORT0_PM1_HD_BACKOFF_ENTROPY_HD_BACKOFF_ENTROPY_MASK (0x3FFU) 1205 #define SW_ETH_MAC_PORT0_PM1_HD_BACKOFF_ENTROPY_HD_BACKOFF_ENTROPY_SHIFT (0U) 1206 #define SW_ETH_MAC_PORT0_PM1_HD_BACKOFF_ENTROPY_HD_BACKOFF_ENTROPY_WIDTH (10U) 1207 #define SW_ETH_MAC_PORT0_PM1_HD_BACKOFF_ENTROPY_HD_BACKOFF_ENTROPY(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_HD_BACKOFF_ENTROPY_HD_BACKOFF_ENTROPY_SHIFT)) & SW_ETH_MAC_PORT0_PM1_HD_BACKOFF_ENTROPY_HD_BACKOFF_ENTROPY_MASK) 1208 1209 #define SW_ETH_MAC_PORT0_PM1_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID_MASK (0x80000000U) 1210 #define SW_ETH_MAC_PORT0_PM1_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID_SHIFT (31U) 1211 #define SW_ETH_MAC_PORT0_PM1_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID_WIDTH (1U) 1212 #define SW_ETH_MAC_PORT0_PM1_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID_SHIFT)) & SW_ETH_MAC_PORT0_PM1_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID_MASK) 1213 /*! @} */ 1214 1215 /*! @name PM1_STATN_CONFIG - Port MAC 1 Statistics Configuration Register */ 1216 /*! @{ */ 1217 1218 #define SW_ETH_MAC_PORT0_PM1_STATN_CONFIG_SAT_MASK (0x1U) 1219 #define SW_ETH_MAC_PORT0_PM1_STATN_CONFIG_SAT_SHIFT (0U) 1220 #define SW_ETH_MAC_PORT0_PM1_STATN_CONFIG_SAT_WIDTH (1U) 1221 #define SW_ETH_MAC_PORT0_PM1_STATN_CONFIG_SAT(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_STATN_CONFIG_SAT_SHIFT)) & SW_ETH_MAC_PORT0_PM1_STATN_CONFIG_SAT_MASK) 1222 1223 #define SW_ETH_MAC_PORT0_PM1_STATN_CONFIG_COD_MASK (0x2U) 1224 #define SW_ETH_MAC_PORT0_PM1_STATN_CONFIG_COD_SHIFT (1U) 1225 #define SW_ETH_MAC_PORT0_PM1_STATN_CONFIG_COD_WIDTH (1U) 1226 #define SW_ETH_MAC_PORT0_PM1_STATN_CONFIG_COD(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_STATN_CONFIG_COD_SHIFT)) & SW_ETH_MAC_PORT0_PM1_STATN_CONFIG_COD_MASK) 1227 1228 #define SW_ETH_MAC_PORT0_PM1_STATN_CONFIG_CLR_MASK (0x4U) 1229 #define SW_ETH_MAC_PORT0_PM1_STATN_CONFIG_CLR_SHIFT (2U) 1230 #define SW_ETH_MAC_PORT0_PM1_STATN_CONFIG_CLR_WIDTH (1U) 1231 #define SW_ETH_MAC_PORT0_PM1_STATN_CONFIG_CLR(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_STATN_CONFIG_CLR_SHIFT)) & SW_ETH_MAC_PORT0_PM1_STATN_CONFIG_CLR_MASK) 1232 /*! @} */ 1233 1234 /*! @name PM1_REOCTN - Port MAC 1 Receive Ethernet Octets Counter(etherStatsOctetsn) */ 1235 /*! @{ */ 1236 1237 #define SW_ETH_MAC_PORT0_PM1_REOCTN_REOCTn_MASK (0xFFFFFFFFFFFFFFFFU) 1238 #define SW_ETH_MAC_PORT0_PM1_REOCTN_REOCTn_SHIFT (0U) 1239 #define SW_ETH_MAC_PORT0_PM1_REOCTN_REOCTn_WIDTH (64U) 1240 #define SW_ETH_MAC_PORT0_PM1_REOCTN_REOCTn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_REOCTN_REOCTn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_REOCTN_REOCTn_MASK) 1241 /*! @} */ 1242 1243 /*! @name PM1_ROCTN - Port MAC 1 Receive Octets Counter(iflnOctetsn) */ 1244 /*! @{ */ 1245 1246 #define SW_ETH_MAC_PORT0_PM1_ROCTN_ROCTn_MASK (0xFFFFFFFFFFFFFFFFU) 1247 #define SW_ETH_MAC_PORT0_PM1_ROCTN_ROCTn_SHIFT (0U) 1248 #define SW_ETH_MAC_PORT0_PM1_ROCTN_ROCTn_WIDTH (64U) 1249 #define SW_ETH_MAC_PORT0_PM1_ROCTN_ROCTn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_ROCTN_ROCTn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_ROCTN_ROCTn_MASK) 1250 /*! @} */ 1251 1252 /*! @name PM1_RXPFN - Port MAC 1 Receive Valid Pause Frame Counter Register(aPAUSEMACCtrlFramesReceivedn) */ 1253 /*! @{ */ 1254 1255 #define SW_ETH_MAC_PORT0_PM1_RXPFN_RXPFn_MASK (0xFFFFFFFFFFFFFFFFU) 1256 #define SW_ETH_MAC_PORT0_PM1_RXPFN_RXPFn_SHIFT (0U) 1257 #define SW_ETH_MAC_PORT0_PM1_RXPFN_RXPFn_WIDTH (64U) 1258 #define SW_ETH_MAC_PORT0_PM1_RXPFN_RXPFn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_RXPFN_RXPFn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_RXPFN_RXPFn_MASK) 1259 /*! @} */ 1260 1261 /*! @name PM1_RFRMN - Port MAC 1 Receive Frame Counter Register(aFramesReceivedOKn) */ 1262 /*! @{ */ 1263 1264 #define SW_ETH_MAC_PORT0_PM1_RFRMN_RFRMn_MASK (0xFFFFFFFFFFFFFFFFU) 1265 #define SW_ETH_MAC_PORT0_PM1_RFRMN_RFRMn_SHIFT (0U) 1266 #define SW_ETH_MAC_PORT0_PM1_RFRMN_RFRMn_WIDTH (64U) 1267 #define SW_ETH_MAC_PORT0_PM1_RFRMN_RFRMn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_RFRMN_RFRMn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_RFRMN_RFRMn_MASK) 1268 /*! @} */ 1269 1270 /*! @name PM1_RFCSN - Port MAC 1 Receive Frame Check Sequence Error Counter Register() */ 1271 /*! @{ */ 1272 1273 #define SW_ETH_MAC_PORT0_PM1_RFCSN_RFCSn_MASK (0xFFFFFFFFFFFFFFFFU) 1274 #define SW_ETH_MAC_PORT0_PM1_RFCSN_RFCSn_SHIFT (0U) 1275 #define SW_ETH_MAC_PORT0_PM1_RFCSN_RFCSn_WIDTH (64U) 1276 #define SW_ETH_MAC_PORT0_PM1_RFCSN_RFCSn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_RFCSN_RFCSn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_RFCSN_RFCSn_MASK) 1277 /*! @} */ 1278 1279 /*! @name PM1_RVLANN - Port MAC 1 Receive VLAN Frame Counter Register(VLANReceivedOKn) */ 1280 /*! @{ */ 1281 1282 #define SW_ETH_MAC_PORT0_PM1_RVLANN_RVLANn_MASK (0xFFFFFFFFFFFFFFFFU) 1283 #define SW_ETH_MAC_PORT0_PM1_RVLANN_RVLANn_SHIFT (0U) 1284 #define SW_ETH_MAC_PORT0_PM1_RVLANN_RVLANn_WIDTH (64U) 1285 #define SW_ETH_MAC_PORT0_PM1_RVLANN_RVLANn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_RVLANN_RVLANn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_RVLANN_RVLANn_MASK) 1286 /*! @} */ 1287 1288 /*! @name PM1_RERRN - Port MAC 1 Receive Frame Error Counter Register(ifInErrorsn) */ 1289 /*! @{ */ 1290 1291 #define SW_ETH_MAC_PORT0_PM1_RERRN_RERRn_MASK (0xFFFFFFFFFFFFFFFFU) 1292 #define SW_ETH_MAC_PORT0_PM1_RERRN_RERRn_SHIFT (0U) 1293 #define SW_ETH_MAC_PORT0_PM1_RERRN_RERRn_WIDTH (64U) 1294 #define SW_ETH_MAC_PORT0_PM1_RERRN_RERRn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_RERRN_RERRn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_RERRN_RERRn_MASK) 1295 /*! @} */ 1296 1297 /*! @name PM1_RUCAN - Port MAC 1 Receive Unicast Frame Counter Register(ifInUcastPktsn) */ 1298 /*! @{ */ 1299 1300 #define SW_ETH_MAC_PORT0_PM1_RUCAN_RUCAn_MASK (0xFFFFFFFFFFFFFFFFU) 1301 #define SW_ETH_MAC_PORT0_PM1_RUCAN_RUCAn_SHIFT (0U) 1302 #define SW_ETH_MAC_PORT0_PM1_RUCAN_RUCAn_WIDTH (64U) 1303 #define SW_ETH_MAC_PORT0_PM1_RUCAN_RUCAn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_RUCAN_RUCAn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_RUCAN_RUCAn_MASK) 1304 /*! @} */ 1305 1306 /*! @name PM1_RMCAN - Port MAC 1 Receive Multicast Frame Counter Register(ifInMulticastPktsn) */ 1307 /*! @{ */ 1308 1309 #define SW_ETH_MAC_PORT0_PM1_RMCAN_RMCAn_MASK (0xFFFFFFFFFFFFFFFFU) 1310 #define SW_ETH_MAC_PORT0_PM1_RMCAN_RMCAn_SHIFT (0U) 1311 #define SW_ETH_MAC_PORT0_PM1_RMCAN_RMCAn_WIDTH (64U) 1312 #define SW_ETH_MAC_PORT0_PM1_RMCAN_RMCAn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_RMCAN_RMCAn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_RMCAN_RMCAn_MASK) 1313 /*! @} */ 1314 1315 /*! @name PM1_RBCAN - Port MAC 1 Receive Broadcast Frame Counter Register(ifInBroadcastPktsn) */ 1316 /*! @{ */ 1317 1318 #define SW_ETH_MAC_PORT0_PM1_RBCAN_RBCAn_MASK (0xFFFFFFFFFFFFFFFFU) 1319 #define SW_ETH_MAC_PORT0_PM1_RBCAN_RBCAn_SHIFT (0U) 1320 #define SW_ETH_MAC_PORT0_PM1_RBCAN_RBCAn_WIDTH (64U) 1321 #define SW_ETH_MAC_PORT0_PM1_RBCAN_RBCAn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_RBCAN_RBCAn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_RBCAN_RBCAn_MASK) 1322 /*! @} */ 1323 1324 /*! @name PM1_RDRPN - Port MAC 1 Receive Dropped Packets Counter Register(etherStatsDropEventsn) */ 1325 /*! @{ */ 1326 1327 #define SW_ETH_MAC_PORT0_PM1_RDRPN_RDRPn_MASK (0xFFFFFFFFFFFFFFFFU) 1328 #define SW_ETH_MAC_PORT0_PM1_RDRPN_RDRPn_SHIFT (0U) 1329 #define SW_ETH_MAC_PORT0_PM1_RDRPN_RDRPn_WIDTH (64U) 1330 #define SW_ETH_MAC_PORT0_PM1_RDRPN_RDRPn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_RDRPN_RDRPn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_RDRPN_RDRPn_MASK) 1331 /*! @} */ 1332 1333 /*! @name PM1_RPKTN - Port MAC 1 Receive Packets Counter Register(etherStatsPktsn) */ 1334 /*! @{ */ 1335 1336 #define SW_ETH_MAC_PORT0_PM1_RPKTN_RPKTn_MASK (0xFFFFFFFFFFFFFFFFU) 1337 #define SW_ETH_MAC_PORT0_PM1_RPKTN_RPKTn_SHIFT (0U) 1338 #define SW_ETH_MAC_PORT0_PM1_RPKTN_RPKTn_WIDTH (64U) 1339 #define SW_ETH_MAC_PORT0_PM1_RPKTN_RPKTn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_RPKTN_RPKTn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_RPKTN_RPKTn_MASK) 1340 /*! @} */ 1341 1342 /*! @name PM1_RUNDN - Port MAC 1 Receive Undersized Packet Counter Register(etherStatsUndersizePktsn) */ 1343 /*! @{ */ 1344 1345 #define SW_ETH_MAC_PORT0_PM1_RUNDN_RUNDn_MASK (0xFFFFFFFFFFFFFFFFU) 1346 #define SW_ETH_MAC_PORT0_PM1_RUNDN_RUNDn_SHIFT (0U) 1347 #define SW_ETH_MAC_PORT0_PM1_RUNDN_RUNDn_WIDTH (64U) 1348 #define SW_ETH_MAC_PORT0_PM1_RUNDN_RUNDn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_RUNDN_RUNDn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_RUNDN_RUNDn_MASK) 1349 /*! @} */ 1350 1351 /*! @name PM1_R64N - Port MAC 1 Receive 64-Octet Packet Counter Register(etherStatsPkts64OctetsN) */ 1352 /*! @{ */ 1353 1354 #define SW_ETH_MAC_PORT0_PM1_R64N_R64n_MASK (0xFFFFFFFFFFFFFFFFU) 1355 #define SW_ETH_MAC_PORT0_PM1_R64N_R64n_SHIFT (0U) 1356 #define SW_ETH_MAC_PORT0_PM1_R64N_R64n_WIDTH (64U) 1357 #define SW_ETH_MAC_PORT0_PM1_R64N_R64n(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_R64N_R64n_SHIFT)) & SW_ETH_MAC_PORT0_PM1_R64N_R64n_MASK) 1358 /*! @} */ 1359 1360 /*! @name PM1_R127N - Port MAC 1 Receive 65 to 127-Octet Packet Counter Register(etherStatsPkts65to127OctetsN) */ 1361 /*! @{ */ 1362 1363 #define SW_ETH_MAC_PORT0_PM1_R127N_R127n_MASK (0xFFFFFFFFFFFFFFFFU) 1364 #define SW_ETH_MAC_PORT0_PM1_R127N_R127n_SHIFT (0U) 1365 #define SW_ETH_MAC_PORT0_PM1_R127N_R127n_WIDTH (64U) 1366 #define SW_ETH_MAC_PORT0_PM1_R127N_R127n(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_R127N_R127n_SHIFT)) & SW_ETH_MAC_PORT0_PM1_R127N_R127n_MASK) 1367 /*! @} */ 1368 1369 /*! @name PM1_R255N - Port MAC 1 Receive 128 to 255-Octet Packet Counter Register(etherStatsPkts128to255OctetsN) */ 1370 /*! @{ */ 1371 1372 #define SW_ETH_MAC_PORT0_PM1_R255N_R255n_MASK (0xFFFFFFFFFFFFFFFFU) 1373 #define SW_ETH_MAC_PORT0_PM1_R255N_R255n_SHIFT (0U) 1374 #define SW_ETH_MAC_PORT0_PM1_R255N_R255n_WIDTH (64U) 1375 #define SW_ETH_MAC_PORT0_PM1_R255N_R255n(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_R255N_R255n_SHIFT)) & SW_ETH_MAC_PORT0_PM1_R255N_R255n_MASK) 1376 /*! @} */ 1377 1378 /*! @name PM1_R511N - Port MAC 1 Receive 256 to 511-Octet Packet Counter Register(etherStatsPkts256to511OctetsN) */ 1379 /*! @{ */ 1380 1381 #define SW_ETH_MAC_PORT0_PM1_R511N_R511n_MASK (0xFFFFFFFFFFFFFFFFU) 1382 #define SW_ETH_MAC_PORT0_PM1_R511N_R511n_SHIFT (0U) 1383 #define SW_ETH_MAC_PORT0_PM1_R511N_R511n_WIDTH (64U) 1384 #define SW_ETH_MAC_PORT0_PM1_R511N_R511n(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_R511N_R511n_SHIFT)) & SW_ETH_MAC_PORT0_PM1_R511N_R511n_MASK) 1385 /*! @} */ 1386 1387 /*! @name PM1_R1023N - Port MAC 1 Receive 512 to 1023-Octet Packet Counter Register(etherStatsPkts512to1023OctetsN) */ 1388 /*! @{ */ 1389 1390 #define SW_ETH_MAC_PORT0_PM1_R1023N_R1023n_MASK (0xFFFFFFFFFFFFFFFFU) 1391 #define SW_ETH_MAC_PORT0_PM1_R1023N_R1023n_SHIFT (0U) 1392 #define SW_ETH_MAC_PORT0_PM1_R1023N_R1023n_WIDTH (64U) 1393 #define SW_ETH_MAC_PORT0_PM1_R1023N_R1023n(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_R1023N_R1023n_SHIFT)) & SW_ETH_MAC_PORT0_PM1_R1023N_R1023n_MASK) 1394 /*! @} */ 1395 1396 /*! @name PM1_R1522N - Port MAC 1 Receive 1024 to 1522-Octet Packet Counter Register(etherStatsPkts1024to1522OctetsN) */ 1397 /*! @{ */ 1398 1399 #define SW_ETH_MAC_PORT0_PM1_R1522N_R1522n_MASK (0xFFFFFFFFFFFFFFFFU) 1400 #define SW_ETH_MAC_PORT0_PM1_R1522N_R1522n_SHIFT (0U) 1401 #define SW_ETH_MAC_PORT0_PM1_R1522N_R1522n_WIDTH (64U) 1402 #define SW_ETH_MAC_PORT0_PM1_R1522N_R1522n(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_R1522N_R1522n_SHIFT)) & SW_ETH_MAC_PORT0_PM1_R1522N_R1522n_MASK) 1403 /*! @} */ 1404 1405 /*! @name PM1_R1523XN - Port MAC 1 Receive 1523 to Max-Octet Packet Counter Register(etherStatsPkts1523toMaxOctetsN) */ 1406 /*! @{ */ 1407 1408 #define SW_ETH_MAC_PORT0_PM1_R1523XN_R1523Xn_MASK (0xFFFFFFFFFFFFFFFFU) 1409 #define SW_ETH_MAC_PORT0_PM1_R1523XN_R1523Xn_SHIFT (0U) 1410 #define SW_ETH_MAC_PORT0_PM1_R1523XN_R1523Xn_WIDTH (64U) 1411 #define SW_ETH_MAC_PORT0_PM1_R1523XN_R1523Xn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_R1523XN_R1523Xn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_R1523XN_R1523Xn_MASK) 1412 /*! @} */ 1413 1414 /*! @name PM1_ROVRN - Port MAC 1 Receive Oversized Packet Counter Register(etherStatsOversizePktsn) */ 1415 /*! @{ */ 1416 1417 #define SW_ETH_MAC_PORT0_PM1_ROVRN_ROVRn_MASK (0xFFFFFFFFFFFFFFFFU) 1418 #define SW_ETH_MAC_PORT0_PM1_ROVRN_ROVRn_SHIFT (0U) 1419 #define SW_ETH_MAC_PORT0_PM1_ROVRN_ROVRn_WIDTH (64U) 1420 #define SW_ETH_MAC_PORT0_PM1_ROVRN_ROVRn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_ROVRN_ROVRn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_ROVRN_ROVRn_MASK) 1421 /*! @} */ 1422 1423 /*! @name PM1_RJBRN - Port MAC 1 Receive Jabber Packet Counter Register(etherStatsJabbersn) */ 1424 /*! @{ */ 1425 1426 #define SW_ETH_MAC_PORT0_PM1_RJBRN_RJBRn_MASK (0xFFFFFFFFFFFFFFFFU) 1427 #define SW_ETH_MAC_PORT0_PM1_RJBRN_RJBRn_SHIFT (0U) 1428 #define SW_ETH_MAC_PORT0_PM1_RJBRN_RJBRn_WIDTH (64U) 1429 #define SW_ETH_MAC_PORT0_PM1_RJBRN_RJBRn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_RJBRN_RJBRn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_RJBRN_RJBRn_MASK) 1430 /*! @} */ 1431 1432 /*! @name PM1_RFRGN - Port MAC 1 Receive Fragment Packet Counter Register(etherStatsFragmentsn */ 1433 /*! @{ */ 1434 1435 #define SW_ETH_MAC_PORT0_PM1_RFRGN_RFRGn_MASK (0xFFFFFFFFFFFFFFFFU) 1436 #define SW_ETH_MAC_PORT0_PM1_RFRGN_RFRGn_SHIFT (0U) 1437 #define SW_ETH_MAC_PORT0_PM1_RFRGN_RFRGn_WIDTH (64U) 1438 #define SW_ETH_MAC_PORT0_PM1_RFRGN_RFRGn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_RFRGN_RFRGn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_RFRGN_RFRGn_MASK) 1439 /*! @} */ 1440 1441 /*! @name PM1_RCNPN - Port MAC 1 Receive Control Packet Counter Register */ 1442 /*! @{ */ 1443 1444 #define SW_ETH_MAC_PORT0_PM1_RCNPN_RCNPn_MASK (0xFFFFFFFFFFFFFFFFU) 1445 #define SW_ETH_MAC_PORT0_PM1_RCNPN_RCNPn_SHIFT (0U) 1446 #define SW_ETH_MAC_PORT0_PM1_RCNPN_RCNPn_WIDTH (64U) 1447 #define SW_ETH_MAC_PORT0_PM1_RCNPN_RCNPn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_RCNPN_RCNPn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_RCNPN_RCNPn_MASK) 1448 /*! @} */ 1449 1450 /*! @name PM1_RDRNTPN - Port MAC 1 Receive Dropped Not Truncated Packets Counter Register(etherStatsDropEventsn) */ 1451 /*! @{ */ 1452 1453 #define SW_ETH_MAC_PORT0_PM1_RDRNTPN_RDRNTPn_MASK (0xFFFFFFFFFFFFFFFFU) 1454 #define SW_ETH_MAC_PORT0_PM1_RDRNTPN_RDRNTPn_SHIFT (0U) 1455 #define SW_ETH_MAC_PORT0_PM1_RDRNTPN_RDRNTPn_WIDTH (64U) 1456 #define SW_ETH_MAC_PORT0_PM1_RDRNTPN_RDRNTPn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_RDRNTPN_RDRNTPn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_RDRNTPN_RDRNTPn_MASK) 1457 /*! @} */ 1458 1459 /*! @name PM1_TEOCTN - Port MAC 1 Transmit Ethernet Octets Counter(etherStatsOctetsn) */ 1460 /*! @{ */ 1461 1462 #define SW_ETH_MAC_PORT0_PM1_TEOCTN_TEOCTn_MASK (0xFFFFFFFFFFFFFFFFU) 1463 #define SW_ETH_MAC_PORT0_PM1_TEOCTN_TEOCTn_SHIFT (0U) 1464 #define SW_ETH_MAC_PORT0_PM1_TEOCTN_TEOCTn_WIDTH (64U) 1465 #define SW_ETH_MAC_PORT0_PM1_TEOCTN_TEOCTn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_TEOCTN_TEOCTn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_TEOCTN_TEOCTn_MASK) 1466 /*! @} */ 1467 1468 /*! @name PM1_TOCTN - Port MAC 1 Transmit Octets Counter Register(ifOutOctetsn) */ 1469 /*! @{ */ 1470 1471 #define SW_ETH_MAC_PORT0_PM1_TOCTN_TOCTn_MASK (0xFFFFFFFFFFFFFFFFU) 1472 #define SW_ETH_MAC_PORT0_PM1_TOCTN_TOCTn_SHIFT (0U) 1473 #define SW_ETH_MAC_PORT0_PM1_TOCTN_TOCTn_WIDTH (64U) 1474 #define SW_ETH_MAC_PORT0_PM1_TOCTN_TOCTn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_TOCTN_TOCTn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_TOCTN_TOCTn_MASK) 1475 /*! @} */ 1476 1477 /*! @name PM1_TXPFN - Port MAC 1 Transmit Valid Pause Frame Counter Register(aPAUSEMACCtrlFramesReceivedn) */ 1478 /*! @{ */ 1479 1480 #define SW_ETH_MAC_PORT0_PM1_TXPFN_TXPFn_MASK (0xFFFFFFFFFFFFFFFFU) 1481 #define SW_ETH_MAC_PORT0_PM1_TXPFN_TXPFn_SHIFT (0U) 1482 #define SW_ETH_MAC_PORT0_PM1_TXPFN_TXPFn_WIDTH (64U) 1483 #define SW_ETH_MAC_PORT0_PM1_TXPFN_TXPFn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_TXPFN_TXPFn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_TXPFN_TXPFn_MASK) 1484 /*! @} */ 1485 1486 /*! @name PM1_TFRMN - Port MAC 1 Transmit Frame Counter Register(aFramesTransmittedOKn) */ 1487 /*! @{ */ 1488 1489 #define SW_ETH_MAC_PORT0_PM1_TFRMN_TFRMn_MASK (0xFFFFFFFFFFFFFFFFU) 1490 #define SW_ETH_MAC_PORT0_PM1_TFRMN_TFRMn_SHIFT (0U) 1491 #define SW_ETH_MAC_PORT0_PM1_TFRMN_TFRMn_WIDTH (64U) 1492 #define SW_ETH_MAC_PORT0_PM1_TFRMN_TFRMn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_TFRMN_TFRMn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_TFRMN_TFRMn_MASK) 1493 /*! @} */ 1494 1495 /*! @name PM1_TFCSN - Port MAC 1 Transmit Frame Check Sequence Error Counter Register() */ 1496 /*! @{ */ 1497 1498 #define SW_ETH_MAC_PORT0_PM1_TFCSN_TFCSn_MASK (0xFFFFFFFFFFFFFFFFU) 1499 #define SW_ETH_MAC_PORT0_PM1_TFCSN_TFCSn_SHIFT (0U) 1500 #define SW_ETH_MAC_PORT0_PM1_TFCSN_TFCSn_WIDTH (64U) 1501 #define SW_ETH_MAC_PORT0_PM1_TFCSN_TFCSn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_TFCSN_TFCSn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_TFCSN_TFCSn_MASK) 1502 /*! @} */ 1503 1504 /*! @name PM1_TVLANN - Port MAC 1 Transmit VLAN Frame Counter Register(VLANTransmittedOKn) */ 1505 /*! @{ */ 1506 1507 #define SW_ETH_MAC_PORT0_PM1_TVLANN_TVLANn_MASK (0xFFFFFFFFFFFFFFFFU) 1508 #define SW_ETH_MAC_PORT0_PM1_TVLANN_TVLANn_SHIFT (0U) 1509 #define SW_ETH_MAC_PORT0_PM1_TVLANN_TVLANn_WIDTH (64U) 1510 #define SW_ETH_MAC_PORT0_PM1_TVLANN_TVLANn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_TVLANN_TVLANn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_TVLANN_TVLANn_MASK) 1511 /*! @} */ 1512 1513 /*! @name PM1_TERRN - Port MAC 1 Transmit Frame Error Counter Register(ifOutErrorsn) */ 1514 /*! @{ */ 1515 1516 #define SW_ETH_MAC_PORT0_PM1_TERRN_TERRn_MASK (0xFFFFFFFFFFFFFFFFU) 1517 #define SW_ETH_MAC_PORT0_PM1_TERRN_TERRn_SHIFT (0U) 1518 #define SW_ETH_MAC_PORT0_PM1_TERRN_TERRn_WIDTH (64U) 1519 #define SW_ETH_MAC_PORT0_PM1_TERRN_TERRn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_TERRN_TERRn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_TERRN_TERRn_MASK) 1520 /*! @} */ 1521 1522 /*! @name PM1_TUCAN - Port MAC 1 Transmit Unicast Frame Counter Register(ifOutUcastPktsn) */ 1523 /*! @{ */ 1524 1525 #define SW_ETH_MAC_PORT0_PM1_TUCAN_TUCAn_MASK (0xFFFFFFFFFFFFFFFFU) 1526 #define SW_ETH_MAC_PORT0_PM1_TUCAN_TUCAn_SHIFT (0U) 1527 #define SW_ETH_MAC_PORT0_PM1_TUCAN_TUCAn_WIDTH (64U) 1528 #define SW_ETH_MAC_PORT0_PM1_TUCAN_TUCAn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_TUCAN_TUCAn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_TUCAN_TUCAn_MASK) 1529 /*! @} */ 1530 1531 /*! @name PM1_TMCAN - Port MAC 1 Transmit Multicast Frame Counter Register(ifOutMulticastPktsn) */ 1532 /*! @{ */ 1533 1534 #define SW_ETH_MAC_PORT0_PM1_TMCAN_TMCAn_MASK (0xFFFFFFFFFFFFFFFFU) 1535 #define SW_ETH_MAC_PORT0_PM1_TMCAN_TMCAn_SHIFT (0U) 1536 #define SW_ETH_MAC_PORT0_PM1_TMCAN_TMCAn_WIDTH (64U) 1537 #define SW_ETH_MAC_PORT0_PM1_TMCAN_TMCAn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_TMCAN_TMCAn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_TMCAN_TMCAn_MASK) 1538 /*! @} */ 1539 1540 /*! @name PM1_TBCAN - Port MAC 1 Transmit Broadcast Frame Counter Register(ifOutBroadcastPktsn) */ 1541 /*! @{ */ 1542 1543 #define SW_ETH_MAC_PORT0_PM1_TBCAN_TBCAn_MASK (0xFFFFFFFFFFFFFFFFU) 1544 #define SW_ETH_MAC_PORT0_PM1_TBCAN_TBCAn_SHIFT (0U) 1545 #define SW_ETH_MAC_PORT0_PM1_TBCAN_TBCAn_WIDTH (64U) 1546 #define SW_ETH_MAC_PORT0_PM1_TBCAN_TBCAn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_TBCAN_TBCAn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_TBCAN_TBCAn_MASK) 1547 /*! @} */ 1548 1549 /*! @name PM1_TPKTN - Port MAC 1 Transmit Packets Counter Register(etherStatsPktsn) */ 1550 /*! @{ */ 1551 1552 #define SW_ETH_MAC_PORT0_PM1_TPKTN_TPKTn_MASK (0xFFFFFFFFFFFFFFFFU) 1553 #define SW_ETH_MAC_PORT0_PM1_TPKTN_TPKTn_SHIFT (0U) 1554 #define SW_ETH_MAC_PORT0_PM1_TPKTN_TPKTn_WIDTH (64U) 1555 #define SW_ETH_MAC_PORT0_PM1_TPKTN_TPKTn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_TPKTN_TPKTn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_TPKTN_TPKTn_MASK) 1556 /*! @} */ 1557 1558 /*! @name PM1_TUNDN - Port MAC 1 Transmit Undersized Packet Counter Register(etherStatsUndersizePktsn) */ 1559 /*! @{ */ 1560 1561 #define SW_ETH_MAC_PORT0_PM1_TUNDN_TUNDn_MASK (0xFFFFFFFFFFFFFFFFU) 1562 #define SW_ETH_MAC_PORT0_PM1_TUNDN_TUNDn_SHIFT (0U) 1563 #define SW_ETH_MAC_PORT0_PM1_TUNDN_TUNDn_WIDTH (64U) 1564 #define SW_ETH_MAC_PORT0_PM1_TUNDN_TUNDn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_TUNDN_TUNDn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_TUNDN_TUNDn_MASK) 1565 /*! @} */ 1566 1567 /*! @name PM1_T64N - Port MAC 1 Transmit 64-Octet Packet Counter Register (etherStatsPkts64OctetsN) */ 1568 /*! @{ */ 1569 1570 #define SW_ETH_MAC_PORT0_PM1_T64N_T64n_MASK (0xFFFFFFFFFFFFFFFFU) 1571 #define SW_ETH_MAC_PORT0_PM1_T64N_T64n_SHIFT (0U) 1572 #define SW_ETH_MAC_PORT0_PM1_T64N_T64n_WIDTH (64U) 1573 #define SW_ETH_MAC_PORT0_PM1_T64N_T64n(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_T64N_T64n_SHIFT)) & SW_ETH_MAC_PORT0_PM1_T64N_T64n_MASK) 1574 /*! @} */ 1575 1576 /*! @name PM1_T127N - Port MAC 1 Transmit 65 to 127-Octet Packet Counter Register (etherStatsPkts65to127OctetsN) */ 1577 /*! @{ */ 1578 1579 #define SW_ETH_MAC_PORT0_PM1_T127N_T127n_MASK (0xFFFFFFFFFFFFFFFFU) 1580 #define SW_ETH_MAC_PORT0_PM1_T127N_T127n_SHIFT (0U) 1581 #define SW_ETH_MAC_PORT0_PM1_T127N_T127n_WIDTH (64U) 1582 #define SW_ETH_MAC_PORT0_PM1_T127N_T127n(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_T127N_T127n_SHIFT)) & SW_ETH_MAC_PORT0_PM1_T127N_T127n_MASK) 1583 /*! @} */ 1584 1585 /*! @name PM1_T255N - Port MAC 1 Transmit 128 to 255-Octet Packet Counter Register (etherStatsPkts128to255OctetsN) */ 1586 /*! @{ */ 1587 1588 #define SW_ETH_MAC_PORT0_PM1_T255N_T255n_MASK (0xFFFFFFFFFFFFFFFFU) 1589 #define SW_ETH_MAC_PORT0_PM1_T255N_T255n_SHIFT (0U) 1590 #define SW_ETH_MAC_PORT0_PM1_T255N_T255n_WIDTH (64U) 1591 #define SW_ETH_MAC_PORT0_PM1_T255N_T255n(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_T255N_T255n_SHIFT)) & SW_ETH_MAC_PORT0_PM1_T255N_T255n_MASK) 1592 /*! @} */ 1593 1594 /*! @name PM1_T511N - Port MAC 1 Transmit 256 to 511-Octet Packet Counter Register (etherStatsPkts256to511OctetsN) */ 1595 /*! @{ */ 1596 1597 #define SW_ETH_MAC_PORT0_PM1_T511N_T511n_MASK (0xFFFFFFFFFFFFFFFFU) 1598 #define SW_ETH_MAC_PORT0_PM1_T511N_T511n_SHIFT (0U) 1599 #define SW_ETH_MAC_PORT0_PM1_T511N_T511n_WIDTH (64U) 1600 #define SW_ETH_MAC_PORT0_PM1_T511N_T511n(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_T511N_T511n_SHIFT)) & SW_ETH_MAC_PORT0_PM1_T511N_T511n_MASK) 1601 /*! @} */ 1602 1603 /*! @name PM1_T1023N - Port MAC 1 Transmit 512 to 1023-Octet Packet Counter Register (etherStatsPkts512to1023OctetsN) */ 1604 /*! @{ */ 1605 1606 #define SW_ETH_MAC_PORT0_PM1_T1023N_T1023n_MASK (0xFFFFFFFFFFFFFFFFU) 1607 #define SW_ETH_MAC_PORT0_PM1_T1023N_T1023n_SHIFT (0U) 1608 #define SW_ETH_MAC_PORT0_PM1_T1023N_T1023n_WIDTH (64U) 1609 #define SW_ETH_MAC_PORT0_PM1_T1023N_T1023n(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_T1023N_T1023n_SHIFT)) & SW_ETH_MAC_PORT0_PM1_T1023N_T1023n_MASK) 1610 /*! @} */ 1611 1612 /*! @name PM1_T1522N - Port MAC 1 Transmit 1024 to 1522-Octet Packet Counter Register (etherStatsPkts1024to1522OctetsN) */ 1613 /*! @{ */ 1614 1615 #define SW_ETH_MAC_PORT0_PM1_T1522N_T1522n_MASK (0xFFFFFFFFFFFFFFFFU) 1616 #define SW_ETH_MAC_PORT0_PM1_T1522N_T1522n_SHIFT (0U) 1617 #define SW_ETH_MAC_PORT0_PM1_T1522N_T1522n_WIDTH (64U) 1618 #define SW_ETH_MAC_PORT0_PM1_T1522N_T1522n(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_T1522N_T1522n_SHIFT)) & SW_ETH_MAC_PORT0_PM1_T1522N_T1522n_MASK) 1619 /*! @} */ 1620 1621 /*! @name PM1_T1523XN - Port MAC 1 Transmit 1523 to TX_MTU-Octet Packet Counter Register (etherStatsPkts1523toMaxOctetsN) */ 1622 /*! @{ */ 1623 1624 #define SW_ETH_MAC_PORT0_PM1_T1523XN_T1523Xn_MASK (0xFFFFFFFFFFFFFFFFU) 1625 #define SW_ETH_MAC_PORT0_PM1_T1523XN_T1523Xn_SHIFT (0U) 1626 #define SW_ETH_MAC_PORT0_PM1_T1523XN_T1523Xn_WIDTH (64U) 1627 #define SW_ETH_MAC_PORT0_PM1_T1523XN_T1523Xn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_T1523XN_T1523Xn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_T1523XN_T1523Xn_MASK) 1628 /*! @} */ 1629 1630 /*! @name PM1_TCNPN - Port MAC 1 Transmit Control Packet Counter Register */ 1631 /*! @{ */ 1632 1633 #define SW_ETH_MAC_PORT0_PM1_TCNPN_TCNPn_MASK (0xFFFFFFFFFFFFFFFFU) 1634 #define SW_ETH_MAC_PORT0_PM1_TCNPN_TCNPn_SHIFT (0U) 1635 #define SW_ETH_MAC_PORT0_PM1_TCNPN_TCNPn_WIDTH (64U) 1636 #define SW_ETH_MAC_PORT0_PM1_TCNPN_TCNPn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_TCNPN_TCNPn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_TCNPN_TCNPn_MASK) 1637 /*! @} */ 1638 1639 /*! @name PM1_TDFRN - Port MAC 1 Transmit Deferred Packet Counter Register(aFramesWithDeferredXmissions) */ 1640 /*! @{ */ 1641 1642 #define SW_ETH_MAC_PORT0_PM1_TDFRN_TDFRn_MASK (0xFFFFFFFFFFFFFFFFU) 1643 #define SW_ETH_MAC_PORT0_PM1_TDFRN_TDFRn_SHIFT (0U) 1644 #define SW_ETH_MAC_PORT0_PM1_TDFRN_TDFRn_WIDTH (64U) 1645 #define SW_ETH_MAC_PORT0_PM1_TDFRN_TDFRn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_TDFRN_TDFRn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_TDFRN_TDFRn_MASK) 1646 /*! @} */ 1647 1648 /*! @name PM1_TMCOLN - Port MAC 1 Transmit Multiple Collisions Counter Register(aMultipleCollisionFrames) */ 1649 /*! @{ */ 1650 1651 #define SW_ETH_MAC_PORT0_PM1_TMCOLN_TMCOLn_MASK (0xFFFFFFFFFFFFFFFFU) 1652 #define SW_ETH_MAC_PORT0_PM1_TMCOLN_TMCOLn_SHIFT (0U) 1653 #define SW_ETH_MAC_PORT0_PM1_TMCOLN_TMCOLn_WIDTH (64U) 1654 #define SW_ETH_MAC_PORT0_PM1_TMCOLN_TMCOLn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_TMCOLN_TMCOLn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_TMCOLN_TMCOLn_MASK) 1655 /*! @} */ 1656 1657 /*! @name PM1_TSCOLN - Port MAC 1 Transmit Single Collision Counter(aSingleCollisionFrames) Register */ 1658 /*! @{ */ 1659 1660 #define SW_ETH_MAC_PORT0_PM1_TSCOLN_TSCOLn_MASK (0xFFFFFFFFFFFFFFFFU) 1661 #define SW_ETH_MAC_PORT0_PM1_TSCOLN_TSCOLn_SHIFT (0U) 1662 #define SW_ETH_MAC_PORT0_PM1_TSCOLN_TSCOLn_WIDTH (64U) 1663 #define SW_ETH_MAC_PORT0_PM1_TSCOLN_TSCOLn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_TSCOLN_TSCOLn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_TSCOLN_TSCOLn_MASK) 1664 /*! @} */ 1665 1666 /*! @name PM1_TLCOLN - Port MAC 1 Transmit Late Collision Counter(aLateCollisions) Register */ 1667 /*! @{ */ 1668 1669 #define SW_ETH_MAC_PORT0_PM1_TLCOLN_TLCOLn_MASK (0xFFFFFFFFFFFFFFFFU) 1670 #define SW_ETH_MAC_PORT0_PM1_TLCOLN_TLCOLn_SHIFT (0U) 1671 #define SW_ETH_MAC_PORT0_PM1_TLCOLN_TLCOLn_WIDTH (64U) 1672 #define SW_ETH_MAC_PORT0_PM1_TLCOLN_TLCOLn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_TLCOLN_TLCOLn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_TLCOLN_TLCOLn_MASK) 1673 /*! @} */ 1674 1675 /*! @name PM1_TECOLN - Port MAC 1 Transmit Excessive Collisions Counter Register */ 1676 /*! @{ */ 1677 1678 #define SW_ETH_MAC_PORT0_PM1_TECOLN_TECOLn_MASK (0xFFFFFFFFFFFFFFFFU) 1679 #define SW_ETH_MAC_PORT0_PM1_TECOLN_TECOLn_SHIFT (0U) 1680 #define SW_ETH_MAC_PORT0_PM1_TECOLN_TECOLn_WIDTH (64U) 1681 #define SW_ETH_MAC_PORT0_PM1_TECOLN_TECOLn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_TECOLN_TECOLn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_TECOLN_TECOLn_MASK) 1682 /*! @} */ 1683 1684 /*! @name PM1_IF_MODE - Port MAC 1 Interface Mode Control Register */ 1685 /*! @{ */ 1686 1687 #define SW_ETH_MAC_PORT0_PM1_IF_MODE_IFMODE_MASK (0x7U) 1688 #define SW_ETH_MAC_PORT0_PM1_IF_MODE_IFMODE_SHIFT (0U) 1689 #define SW_ETH_MAC_PORT0_PM1_IF_MODE_IFMODE_WIDTH (3U) 1690 #define SW_ETH_MAC_PORT0_PM1_IF_MODE_IFMODE(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_IF_MODE_IFMODE_SHIFT)) & SW_ETH_MAC_PORT0_PM1_IF_MODE_IFMODE_MASK) 1691 1692 #define SW_ETH_MAC_PORT0_PM1_IF_MODE_REVMII_MASK (0x8U) 1693 #define SW_ETH_MAC_PORT0_PM1_IF_MODE_REVMII_SHIFT (3U) 1694 #define SW_ETH_MAC_PORT0_PM1_IF_MODE_REVMII_WIDTH (1U) 1695 #define SW_ETH_MAC_PORT0_PM1_IF_MODE_REVMII(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_IF_MODE_REVMII_SHIFT)) & SW_ETH_MAC_PORT0_PM1_IF_MODE_REVMII_MASK) 1696 1697 #define SW_ETH_MAC_PORT0_PM1_IF_MODE_M10_MASK (0x10U) 1698 #define SW_ETH_MAC_PORT0_PM1_IF_MODE_M10_SHIFT (4U) 1699 #define SW_ETH_MAC_PORT0_PM1_IF_MODE_M10_WIDTH (1U) 1700 #define SW_ETH_MAC_PORT0_PM1_IF_MODE_M10(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_IF_MODE_M10_SHIFT)) & SW_ETH_MAC_PORT0_PM1_IF_MODE_M10_MASK) 1701 1702 #define SW_ETH_MAC_PORT0_PM1_IF_MODE_HD_MASK (0x40U) 1703 #define SW_ETH_MAC_PORT0_PM1_IF_MODE_HD_SHIFT (6U) 1704 #define SW_ETH_MAC_PORT0_PM1_IF_MODE_HD_WIDTH (1U) 1705 #define SW_ETH_MAC_PORT0_PM1_IF_MODE_HD(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_IF_MODE_HD_SHIFT)) & SW_ETH_MAC_PORT0_PM1_IF_MODE_HD_MASK) 1706 1707 #define SW_ETH_MAC_PORT0_PM1_IF_MODE_SSP_MASK (0x6000U) 1708 #define SW_ETH_MAC_PORT0_PM1_IF_MODE_SSP_SHIFT (13U) 1709 #define SW_ETH_MAC_PORT0_PM1_IF_MODE_SSP_WIDTH (2U) 1710 #define SW_ETH_MAC_PORT0_PM1_IF_MODE_SSP(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_IF_MODE_SSP_SHIFT)) & SW_ETH_MAC_PORT0_PM1_IF_MODE_SSP_MASK) 1711 /*! @} */ 1712 1713 /*! @name MAC_MERGE_MMCSR - Port MAC Merge Control and Status Register */ 1714 /*! @{ */ 1715 1716 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LPS_MASK (0x1U) 1717 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LPS_SHIFT (0U) 1718 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LPS_WIDTH (1U) 1719 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LPS(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LPS_SHIFT)) & SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LPS_MASK) 1720 1721 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LPE_MASK (0x2U) 1722 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LPE_SHIFT (1U) 1723 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LPE_WIDTH (1U) 1724 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LPE(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LPE_SHIFT)) & SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LPE_MASK) 1725 1726 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LPA_MASK (0x4U) 1727 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LPA_SHIFT (2U) 1728 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LPA_WIDTH (1U) 1729 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LPA(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LPA_SHIFT)) & SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LPA_MASK) 1730 1731 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LAFS_MASK (0x18U) 1732 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LAFS_SHIFT (3U) 1733 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LAFS_WIDTH (2U) 1734 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LAFS(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LAFS_SHIFT)) & SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LAFS_MASK) 1735 1736 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_RPS_MASK (0x20U) 1737 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_RPS_SHIFT (5U) 1738 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_RPS_WIDTH (1U) 1739 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_RPS(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_RPS_SHIFT)) & SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_RPS_MASK) 1740 1741 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_RPE_MASK (0x40U) 1742 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_RPE_SHIFT (6U) 1743 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_RPE_WIDTH (1U) 1744 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_RPE(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_RPE_SHIFT)) & SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_RPE_MASK) 1745 1746 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_RPA_MASK (0x80U) 1747 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_RPA_SHIFT (7U) 1748 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_RPA_WIDTH (1U) 1749 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_RPA(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_RPA_SHIFT)) & SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_RPA_MASK) 1750 1751 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_RAFS_MASK (0x300U) 1752 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_RAFS_SHIFT (8U) 1753 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_RAFS_WIDTH (2U) 1754 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_RAFS(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_RAFS_SHIFT)) & SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_RAFS_MASK) 1755 1756 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_ME_MASK (0x18000U) 1757 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_ME_SHIFT (15U) 1758 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_ME_WIDTH (2U) 1759 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_ME(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_ME_SHIFT)) & SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_ME_MASK) 1760 1761 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_VDIS_MASK (0x20000U) 1762 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_VDIS_SHIFT (17U) 1763 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_VDIS_WIDTH (1U) 1764 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_VDIS(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_VDIS_SHIFT)) & SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_VDIS_MASK) 1765 1766 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_VSTS_MASK (0x1C0000U) 1767 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_VSTS_SHIFT (18U) 1768 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_VSTS_WIDTH (3U) 1769 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_VSTS(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_VSTS_SHIFT)) & SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_VSTS_MASK) 1770 1771 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_TXSTS_MASK (0x600000U) 1772 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_TXSTS_SHIFT (21U) 1773 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_TXSTS_WIDTH (2U) 1774 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_TXSTS(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_TXSTS_SHIFT)) & SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_TXSTS_MASK) 1775 1776 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_VT_MASK (0x3F800000U) 1777 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_VT_SHIFT (23U) 1778 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_VT_WIDTH (7U) 1779 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_VT(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_VT_SHIFT)) & SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_VT_MASK) 1780 1781 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LINK_FAIL_MASK (0x80000000U) 1782 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LINK_FAIL_SHIFT (31U) 1783 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LINK_FAIL_WIDTH (1U) 1784 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LINK_FAIL(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LINK_FAIL_SHIFT)) & SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LINK_FAIL_MASK) 1785 /*! @} */ 1786 1787 /*! @name MAC_MERGE_MMFAECR - Port MAC Merge Frame Assembly Error Count Register */ 1788 /*! @{ */ 1789 1790 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMFAECR_MMFAEC_MASK (0xFFFFFFFFU) 1791 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMFAECR_MMFAEC_SHIFT (0U) 1792 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMFAECR_MMFAEC_WIDTH (32U) 1793 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMFAECR_MMFAEC(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_MAC_MERGE_MMFAECR_MMFAEC_SHIFT)) & SW_ETH_MAC_PORT0_MAC_MERGE_MMFAECR_MMFAEC_MASK) 1794 /*! @} */ 1795 1796 /*! @name MAC_MERGE_MMFSECR - Port MAC Merge Frame SMD Error Count Register */ 1797 /*! @{ */ 1798 1799 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMFSECR_MMFSEC_MASK (0xFFFFFFFFU) 1800 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMFSECR_MMFSEC_SHIFT (0U) 1801 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMFSECR_MMFSEC_WIDTH (32U) 1802 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMFSECR_MMFSEC(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_MAC_MERGE_MMFSECR_MMFSEC_SHIFT)) & SW_ETH_MAC_PORT0_MAC_MERGE_MMFSECR_MMFSEC_MASK) 1803 /*! @} */ 1804 1805 /*! @name MAC_MERGE_MMFAOCR - Port MAC Merge Frame Assembly OK Count Register */ 1806 /*! @{ */ 1807 1808 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMFAOCR_MMFAOC_MASK (0xFFFFFFFFU) 1809 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMFAOCR_MMFAOC_SHIFT (0U) 1810 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMFAOCR_MMFAOC_WIDTH (32U) 1811 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMFAOCR_MMFAOC(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_MAC_MERGE_MMFAOCR_MMFAOC_SHIFT)) & SW_ETH_MAC_PORT0_MAC_MERGE_MMFAOCR_MMFAOC_MASK) 1812 /*! @} */ 1813 1814 /*! @name MAC_MERGE_MMFCRXR - Port MAC Merge Fragment Count RX Register */ 1815 /*! @{ */ 1816 1817 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMFCRXR_MMFCRX_MASK (0xFFFFFFFFU) 1818 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMFCRXR_MMFCRX_SHIFT (0U) 1819 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMFCRXR_MMFCRX_WIDTH (32U) 1820 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMFCRXR_MMFCRX(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_MAC_MERGE_MMFCRXR_MMFCRX_SHIFT)) & SW_ETH_MAC_PORT0_MAC_MERGE_MMFCRXR_MMFCRX_MASK) 1821 /*! @} */ 1822 1823 /*! @name MAC_MERGE_MMFCTXR - Port MAC Merge Fragment Count TX Register */ 1824 /*! @{ */ 1825 1826 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMFCTXR_MMFCTX_MASK (0xFFFFFFFFU) 1827 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMFCTXR_MMFCTX_SHIFT (0U) 1828 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMFCTXR_MMFCTX_WIDTH (32U) 1829 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMFCTXR_MMFCTX(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_MAC_MERGE_MMFCTXR_MMFCTX_SHIFT)) & SW_ETH_MAC_PORT0_MAC_MERGE_MMFCTXR_MMFCTX_MASK) 1830 /*! @} */ 1831 1832 /*! @name MAC_MERGE_MMHCR - Port MAC Merge Hold Count Register */ 1833 /*! @{ */ 1834 1835 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMHCR_MMHC_MASK (0xFFFFFFFFU) 1836 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMHCR_MMHC_SHIFT (0U) 1837 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMHCR_MMHC_WIDTH (32U) 1838 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMHCR_MMHC(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_MAC_MERGE_MMHCR_MMHC_SHIFT)) & SW_ETH_MAC_PORT0_MAC_MERGE_MMHCR_MMHC_MASK) 1839 /*! @} */ 1840 1841 /*! @name PEMDIOCR - Port external MDIO configuration register */ 1842 /*! @{ */ 1843 1844 #define SW_ETH_MAC_PORT0_PEMDIOCR_BSY2_MASK (0x1U) 1845 #define SW_ETH_MAC_PORT0_PEMDIOCR_BSY2_SHIFT (0U) 1846 #define SW_ETH_MAC_PORT0_PEMDIOCR_BSY2_WIDTH (1U) 1847 #define SW_ETH_MAC_PORT0_PEMDIOCR_BSY2(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PEMDIOCR_BSY2_SHIFT)) & SW_ETH_MAC_PORT0_PEMDIOCR_BSY2_MASK) 1848 1849 #define SW_ETH_MAC_PORT0_PEMDIOCR_MDIO_RD_ER_MASK (0x2U) 1850 #define SW_ETH_MAC_PORT0_PEMDIOCR_MDIO_RD_ER_SHIFT (1U) 1851 #define SW_ETH_MAC_PORT0_PEMDIOCR_MDIO_RD_ER_WIDTH (1U) 1852 #define SW_ETH_MAC_PORT0_PEMDIOCR_MDIO_RD_ER(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PEMDIOCR_MDIO_RD_ER_SHIFT)) & SW_ETH_MAC_PORT0_PEMDIOCR_MDIO_RD_ER_MASK) 1853 1854 #define SW_ETH_MAC_PORT0_PEMDIOCR_MDIO_HOLD_MASK (0x1CU) 1855 #define SW_ETH_MAC_PORT0_PEMDIOCR_MDIO_HOLD_SHIFT (2U) 1856 #define SW_ETH_MAC_PORT0_PEMDIOCR_MDIO_HOLD_WIDTH (3U) 1857 #define SW_ETH_MAC_PORT0_PEMDIOCR_MDIO_HOLD(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PEMDIOCR_MDIO_HOLD_SHIFT)) & SW_ETH_MAC_PORT0_PEMDIOCR_MDIO_HOLD_MASK) 1858 1859 #define SW_ETH_MAC_PORT0_PEMDIOCR_PRE_DIS_MASK (0x20U) 1860 #define SW_ETH_MAC_PORT0_PEMDIOCR_PRE_DIS_SHIFT (5U) 1861 #define SW_ETH_MAC_PORT0_PEMDIOCR_PRE_DIS_WIDTH (1U) 1862 #define SW_ETH_MAC_PORT0_PEMDIOCR_PRE_DIS(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PEMDIOCR_PRE_DIS_SHIFT)) & SW_ETH_MAC_PORT0_PEMDIOCR_PRE_DIS_MASK) 1863 1864 #define SW_ETH_MAC_PORT0_PEMDIOCR_ENC45_MASK (0x40U) 1865 #define SW_ETH_MAC_PORT0_PEMDIOCR_ENC45_SHIFT (6U) 1866 #define SW_ETH_MAC_PORT0_PEMDIOCR_ENC45_WIDTH (1U) 1867 #define SW_ETH_MAC_PORT0_PEMDIOCR_ENC45(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PEMDIOCR_ENC45_SHIFT)) & SW_ETH_MAC_PORT0_PEMDIOCR_ENC45_MASK) 1868 1869 #define SW_ETH_MAC_PORT0_PEMDIOCR_MDIO_CLK_DIV_MASK (0xFF80U) 1870 #define SW_ETH_MAC_PORT0_PEMDIOCR_MDIO_CLK_DIV_SHIFT (7U) 1871 #define SW_ETH_MAC_PORT0_PEMDIOCR_MDIO_CLK_DIV_WIDTH (9U) 1872 #define SW_ETH_MAC_PORT0_PEMDIOCR_MDIO_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PEMDIOCR_MDIO_CLK_DIV_SHIFT)) & SW_ETH_MAC_PORT0_PEMDIOCR_MDIO_CLK_DIV_MASK) 1873 1874 #define SW_ETH_MAC_PORT0_PEMDIOCR_WHOAMI_MASK (0x70000U) 1875 #define SW_ETH_MAC_PORT0_PEMDIOCR_WHOAMI_SHIFT (16U) 1876 #define SW_ETH_MAC_PORT0_PEMDIOCR_WHOAMI_WIDTH (3U) 1877 #define SW_ETH_MAC_PORT0_PEMDIOCR_WHOAMI(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PEMDIOCR_WHOAMI_SHIFT)) & SW_ETH_MAC_PORT0_PEMDIOCR_WHOAMI_MASK) 1878 1879 #define SW_ETH_MAC_PORT0_PEMDIOCR_EHOLD_MASK (0x400000U) 1880 #define SW_ETH_MAC_PORT0_PEMDIOCR_EHOLD_SHIFT (22U) 1881 #define SW_ETH_MAC_PORT0_PEMDIOCR_EHOLD_WIDTH (1U) 1882 #define SW_ETH_MAC_PORT0_PEMDIOCR_EHOLD(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PEMDIOCR_EHOLD_SHIFT)) & SW_ETH_MAC_PORT0_PEMDIOCR_EHOLD_MASK) 1883 1884 #define SW_ETH_MAC_PORT0_PEMDIOCR_NEG_MASK (0x800000U) 1885 #define SW_ETH_MAC_PORT0_PEMDIOCR_NEG_SHIFT (23U) 1886 #define SW_ETH_MAC_PORT0_PEMDIOCR_NEG_WIDTH (1U) 1887 #define SW_ETH_MAC_PORT0_PEMDIOCR_NEG(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PEMDIOCR_NEG_SHIFT)) & SW_ETH_MAC_PORT0_PEMDIOCR_NEG_MASK) 1888 1889 #define SW_ETH_MAC_PORT0_PEMDIOCR_ADDR_ERR_MASK (0x10000000U) 1890 #define SW_ETH_MAC_PORT0_PEMDIOCR_ADDR_ERR_SHIFT (28U) 1891 #define SW_ETH_MAC_PORT0_PEMDIOCR_ADDR_ERR_WIDTH (1U) 1892 #define SW_ETH_MAC_PORT0_PEMDIOCR_ADDR_ERR(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PEMDIOCR_ADDR_ERR_SHIFT)) & SW_ETH_MAC_PORT0_PEMDIOCR_ADDR_ERR_MASK) 1893 1894 #define SW_ETH_MAC_PORT0_PEMDIOCR_CIM_MASK (0x20000000U) 1895 #define SW_ETH_MAC_PORT0_PEMDIOCR_CIM_SHIFT (29U) 1896 #define SW_ETH_MAC_PORT0_PEMDIOCR_CIM_WIDTH (1U) 1897 #define SW_ETH_MAC_PORT0_PEMDIOCR_CIM(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PEMDIOCR_CIM_SHIFT)) & SW_ETH_MAC_PORT0_PEMDIOCR_CIM_MASK) 1898 1899 #define SW_ETH_MAC_PORT0_PEMDIOCR_CMP_MASK (0x40000000U) 1900 #define SW_ETH_MAC_PORT0_PEMDIOCR_CMP_SHIFT (30U) 1901 #define SW_ETH_MAC_PORT0_PEMDIOCR_CMP_WIDTH (1U) 1902 #define SW_ETH_MAC_PORT0_PEMDIOCR_CMP(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PEMDIOCR_CMP_SHIFT)) & SW_ETH_MAC_PORT0_PEMDIOCR_CMP_MASK) 1903 1904 #define SW_ETH_MAC_PORT0_PEMDIOCR_BSY1_MASK (0x80000000U) 1905 #define SW_ETH_MAC_PORT0_PEMDIOCR_BSY1_SHIFT (31U) 1906 #define SW_ETH_MAC_PORT0_PEMDIOCR_BSY1_WIDTH (1U) 1907 #define SW_ETH_MAC_PORT0_PEMDIOCR_BSY1(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PEMDIOCR_BSY1_SHIFT)) & SW_ETH_MAC_PORT0_PEMDIOCR_BSY1_MASK) 1908 /*! @} */ 1909 1910 /*! @name PEMDIOICR - Port external MDIO interface control register */ 1911 /*! @{ */ 1912 1913 #define SW_ETH_MAC_PORT0_PEMDIOICR_DEV_ADDR_MASK (0x1FU) 1914 #define SW_ETH_MAC_PORT0_PEMDIOICR_DEV_ADDR_SHIFT (0U) 1915 #define SW_ETH_MAC_PORT0_PEMDIOICR_DEV_ADDR_WIDTH (5U) 1916 #define SW_ETH_MAC_PORT0_PEMDIOICR_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PEMDIOICR_DEV_ADDR_SHIFT)) & SW_ETH_MAC_PORT0_PEMDIOICR_DEV_ADDR_MASK) 1917 1918 #define SW_ETH_MAC_PORT0_PEMDIOICR_PORT_ADDR_MASK (0x3E0U) 1919 #define SW_ETH_MAC_PORT0_PEMDIOICR_PORT_ADDR_SHIFT (5U) 1920 #define SW_ETH_MAC_PORT0_PEMDIOICR_PORT_ADDR_WIDTH (5U) 1921 #define SW_ETH_MAC_PORT0_PEMDIOICR_PORT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PEMDIOICR_PORT_ADDR_SHIFT)) & SW_ETH_MAC_PORT0_PEMDIOICR_PORT_ADDR_MASK) 1922 1923 #define SW_ETH_MAC_PORT0_PEMDIOICR_POST_INC_MASK (0x4000U) 1924 #define SW_ETH_MAC_PORT0_PEMDIOICR_POST_INC_SHIFT (14U) 1925 #define SW_ETH_MAC_PORT0_PEMDIOICR_POST_INC_WIDTH (1U) 1926 #define SW_ETH_MAC_PORT0_PEMDIOICR_POST_INC(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PEMDIOICR_POST_INC_SHIFT)) & SW_ETH_MAC_PORT0_PEMDIOICR_POST_INC_MASK) 1927 1928 #define SW_ETH_MAC_PORT0_PEMDIOICR_READ_MASK (0x8000U) 1929 #define SW_ETH_MAC_PORT0_PEMDIOICR_READ_SHIFT (15U) 1930 #define SW_ETH_MAC_PORT0_PEMDIOICR_READ_WIDTH (1U) 1931 #define SW_ETH_MAC_PORT0_PEMDIOICR_READ(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PEMDIOICR_READ_SHIFT)) & SW_ETH_MAC_PORT0_PEMDIOICR_READ_MASK) 1932 1933 #define SW_ETH_MAC_PORT0_PEMDIOICR_BSY_MASK (0x80000000U) 1934 #define SW_ETH_MAC_PORT0_PEMDIOICR_BSY_SHIFT (31U) 1935 #define SW_ETH_MAC_PORT0_PEMDIOICR_BSY_WIDTH (1U) 1936 #define SW_ETH_MAC_PORT0_PEMDIOICR_BSY(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PEMDIOICR_BSY_SHIFT)) & SW_ETH_MAC_PORT0_PEMDIOICR_BSY_MASK) 1937 /*! @} */ 1938 1939 /*! @name PEMDIOIDR - Port external MDIO interface data register */ 1940 /*! @{ */ 1941 1942 #define SW_ETH_MAC_PORT0_PEMDIOIDR_MDIO_DATA_MASK (0xFFFFU) 1943 #define SW_ETH_MAC_PORT0_PEMDIOIDR_MDIO_DATA_SHIFT (0U) 1944 #define SW_ETH_MAC_PORT0_PEMDIOIDR_MDIO_DATA_WIDTH (16U) 1945 #define SW_ETH_MAC_PORT0_PEMDIOIDR_MDIO_DATA(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PEMDIOIDR_MDIO_DATA_SHIFT)) & SW_ETH_MAC_PORT0_PEMDIOIDR_MDIO_DATA_MASK) 1946 /*! @} */ 1947 1948 /*! @name PEMDIORAR - Port external MDIO register address register */ 1949 /*! @{ */ 1950 1951 #define SW_ETH_MAC_PORT0_PEMDIORAR_REGADDR_MASK (0xFFFFU) 1952 #define SW_ETH_MAC_PORT0_PEMDIORAR_REGADDR_SHIFT (0U) 1953 #define SW_ETH_MAC_PORT0_PEMDIORAR_REGADDR_WIDTH (16U) 1954 #define SW_ETH_MAC_PORT0_PEMDIORAR_REGADDR(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PEMDIORAR_REGADDR_SHIFT)) & SW_ETH_MAC_PORT0_PEMDIORAR_REGADDR_MASK) 1955 /*! @} */ 1956 1957 /*! @name PEMDIOSR - Port external MDIO status register */ 1958 /*! @{ */ 1959 1960 #define SW_ETH_MAC_PORT0_PEMDIOSR_BSY_MASK (0x1U) 1961 #define SW_ETH_MAC_PORT0_PEMDIOSR_BSY_SHIFT (0U) 1962 #define SW_ETH_MAC_PORT0_PEMDIOSR_BSY_WIDTH (1U) 1963 #define SW_ETH_MAC_PORT0_PEMDIOSR_BSY(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PEMDIOSR_BSY_SHIFT)) & SW_ETH_MAC_PORT0_PEMDIOSR_BSY_MASK) 1964 1965 #define SW_ETH_MAC_PORT0_PEMDIOSR_WHT_LIST_MASK (0x1F00U) 1966 #define SW_ETH_MAC_PORT0_PEMDIOSR_WHT_LIST_SHIFT (8U) 1967 #define SW_ETH_MAC_PORT0_PEMDIOSR_WHT_LIST_WIDTH (5U) 1968 #define SW_ETH_MAC_PORT0_PEMDIOSR_WHT_LIST(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PEMDIOSR_WHT_LIST_SHIFT)) & SW_ETH_MAC_PORT0_PEMDIOSR_WHT_LIST_MASK) 1969 1970 #define SW_ETH_MAC_PORT0_PEMDIOSR_WHT_LIST_ENA_MASK (0x8000U) 1971 #define SW_ETH_MAC_PORT0_PEMDIOSR_WHT_LIST_ENA_SHIFT (15U) 1972 #define SW_ETH_MAC_PORT0_PEMDIOSR_WHT_LIST_ENA_WIDTH (1U) 1973 #define SW_ETH_MAC_PORT0_PEMDIOSR_WHT_LIST_ENA(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PEMDIOSR_WHT_LIST_ENA_SHIFT)) & SW_ETH_MAC_PORT0_PEMDIOSR_WHT_LIST_ENA_MASK) 1974 1975 #define SW_ETH_MAC_PORT0_PEMDIOSR_PORT_ID_MASK (0x70000U) 1976 #define SW_ETH_MAC_PORT0_PEMDIOSR_PORT_ID_SHIFT (16U) 1977 #define SW_ETH_MAC_PORT0_PEMDIOSR_PORT_ID_WIDTH (3U) 1978 #define SW_ETH_MAC_PORT0_PEMDIOSR_PORT_ID(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PEMDIOSR_PORT_ID_SHIFT)) & SW_ETH_MAC_PORT0_PEMDIOSR_PORT_ID_MASK) 1979 1980 #define SW_ETH_MAC_PORT0_PEMDIOSR_REQ_TYPE_MASK (0x80000U) 1981 #define SW_ETH_MAC_PORT0_PEMDIOSR_REQ_TYPE_SHIFT (19U) 1982 #define SW_ETH_MAC_PORT0_PEMDIOSR_REQ_TYPE_WIDTH (1U) 1983 #define SW_ETH_MAC_PORT0_PEMDIOSR_REQ_TYPE(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PEMDIOSR_REQ_TYPE_SHIFT)) & SW_ETH_MAC_PORT0_PEMDIOSR_REQ_TYPE_MASK) 1984 /*! @} */ 1985 1986 /*! @name PPSCR - PHY status configuration register */ 1987 /*! @{ */ 1988 1989 #define SW_ETH_MAC_PORT0_PPSCR_BSY_MASK (0x1U) 1990 #define SW_ETH_MAC_PORT0_PPSCR_BSY_SHIFT (0U) 1991 #define SW_ETH_MAC_PORT0_PPSCR_BSY_WIDTH (1U) 1992 #define SW_ETH_MAC_PORT0_PPSCR_BSY(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PPSCR_BSY_SHIFT)) & SW_ETH_MAC_PORT0_PPSCR_BSY_MASK) 1993 1994 #define SW_ETH_MAC_PORT0_PPSCR_MDIO_RD_ER_MASK (0x2U) 1995 #define SW_ETH_MAC_PORT0_PPSCR_MDIO_RD_ER_SHIFT (1U) 1996 #define SW_ETH_MAC_PORT0_PPSCR_MDIO_RD_ER_WIDTH (1U) 1997 #define SW_ETH_MAC_PORT0_PPSCR_MDIO_RD_ER(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PPSCR_MDIO_RD_ER_SHIFT)) & SW_ETH_MAC_PORT0_PPSCR_MDIO_RD_ER_MASK) 1998 1999 #define SW_ETH_MAC_PORT0_PPSCR_STATUS_INTERVAL_MASK (0xFFFF0000U) 2000 #define SW_ETH_MAC_PORT0_PPSCR_STATUS_INTERVAL_SHIFT (16U) 2001 #define SW_ETH_MAC_PORT0_PPSCR_STATUS_INTERVAL_WIDTH (16U) 2002 #define SW_ETH_MAC_PORT0_PPSCR_STATUS_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PPSCR_STATUS_INTERVAL_SHIFT)) & SW_ETH_MAC_PORT0_PPSCR_STATUS_INTERVAL_MASK) 2003 /*! @} */ 2004 2005 /*! @name PPSCTRLR - Port PHY status control register */ 2006 /*! @{ */ 2007 2008 #define SW_ETH_MAC_PORT0_PPSCTRLR_DEV_ADDR_MASK (0x1FU) 2009 #define SW_ETH_MAC_PORT0_PPSCTRLR_DEV_ADDR_SHIFT (0U) 2010 #define SW_ETH_MAC_PORT0_PPSCTRLR_DEV_ADDR_WIDTH (5U) 2011 #define SW_ETH_MAC_PORT0_PPSCTRLR_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PPSCTRLR_DEV_ADDR_SHIFT)) & SW_ETH_MAC_PORT0_PPSCTRLR_DEV_ADDR_MASK) 2012 2013 #define SW_ETH_MAC_PORT0_PPSCTRLR_PORT_ADDR_MASK (0x3E0U) 2014 #define SW_ETH_MAC_PORT0_PPSCTRLR_PORT_ADDR_SHIFT (5U) 2015 #define SW_ETH_MAC_PORT0_PPSCTRLR_PORT_ADDR_WIDTH (5U) 2016 #define SW_ETH_MAC_PORT0_PPSCTRLR_PORT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PPSCTRLR_PORT_ADDR_SHIFT)) & SW_ETH_MAC_PORT0_PPSCTRLR_PORT_ADDR_MASK) 2017 /*! @} */ 2018 2019 /*! @name PPSDR - Port PHY status data register */ 2020 /*! @{ */ 2021 2022 #define SW_ETH_MAC_PORT0_PPSDR_MDIO_DATA_MASK (0xFFFFU) 2023 #define SW_ETH_MAC_PORT0_PPSDR_MDIO_DATA_SHIFT (0U) 2024 #define SW_ETH_MAC_PORT0_PPSDR_MDIO_DATA_WIDTH (16U) 2025 #define SW_ETH_MAC_PORT0_PPSDR_MDIO_DATA(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PPSDR_MDIO_DATA_SHIFT)) & SW_ETH_MAC_PORT0_PPSDR_MDIO_DATA_MASK) 2026 2027 #define SW_ETH_MAC_PORT0_PPSDR_CURR_CNT_MASK (0xFFFF0000U) 2028 #define SW_ETH_MAC_PORT0_PPSDR_CURR_CNT_SHIFT (16U) 2029 #define SW_ETH_MAC_PORT0_PPSDR_CURR_CNT_WIDTH (16U) 2030 #define SW_ETH_MAC_PORT0_PPSDR_CURR_CNT(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PPSDR_CURR_CNT_SHIFT)) & SW_ETH_MAC_PORT0_PPSDR_CURR_CNT_MASK) 2031 /*! @} */ 2032 2033 /*! @name PPSRAR - Port PHY status register address register */ 2034 /*! @{ */ 2035 2036 #define SW_ETH_MAC_PORT0_PPSRAR_REGADDR_MASK (0xFFFFU) 2037 #define SW_ETH_MAC_PORT0_PPSRAR_REGADDR_SHIFT (0U) 2038 #define SW_ETH_MAC_PORT0_PPSRAR_REGADDR_WIDTH (16U) 2039 #define SW_ETH_MAC_PORT0_PPSRAR_REGADDR(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PPSRAR_REGADDR_SHIFT)) & SW_ETH_MAC_PORT0_PPSRAR_REGADDR_MASK) 2040 /*! @} */ 2041 2042 /*! @name PPSER - Port PHY status event register */ 2043 /*! @{ */ 2044 2045 #define SW_ETH_MAC_PORT0_PPSER_STATUS_EVENT_HL_MASK (0xFFFFU) 2046 #define SW_ETH_MAC_PORT0_PPSER_STATUS_EVENT_HL_SHIFT (0U) 2047 #define SW_ETH_MAC_PORT0_PPSER_STATUS_EVENT_HL_WIDTH (16U) 2048 #define SW_ETH_MAC_PORT0_PPSER_STATUS_EVENT_HL(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PPSER_STATUS_EVENT_HL_SHIFT)) & SW_ETH_MAC_PORT0_PPSER_STATUS_EVENT_HL_MASK) 2049 2050 #define SW_ETH_MAC_PORT0_PPSER_STATUS_EVENT_LH_MASK (0xFFFF0000U) 2051 #define SW_ETH_MAC_PORT0_PPSER_STATUS_EVENT_LH_SHIFT (16U) 2052 #define SW_ETH_MAC_PORT0_PPSER_STATUS_EVENT_LH_WIDTH (16U) 2053 #define SW_ETH_MAC_PORT0_PPSER_STATUS_EVENT_LH(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PPSER_STATUS_EVENT_LH_SHIFT)) & SW_ETH_MAC_PORT0_PPSER_STATUS_EVENT_LH_MASK) 2054 /*! @} */ 2055 2056 /*! @name PPSMR - Port PHY status mask register */ 2057 /*! @{ */ 2058 2059 #define SW_ETH_MAC_PORT0_PPSMR_STATUS_MASK_HL_MASK (0xFFFFU) 2060 #define SW_ETH_MAC_PORT0_PPSMR_STATUS_MASK_HL_SHIFT (0U) 2061 #define SW_ETH_MAC_PORT0_PPSMR_STATUS_MASK_HL_WIDTH (16U) 2062 #define SW_ETH_MAC_PORT0_PPSMR_STATUS_MASK_HL(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PPSMR_STATUS_MASK_HL_SHIFT)) & SW_ETH_MAC_PORT0_PPSMR_STATUS_MASK_HL_MASK) 2063 2064 #define SW_ETH_MAC_PORT0_PPSMR_STATUS_MASK_LH_MASK (0xFFFF0000U) 2065 #define SW_ETH_MAC_PORT0_PPSMR_STATUS_MASK_LH_SHIFT (16U) 2066 #define SW_ETH_MAC_PORT0_PPSMR_STATUS_MASK_LH_WIDTH (16U) 2067 #define SW_ETH_MAC_PORT0_PPSMR_STATUS_MASK_LH(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PPSMR_STATUS_MASK_LH_SHIFT)) & SW_ETH_MAC_PORT0_PPSMR_STATUS_MASK_LH_MASK) 2068 /*! @} */ 2069 2070 /*! 2071 * @} 2072 */ /* end of group SW_ETH_MAC_PORT0_Register_Masks */ 2073 2074 /*! 2075 * @} 2076 */ /* end of group SW_ETH_MAC_PORT0_Peripheral_Access_Layer */ 2077 2078 #endif /* #if !defined(S32Z2_SW_ETH_MAC_PORT0_H_) */ 2079
