| /hal_nxp-3.6.0/mcux/mcux-sdk/drivers/pxp/ |
| D | fsl_pxp.h | 1315 base->STAT_CLR = statusMask; in PXP_ClearStatusFlags()
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| D | fsl_pxp.c | 914 base->STAT_CLR = PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK; in PXP_LoadLutTable()
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1042/ |
| D | MIMXRT1042.h | 12827 __IO uint32_t STAT_CLR; /**< DCP status register, offset: 0x18 */ member
38514 __IO uint32_t STAT_CLR; /**< Status Register, offset: 0x18 */ member
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1052/ |
| D | MIMXRT1052.h | 12368 __IO uint32_t STAT_CLR; /**< DCP status register, offset: 0x18 */ member
37834 __IO uint32_t STAT_CLR; /**< Status Register, offset: 0x18 */ member
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1062/ |
| D | MIMXRT1062.h | 13980 __IO uint32_t STAT_CLR; /**< DCP status register, offset: 0x18 */ member
40051 __IO uint32_t STAT_CLR; /**< Status Register, offset: 0x18 */ member
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1064/ |
| D | MIMXRT1064.h | 14054 __IO uint32_t STAT_CLR; /**< DCP status register, offset: 0x18 */ member
40045 __IO uint32_t STAT_CLR; /**< Status Register, offset: 0x18 */ member
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1011/ |
| D | MIMXRT1011.h | 8259 __IO uint32_t STAT_CLR; /**< DCP status register, offset: 0x18 */ member
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1015/ |
| D | MIMXRT1015.h | 8977 __IO uint32_t STAT_CLR; /**< DCP status register, offset: 0x18 */ member
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1024/ |
| D | MIMXRT1024.h | 10541 __IO uint32_t STAT_CLR; /**< DCP status register, offset: 0x18 */ member
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1021/ |
| D | MIMXRT1021.h | 10557 __IO uint32_t STAT_CLR; /**< DCP status register, offset: 0x18 */ member
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1051/ |
| D | MIMXRT1051.h | 11583 __IO uint32_t STAT_CLR; /**< DCP status register, offset: 0x18 */ member
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1041/ |
| D | MIMXRT1041.h | 12825 __IO uint32_t STAT_CLR; /**< DCP status register, offset: 0x18 */ member
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1061/ |
| D | MIMXRT1061.h | 13194 __IO uint32_t STAT_CLR; /**< DCP status register, offset: 0x18 */ member
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1166/ |
| D | MIMXRT1166_cm4.h | 70669 __IO uint32_t STAT_CLR; /**< Status Register, offset: 0x18 */ member
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| D | MIMXRT1166_cm7.h | 69736 __IO uint32_t STAT_CLR; /**< Status Register, offset: 0x18 */ member
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1173/ |
| D | MIMXRT1173_cm7.h | 80917 __IO uint32_t STAT_CLR; /**< Status Register, offset: 0x18 */ member
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| D | MIMXRT1173_cm4.h | 81850 __IO uint32_t STAT_CLR; /**< Status Register, offset: 0x18 */ member
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1172/ |
| D | MIMXRT1172.h | 80920 __IO uint32_t STAT_CLR; /**< Status Register, offset: 0x18 */ member
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1176/ |
| D | MIMXRT1176_cm7.h | 80920 __IO uint32_t STAT_CLR; /**< Status Register, offset: 0x18 */ member
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| D | MIMXRT1176_cm4.h | 81853 __IO uint32_t STAT_CLR; /**< Status Register, offset: 0x18 */ member
|
