1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2023 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_SPI.h 10 * @version 2.1 11 * @date 2023-07-20 12 * @brief Peripheral Access Layer for S32Z2_SPI 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_SPI_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_SPI_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- SPI Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer 68 * @{ 69 */ 70 71 /** SPI - Size of Registers Arrays */ 72 #define SPI_MODE_CTAR_CTAR_COUNT 6u 73 #define SPI_MODE_CTAR_SLAVE_CTAR_SLAVE_COUNT 1u 74 #define SPI_TXFR_COUNT 5u 75 #define SPI_RXFR_COUNT 5u 76 #define SPI_CTARE_COUNT 6u 77 78 /** SPI - Register Layout Typedef */ 79 typedef struct { 80 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ 81 uint8_t RESERVED_0[4]; 82 __IO uint32_t TCR; /**< Transfer Count Register, offset: 0x8 */ 83 union { /* offset: 0xC */ 84 __IO uint32_t CTAR[SPI_MODE_CTAR_CTAR_COUNT]; /**< Clock and Transfer Attributes Register (in Master mode), array offset: 0xC, array step: 0x4 */ 85 __IO uint32_t CTAR_SLAVE[SPI_MODE_CTAR_SLAVE_CTAR_SLAVE_COUNT]; /**< Clock and Transfer Attributes Register (in Slave mode), array offset: 0xC, array step: 0x4 */ 86 } MODE; 87 uint8_t RESERVED_1[8]; 88 __IO uint32_t SR; /**< Status Register, offset: 0x2C */ 89 __IO uint32_t RSER; /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */ 90 union { /* offset: 0x34 */ 91 struct { /* offset: 0x34 */ 92 __IO uint16_t TX; /**< SPI_TX register, offset: 0x34 */ 93 __IO uint16_t CMD; /**< SPI_CMD register, offset: 0x36 */ 94 } FIFO; 95 __IO uint32_t PUSHR; /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */ 96 __IO uint32_t PUSHR_SLAVE; /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */ 97 } PUSHR; 98 __I uint32_t POPR; /**< POP RX FIFO Register, offset: 0x38 */ 99 __I uint32_t TXFR[SPI_TXFR_COUNT]; /**< Transmit FIFO Registers, array offset: 0x3C, array step: 0x4 */ 100 uint8_t RESERVED_2[44]; 101 __I uint32_t RXFR[SPI_RXFR_COUNT]; /**< Receive FIFO Registers, array offset: 0x7C, array step: 0x4 */ 102 uint8_t RESERVED_3[140]; 103 __IO uint32_t CTARE[SPI_CTARE_COUNT]; /**< Clock and Transfer Attributes Register Extended, array offset: 0x11C, array step: 0x4 */ 104 uint8_t RESERVED_4[8]; 105 __I uint32_t SREX; /**< Status Register Extended, offset: 0x13C */ 106 } SPI_Type, *SPI_MemMapPtr; 107 108 /** Number of instances of the SPI module. */ 109 #define SPI_INSTANCE_COUNT (10) 110 111 /* SPI - Peripheral instance base addresses */ 112 /** Peripheral SPI_0 base address */ 113 #define IP_SPI_0_BASE (0x40130000u) 114 /** Peripheral SPI_0 base pointer */ 115 #define IP_SPI_0 ((SPI_Type *)IP_SPI_0_BASE) 116 /** Peripheral SPI_1 base address */ 117 #define IP_SPI_1_BASE (0x40140000u) 118 /** Peripheral SPI_1 base pointer */ 119 #define IP_SPI_1 ((SPI_Type *)IP_SPI_1_BASE) 120 /** Peripheral SPI_2 base address */ 121 #define IP_SPI_2_BASE (0x40930000u) 122 /** Peripheral SPI_2 base pointer */ 123 #define IP_SPI_2 ((SPI_Type *)IP_SPI_2_BASE) 124 /** Peripheral SPI_3 base address */ 125 #define IP_SPI_3_BASE (0x40940000u) 126 /** Peripheral SPI_3 base pointer */ 127 #define IP_SPI_3 ((SPI_Type *)IP_SPI_3_BASE) 128 /** Peripheral SPI_4 base address */ 129 #define IP_SPI_4_BASE (0x40950000u) 130 /** Peripheral SPI_4 base pointer */ 131 #define IP_SPI_4 ((SPI_Type *)IP_SPI_4_BASE) 132 /** Peripheral SPI_5 base address */ 133 #define IP_SPI_5_BASE (0x42130000u) 134 /** Peripheral SPI_5 base pointer */ 135 #define IP_SPI_5 ((SPI_Type *)IP_SPI_5_BASE) 136 /** Peripheral SPI_6 base address */ 137 #define IP_SPI_6_BASE (0x42140000u) 138 /** Peripheral SPI_6 base pointer */ 139 #define IP_SPI_6 ((SPI_Type *)IP_SPI_6_BASE) 140 /** Peripheral SPI_7 base address */ 141 #define IP_SPI_7_BASE (0x42150000u) 142 /** Peripheral SPI_7 base pointer */ 143 #define IP_SPI_7 ((SPI_Type *)IP_SPI_7_BASE) 144 /** Peripheral SPI_8 base address */ 145 #define IP_SPI_8_BASE (0x42930000u) 146 /** Peripheral SPI_8 base pointer */ 147 #define IP_SPI_8 ((SPI_Type *)IP_SPI_8_BASE) 148 /** Peripheral SPI_9 base address */ 149 #define IP_SPI_9_BASE (0x42940000u) 150 /** Peripheral SPI_9 base pointer */ 151 #define IP_SPI_9 ((SPI_Type *)IP_SPI_9_BASE) 152 /** Array initializer of SPI peripheral base addresses */ 153 #define IP_SPI_BASE_ADDRS { IP_SPI_0_BASE, IP_SPI_1_BASE, IP_SPI_2_BASE, IP_SPI_3_BASE, IP_SPI_4_BASE, IP_SPI_5_BASE, IP_SPI_6_BASE, IP_SPI_7_BASE, IP_SPI_8_BASE, IP_SPI_9_BASE } 154 /** Array initializer of SPI peripheral base pointers */ 155 #define IP_SPI_BASE_PTRS { IP_SPI_0, IP_SPI_1, IP_SPI_2, IP_SPI_3, IP_SPI_4, IP_SPI_5, IP_SPI_6, IP_SPI_7, IP_SPI_8, IP_SPI_9 } 156 157 /* ---------------------------------------------------------------------------- 158 -- SPI Register Masks 159 ---------------------------------------------------------------------------- */ 160 161 /*! 162 * @addtogroup SPI_Register_Masks SPI Register Masks 163 * @{ 164 */ 165 166 /*! @name MCR - Module Configuration Register */ 167 /*! @{ */ 168 169 #define SPI_MCR_HALT_MASK (0x1U) 170 #define SPI_MCR_HALT_SHIFT (0U) 171 #define SPI_MCR_HALT_WIDTH (1U) 172 #define SPI_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK) 173 174 #define SPI_MCR_PES_MASK (0x2U) 175 #define SPI_MCR_PES_SHIFT (1U) 176 #define SPI_MCR_PES_WIDTH (1U) 177 #define SPI_MCR_PES(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PES_SHIFT)) & SPI_MCR_PES_MASK) 178 179 #define SPI_MCR_FCPCS_MASK (0x4U) 180 #define SPI_MCR_FCPCS_SHIFT (2U) 181 #define SPI_MCR_FCPCS_WIDTH (1U) 182 #define SPI_MCR_FCPCS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FCPCS_SHIFT)) & SPI_MCR_FCPCS_MASK) 183 184 #define SPI_MCR_XSPI_MASK (0x8U) 185 #define SPI_MCR_XSPI_SHIFT (3U) 186 #define SPI_MCR_XSPI_WIDTH (1U) 187 #define SPI_MCR_XSPI(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_XSPI_SHIFT)) & SPI_MCR_XSPI_MASK) 188 189 #define SPI_MCR_SMPL_PT_MASK (0x300U) 190 #define SPI_MCR_SMPL_PT_SHIFT (8U) 191 #define SPI_MCR_SMPL_PT_WIDTH (2U) 192 #define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK) 193 194 #define SPI_MCR_CLR_RXF_MASK (0x400U) 195 #define SPI_MCR_CLR_RXF_SHIFT (10U) 196 #define SPI_MCR_CLR_RXF_WIDTH (1U) 197 #define SPI_MCR_CLR_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK) 198 199 #define SPI_MCR_CLR_TXF_MASK (0x800U) 200 #define SPI_MCR_CLR_TXF_SHIFT (11U) 201 #define SPI_MCR_CLR_TXF_WIDTH (1U) 202 #define SPI_MCR_CLR_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK) 203 204 #define SPI_MCR_DIS_RXF_MASK (0x1000U) 205 #define SPI_MCR_DIS_RXF_SHIFT (12U) 206 #define SPI_MCR_DIS_RXF_WIDTH (1U) 207 #define SPI_MCR_DIS_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK) 208 209 #define SPI_MCR_DIS_TXF_MASK (0x2000U) 210 #define SPI_MCR_DIS_TXF_SHIFT (13U) 211 #define SPI_MCR_DIS_TXF_WIDTH (1U) 212 #define SPI_MCR_DIS_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK) 213 214 #define SPI_MCR_MDIS_MASK (0x4000U) 215 #define SPI_MCR_MDIS_SHIFT (14U) 216 #define SPI_MCR_MDIS_WIDTH (1U) 217 #define SPI_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK) 218 219 #define SPI_MCR_PCSIS_MASK (0x1F0000U) 220 #define SPI_MCR_PCSIS_SHIFT (16U) 221 #define SPI_MCR_PCSIS_WIDTH (5U) 222 #define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK) 223 224 #define SPI_MCR_ROOE_MASK (0x1000000U) 225 #define SPI_MCR_ROOE_SHIFT (24U) 226 #define SPI_MCR_ROOE_WIDTH (1U) 227 #define SPI_MCR_ROOE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK) 228 229 #define SPI_MCR_MTFE_MASK (0x4000000U) 230 #define SPI_MCR_MTFE_SHIFT (26U) 231 #define SPI_MCR_MTFE_WIDTH (1U) 232 #define SPI_MCR_MTFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK) 233 234 #define SPI_MCR_FRZ_MASK (0x8000000U) 235 #define SPI_MCR_FRZ_SHIFT (27U) 236 #define SPI_MCR_FRZ_WIDTH (1U) 237 #define SPI_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK) 238 239 #define SPI_MCR_DCONF_MASK (0x30000000U) 240 #define SPI_MCR_DCONF_SHIFT (28U) 241 #define SPI_MCR_DCONF_WIDTH (2U) 242 #define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK) 243 244 #define SPI_MCR_CONT_SCKE_MASK (0x40000000U) 245 #define SPI_MCR_CONT_SCKE_SHIFT (30U) 246 #define SPI_MCR_CONT_SCKE_WIDTH (1U) 247 #define SPI_MCR_CONT_SCKE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK) 248 249 #define SPI_MCR_MSTR_MASK (0x80000000U) 250 #define SPI_MCR_MSTR_SHIFT (31U) 251 #define SPI_MCR_MSTR_WIDTH (1U) 252 #define SPI_MCR_MSTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK) 253 /*! @} */ 254 255 /*! @name TCR - Transfer Count Register */ 256 /*! @{ */ 257 258 #define SPI_TCR_SPI_TCNT_MASK (0xFFFF0000U) 259 #define SPI_TCR_SPI_TCNT_SHIFT (16U) 260 #define SPI_TCR_SPI_TCNT_WIDTH (16U) 261 #define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_TCR_SPI_TCNT_SHIFT)) & SPI_TCR_SPI_TCNT_MASK) 262 /*! @} */ 263 264 /*! @name CTAR - Clock and Transfer Attributes Register (in Master mode) */ 265 /*! @{ */ 266 267 #define SPI_CTAR_BR_MASK (0xFU) 268 #define SPI_CTAR_BR_SHIFT (0U) 269 #define SPI_CTAR_BR_WIDTH (4U) 270 #define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_BR_SHIFT)) & SPI_CTAR_BR_MASK) 271 272 #define SPI_CTAR_DT_MASK (0xF0U) 273 #define SPI_CTAR_DT_SHIFT (4U) 274 #define SPI_CTAR_DT_WIDTH (4U) 275 #define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DT_SHIFT)) & SPI_CTAR_DT_MASK) 276 277 #define SPI_CTAR_ASC_MASK (0xF00U) 278 #define SPI_CTAR_ASC_SHIFT (8U) 279 #define SPI_CTAR_ASC_WIDTH (4U) 280 #define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_ASC_SHIFT)) & SPI_CTAR_ASC_MASK) 281 282 #define SPI_CTAR_CSSCK_MASK (0xF000U) 283 #define SPI_CTAR_CSSCK_SHIFT (12U) 284 #define SPI_CTAR_CSSCK_WIDTH (4U) 285 #define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CSSCK_SHIFT)) & SPI_CTAR_CSSCK_MASK) 286 287 #define SPI_CTAR_PBR_MASK (0x30000U) 288 #define SPI_CTAR_PBR_SHIFT (16U) 289 #define SPI_CTAR_PBR_WIDTH (2U) 290 #define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PBR_SHIFT)) & SPI_CTAR_PBR_MASK) 291 292 #define SPI_CTAR_PDT_MASK (0xC0000U) 293 #define SPI_CTAR_PDT_SHIFT (18U) 294 #define SPI_CTAR_PDT_WIDTH (2U) 295 #define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PDT_SHIFT)) & SPI_CTAR_PDT_MASK) 296 297 #define SPI_CTAR_PASC_MASK (0x300000U) 298 #define SPI_CTAR_PASC_SHIFT (20U) 299 #define SPI_CTAR_PASC_WIDTH (2U) 300 #define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PASC_SHIFT)) & SPI_CTAR_PASC_MASK) 301 302 #define SPI_CTAR_PCSSCK_MASK (0xC00000U) 303 #define SPI_CTAR_PCSSCK_SHIFT (22U) 304 #define SPI_CTAR_PCSSCK_WIDTH (2U) 305 #define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK) 306 307 #define SPI_CTAR_LSBFE_MASK (0x1000000U) 308 #define SPI_CTAR_LSBFE_SHIFT (24U) 309 #define SPI_CTAR_LSBFE_WIDTH (1U) 310 #define SPI_CTAR_LSBFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_LSBFE_SHIFT)) & SPI_CTAR_LSBFE_MASK) 311 312 #define SPI_CTAR_CPHA_MASK (0x2000000U) 313 #define SPI_CTAR_CPHA_SHIFT (25U) 314 #define SPI_CTAR_CPHA_WIDTH (1U) 315 #define SPI_CTAR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPHA_SHIFT)) & SPI_CTAR_CPHA_MASK) 316 317 #define SPI_CTAR_CPOL_MASK (0x4000000U) 318 #define SPI_CTAR_CPOL_SHIFT (26U) 319 #define SPI_CTAR_CPOL_WIDTH (1U) 320 #define SPI_CTAR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPOL_SHIFT)) & SPI_CTAR_CPOL_MASK) 321 322 #define SPI_CTAR_FMSZ_MASK (0x78000000U) 323 #define SPI_CTAR_FMSZ_SHIFT (27U) 324 #define SPI_CTAR_FMSZ_WIDTH (4U) 325 #define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_FMSZ_SHIFT)) & SPI_CTAR_FMSZ_MASK) 326 327 #define SPI_CTAR_DBR_MASK (0x80000000U) 328 #define SPI_CTAR_DBR_SHIFT (31U) 329 #define SPI_CTAR_DBR_WIDTH (1U) 330 #define SPI_CTAR_DBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DBR_SHIFT)) & SPI_CTAR_DBR_MASK) 331 /*! @} */ 332 333 /*! @name CTAR_SLAVE - Clock and Transfer Attributes Register (in Slave mode) */ 334 /*! @{ */ 335 336 #define SPI_CTAR_SLAVE_PP_MASK (0x800000U) 337 #define SPI_CTAR_SLAVE_PP_SHIFT (23U) 338 #define SPI_CTAR_SLAVE_PP_WIDTH (1U) 339 #define SPI_CTAR_SLAVE_PP(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_PP_SHIFT)) & SPI_CTAR_SLAVE_PP_MASK) 340 341 #define SPI_CTAR_SLAVE_PE_MASK (0x1000000U) 342 #define SPI_CTAR_SLAVE_PE_SHIFT (24U) 343 #define SPI_CTAR_SLAVE_PE_WIDTH (1U) 344 #define SPI_CTAR_SLAVE_PE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_PE_SHIFT)) & SPI_CTAR_SLAVE_PE_MASK) 345 346 #define SPI_CTAR_SLAVE_CPHA_MASK (0x2000000U) 347 #define SPI_CTAR_SLAVE_CPHA_SHIFT (25U) 348 #define SPI_CTAR_SLAVE_CPHA_WIDTH (1U) 349 #define SPI_CTAR_SLAVE_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPHA_SHIFT)) & SPI_CTAR_SLAVE_CPHA_MASK) 350 351 #define SPI_CTAR_SLAVE_CPOL_MASK (0x4000000U) 352 #define SPI_CTAR_SLAVE_CPOL_SHIFT (26U) 353 #define SPI_CTAR_SLAVE_CPOL_WIDTH (1U) 354 #define SPI_CTAR_SLAVE_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPOL_SHIFT)) & SPI_CTAR_SLAVE_CPOL_MASK) 355 356 #define SPI_CTAR_SLAVE_FMSZ_MASK (0xF8000000U) 357 #define SPI_CTAR_SLAVE_FMSZ_SHIFT (27U) 358 #define SPI_CTAR_SLAVE_FMSZ_WIDTH (5U) 359 #define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_FMSZ_SHIFT)) & SPI_CTAR_SLAVE_FMSZ_MASK) 360 /*! @} */ 361 362 /*! @name SR - Status Register */ 363 /*! @{ */ 364 365 #define SPI_SR_POPNXTPTR_MASK (0xFU) 366 #define SPI_SR_POPNXTPTR_SHIFT (0U) 367 #define SPI_SR_POPNXTPTR_WIDTH (4U) 368 #define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_POPNXTPTR_SHIFT)) & SPI_SR_POPNXTPTR_MASK) 369 370 #define SPI_SR_RXCTR_MASK (0xF0U) 371 #define SPI_SR_RXCTR_SHIFT (4U) 372 #define SPI_SR_RXCTR_WIDTH (4U) 373 #define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RXCTR_SHIFT)) & SPI_SR_RXCTR_MASK) 374 375 #define SPI_SR_TXNXTPTR_MASK (0xF00U) 376 #define SPI_SR_TXNXTPTR_SHIFT (8U) 377 #define SPI_SR_TXNXTPTR_WIDTH (4U) 378 #define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXNXTPTR_SHIFT)) & SPI_SR_TXNXTPTR_MASK) 379 380 #define SPI_SR_TXCTR_MASK (0xF000U) 381 #define SPI_SR_TXCTR_SHIFT (12U) 382 #define SPI_SR_TXCTR_WIDTH (4U) 383 #define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXCTR_SHIFT)) & SPI_SR_TXCTR_MASK) 384 385 #define SPI_SR_CMDFFF_MASK (0x10000U) 386 #define SPI_SR_CMDFFF_SHIFT (16U) 387 #define SPI_SR_CMDFFF_WIDTH (1U) 388 #define SPI_SR_CMDFFF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_CMDFFF_SHIFT)) & SPI_SR_CMDFFF_MASK) 389 390 #define SPI_SR_RFDF_MASK (0x20000U) 391 #define SPI_SR_RFDF_SHIFT (17U) 392 #define SPI_SR_RFDF_WIDTH (1U) 393 #define SPI_SR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFDF_SHIFT)) & SPI_SR_RFDF_MASK) 394 395 #define SPI_SR_TFIWF_MASK (0x40000U) 396 #define SPI_SR_TFIWF_SHIFT (18U) 397 #define SPI_SR_TFIWF_WIDTH (1U) 398 #define SPI_SR_TFIWF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFIWF_SHIFT)) & SPI_SR_TFIWF_MASK) 399 400 #define SPI_SR_RFOF_MASK (0x80000U) 401 #define SPI_SR_RFOF_SHIFT (19U) 402 #define SPI_SR_RFOF_WIDTH (1U) 403 #define SPI_SR_RFOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFOF_SHIFT)) & SPI_SR_RFOF_MASK) 404 405 #define SPI_SR_SPEF_MASK (0x200000U) 406 #define SPI_SR_SPEF_SHIFT (21U) 407 #define SPI_SR_SPEF_WIDTH (1U) 408 #define SPI_SR_SPEF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_SPEF_SHIFT)) & SPI_SR_SPEF_MASK) 409 410 #define SPI_SR_CMDTCF_MASK (0x800000U) 411 #define SPI_SR_CMDTCF_SHIFT (23U) 412 #define SPI_SR_CMDTCF_WIDTH (1U) 413 #define SPI_SR_CMDTCF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_CMDTCF_SHIFT)) & SPI_SR_CMDTCF_MASK) 414 415 #define SPI_SR_BSYF_MASK (0x1000000U) 416 #define SPI_SR_BSYF_SHIFT (24U) 417 #define SPI_SR_BSYF_WIDTH (1U) 418 #define SPI_SR_BSYF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_BSYF_SHIFT)) & SPI_SR_BSYF_MASK) 419 420 #define SPI_SR_TFFF_MASK (0x2000000U) 421 #define SPI_SR_TFFF_SHIFT (25U) 422 #define SPI_SR_TFFF_WIDTH (1U) 423 #define SPI_SR_TFFF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK) 424 425 #define SPI_SR_TFUF_MASK (0x8000000U) 426 #define SPI_SR_TFUF_SHIFT (27U) 427 #define SPI_SR_TFUF_WIDTH (1U) 428 #define SPI_SR_TFUF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFUF_SHIFT)) & SPI_SR_TFUF_MASK) 429 430 #define SPI_SR_EOQF_MASK (0x10000000U) 431 #define SPI_SR_EOQF_SHIFT (28U) 432 #define SPI_SR_EOQF_WIDTH (1U) 433 #define SPI_SR_EOQF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_EOQF_SHIFT)) & SPI_SR_EOQF_MASK) 434 435 #define SPI_SR_TXRXS_MASK (0x40000000U) 436 #define SPI_SR_TXRXS_SHIFT (30U) 437 #define SPI_SR_TXRXS_WIDTH (1U) 438 #define SPI_SR_TXRXS(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXRXS_SHIFT)) & SPI_SR_TXRXS_MASK) 439 440 #define SPI_SR_TCF_MASK (0x80000000U) 441 #define SPI_SR_TCF_SHIFT (31U) 442 #define SPI_SR_TCF_WIDTH (1U) 443 #define SPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TCF_SHIFT)) & SPI_SR_TCF_MASK) 444 /*! @} */ 445 446 /*! @name RSER - DMA/Interrupt Request Select and Enable Register */ 447 /*! @{ */ 448 449 #define SPI_RSER_CMDFFF_DIRS_MASK (0x8000U) 450 #define SPI_RSER_CMDFFF_DIRS_SHIFT (15U) 451 #define SPI_RSER_CMDFFF_DIRS_WIDTH (1U) 452 #define SPI_RSER_CMDFFF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_CMDFFF_DIRS_SHIFT)) & SPI_RSER_CMDFFF_DIRS_MASK) 453 454 #define SPI_RSER_RFDF_DIRS_MASK (0x10000U) 455 #define SPI_RSER_RFDF_DIRS_SHIFT (16U) 456 #define SPI_RSER_RFDF_DIRS_WIDTH (1U) 457 #define SPI_RSER_RFDF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_DIRS_SHIFT)) & SPI_RSER_RFDF_DIRS_MASK) 458 459 #define SPI_RSER_RFDF_RE_MASK (0x20000U) 460 #define SPI_RSER_RFDF_RE_SHIFT (17U) 461 #define SPI_RSER_RFDF_RE_WIDTH (1U) 462 #define SPI_RSER_RFDF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_RE_SHIFT)) & SPI_RSER_RFDF_RE_MASK) 463 464 #define SPI_RSER_TFIWF_RE_MASK (0x40000U) 465 #define SPI_RSER_TFIWF_RE_SHIFT (18U) 466 #define SPI_RSER_TFIWF_RE_WIDTH (1U) 467 #define SPI_RSER_TFIWF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFIWF_RE_SHIFT)) & SPI_RSER_TFIWF_RE_MASK) 468 469 #define SPI_RSER_RFOF_RE_MASK (0x80000U) 470 #define SPI_RSER_RFOF_RE_SHIFT (19U) 471 #define SPI_RSER_RFOF_RE_WIDTH (1U) 472 #define SPI_RSER_RFOF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFOF_RE_SHIFT)) & SPI_RSER_RFOF_RE_MASK) 473 474 #define SPI_RSER_SPEF_RE_MASK (0x200000U) 475 #define SPI_RSER_SPEF_RE_SHIFT (21U) 476 #define SPI_RSER_SPEF_RE_WIDTH (1U) 477 #define SPI_RSER_SPEF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_SPEF_RE_SHIFT)) & SPI_RSER_SPEF_RE_MASK) 478 479 #define SPI_RSER_CMDTCF_RE_MASK (0x800000U) 480 #define SPI_RSER_CMDTCF_RE_SHIFT (23U) 481 #define SPI_RSER_CMDTCF_RE_WIDTH (1U) 482 #define SPI_RSER_CMDTCF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_CMDTCF_RE_SHIFT)) & SPI_RSER_CMDTCF_RE_MASK) 483 484 #define SPI_RSER_TFFF_DIRS_MASK (0x1000000U) 485 #define SPI_RSER_TFFF_DIRS_SHIFT (24U) 486 #define SPI_RSER_TFFF_DIRS_WIDTH (1U) 487 #define SPI_RSER_TFFF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_DIRS_SHIFT)) & SPI_RSER_TFFF_DIRS_MASK) 488 489 #define SPI_RSER_TFFF_RE_MASK (0x2000000U) 490 #define SPI_RSER_TFFF_RE_SHIFT (25U) 491 #define SPI_RSER_TFFF_RE_WIDTH (1U) 492 #define SPI_RSER_TFFF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK) 493 494 #define SPI_RSER_TFUF_RE_MASK (0x8000000U) 495 #define SPI_RSER_TFUF_RE_SHIFT (27U) 496 #define SPI_RSER_TFUF_RE_WIDTH (1U) 497 #define SPI_RSER_TFUF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFUF_RE_SHIFT)) & SPI_RSER_TFUF_RE_MASK) 498 499 #define SPI_RSER_EOQF_RE_MASK (0x10000000U) 500 #define SPI_RSER_EOQF_RE_SHIFT (28U) 501 #define SPI_RSER_EOQF_RE_WIDTH (1U) 502 #define SPI_RSER_EOQF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_EOQF_RE_SHIFT)) & SPI_RSER_EOQF_RE_MASK) 503 504 #define SPI_RSER_CMDFFF_RE_MASK (0x40000000U) 505 #define SPI_RSER_CMDFFF_RE_SHIFT (30U) 506 #define SPI_RSER_CMDFFF_RE_WIDTH (1U) 507 #define SPI_RSER_CMDFFF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_CMDFFF_RE_SHIFT)) & SPI_RSER_CMDFFF_RE_MASK) 508 509 #define SPI_RSER_TCF_RE_MASK (0x80000000U) 510 #define SPI_RSER_TCF_RE_SHIFT (31U) 511 #define SPI_RSER_TCF_RE_WIDTH (1U) 512 #define SPI_RSER_TCF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TCF_RE_SHIFT)) & SPI_RSER_TCF_RE_MASK) 513 /*! @} */ 514 515 /*! @name TX - SPI_TX register */ 516 /*! @{ */ 517 518 #define SPI_TX_TX_MASK (0xFFFFU) 519 #define SPI_TX_TX_SHIFT (0U) 520 #define SPI_TX_TX_WIDTH (16U) 521 #define SPI_TX_TX(x) (((uint16_t)(((uint16_t)(x)) << SPI_TX_TX_SHIFT)) & SPI_TX_TX_MASK) 522 /*! @} */ 523 524 /*! @name CMD - SPI_CMD register */ 525 /*! @{ */ 526 527 #define SPI_CMD_CMD_MASK (0xFFFFU) 528 #define SPI_CMD_CMD_SHIFT (0U) 529 #define SPI_CMD_CMD_WIDTH (16U) 530 #define SPI_CMD_CMD(x) (((uint16_t)(((uint16_t)(x)) << SPI_CMD_CMD_SHIFT)) & SPI_CMD_CMD_MASK) 531 /*! @} */ 532 533 /*! @name PUSHR - PUSH TX FIFO Register In Master Mode */ 534 /*! @{ */ 535 536 #define SPI_PUSHR_TXDATA_MASK (0xFFFFU) 537 #define SPI_PUSHR_TXDATA_SHIFT (0U) 538 #define SPI_PUSHR_TXDATA_WIDTH (16U) 539 #define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_TXDATA_SHIFT)) & SPI_PUSHR_TXDATA_MASK) 540 541 #define SPI_PUSHR_PCS_MASK (0x1F0000U) 542 #define SPI_PUSHR_PCS_SHIFT (16U) 543 #define SPI_PUSHR_PCS_WIDTH (5U) 544 #define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_PCS_SHIFT)) & SPI_PUSHR_PCS_MASK) 545 546 #define SPI_PUSHR_PP_MCSC_MASK (0x1000000U) 547 #define SPI_PUSHR_PP_MCSC_SHIFT (24U) 548 #define SPI_PUSHR_PP_MCSC_WIDTH (1U) 549 #define SPI_PUSHR_PP_MCSC(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_PP_MCSC_SHIFT)) & SPI_PUSHR_PP_MCSC_MASK) 550 551 #define SPI_PUSHR_PE_MASC_MASK (0x2000000U) 552 #define SPI_PUSHR_PE_MASC_SHIFT (25U) 553 #define SPI_PUSHR_PE_MASC_WIDTH (1U) 554 #define SPI_PUSHR_PE_MASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_PE_MASC_SHIFT)) & SPI_PUSHR_PE_MASC_MASK) 555 556 #define SPI_PUSHR_CTCNT_MASK (0x4000000U) 557 #define SPI_PUSHR_CTCNT_SHIFT (26U) 558 #define SPI_PUSHR_CTCNT_WIDTH (1U) 559 #define SPI_PUSHR_CTCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTCNT_SHIFT)) & SPI_PUSHR_CTCNT_MASK) 560 561 #define SPI_PUSHR_EOQ_MASK (0x8000000U) 562 #define SPI_PUSHR_EOQ_SHIFT (27U) 563 #define SPI_PUSHR_EOQ_WIDTH (1U) 564 #define SPI_PUSHR_EOQ(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_EOQ_SHIFT)) & SPI_PUSHR_EOQ_MASK) 565 566 #define SPI_PUSHR_CTAS_MASK (0x70000000U) 567 #define SPI_PUSHR_CTAS_SHIFT (28U) 568 #define SPI_PUSHR_CTAS_WIDTH (3U) 569 #define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTAS_SHIFT)) & SPI_PUSHR_CTAS_MASK) 570 571 #define SPI_PUSHR_CONT_MASK (0x80000000U) 572 #define SPI_PUSHR_CONT_SHIFT (31U) 573 #define SPI_PUSHR_CONT_WIDTH (1U) 574 #define SPI_PUSHR_CONT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CONT_SHIFT)) & SPI_PUSHR_CONT_MASK) 575 /*! @} */ 576 577 /*! @name PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode */ 578 /*! @{ */ 579 580 #define SPI_PUSHR_SLAVE_TXDATA_MASK (0xFFFFU) 581 #define SPI_PUSHR_SLAVE_TXDATA_SHIFT (0U) 582 #define SPI_PUSHR_SLAVE_TXDATA_WIDTH (16U) 583 #define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_SLAVE_TXDATA_SHIFT)) & SPI_PUSHR_SLAVE_TXDATA_MASK) 584 /*! @} */ 585 586 /*! @name POPR - POP RX FIFO Register */ 587 /*! @{ */ 588 589 #define SPI_POPR_RXDATA_MASK (0xFFFFFFFFU) 590 #define SPI_POPR_RXDATA_SHIFT (0U) 591 #define SPI_POPR_RXDATA_WIDTH (32U) 592 #define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_POPR_RXDATA_SHIFT)) & SPI_POPR_RXDATA_MASK) 593 /*! @} */ 594 595 /*! @name TXFR - Transmit FIFO Registers */ 596 /*! @{ */ 597 598 #define SPI_TXFR_TXDATA_MASK (0xFFFFU) 599 #define SPI_TXFR_TXDATA_SHIFT (0U) 600 #define SPI_TXFR_TXDATA_WIDTH (16U) 601 #define SPI_TXFR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR_TXDATA_SHIFT)) & SPI_TXFR_TXDATA_MASK) 602 603 #define SPI_TXFR_TXCMD_TXDATA_MASK (0xFFFF0000U) 604 #define SPI_TXFR_TXCMD_TXDATA_SHIFT (16U) 605 #define SPI_TXFR_TXCMD_TXDATA_WIDTH (16U) 606 #define SPI_TXFR_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR_TXCMD_TXDATA_SHIFT)) & SPI_TXFR_TXCMD_TXDATA_MASK) 607 /*! @} */ 608 609 /*! @name RXFR - Receive FIFO Registers */ 610 /*! @{ */ 611 612 #define SPI_RXFR_RXDATA_MASK (0xFFFFFFFFU) 613 #define SPI_RXFR_RXDATA_SHIFT (0U) 614 #define SPI_RXFR_RXDATA_WIDTH (32U) 615 #define SPI_RXFR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR_RXDATA_SHIFT)) & SPI_RXFR_RXDATA_MASK) 616 /*! @} */ 617 618 /*! @name CTARE - Clock and Transfer Attributes Register Extended */ 619 /*! @{ */ 620 621 #define SPI_CTARE_DTCP_MASK (0x7FFU) 622 #define SPI_CTARE_DTCP_SHIFT (0U) 623 #define SPI_CTARE_DTCP_WIDTH (11U) 624 #define SPI_CTARE_DTCP(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTARE_DTCP_SHIFT)) & SPI_CTARE_DTCP_MASK) 625 626 #define SPI_CTARE_FMSZE_MASK (0x10000U) 627 #define SPI_CTARE_FMSZE_SHIFT (16U) 628 #define SPI_CTARE_FMSZE_WIDTH (1U) 629 #define SPI_CTARE_FMSZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTARE_FMSZE_SHIFT)) & SPI_CTARE_FMSZE_MASK) 630 /*! @} */ 631 632 /*! @name SREX - Status Register Extended */ 633 /*! @{ */ 634 635 #define SPI_SREX_CMDNXTPTR_MASK (0xFU) 636 #define SPI_SREX_CMDNXTPTR_SHIFT (0U) 637 #define SPI_SREX_CMDNXTPTR_WIDTH (4U) 638 #define SPI_SREX_CMDNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SREX_CMDNXTPTR_SHIFT)) & SPI_SREX_CMDNXTPTR_MASK) 639 640 #define SPI_SREX_CMDCTR_MASK (0x1F0U) 641 #define SPI_SREX_CMDCTR_SHIFT (4U) 642 #define SPI_SREX_CMDCTR_WIDTH (5U) 643 #define SPI_SREX_CMDCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SREX_CMDCTR_SHIFT)) & SPI_SREX_CMDCTR_MASK) 644 645 #define SPI_SREX_RXCTR4_MASK (0x800U) 646 #define SPI_SREX_RXCTR4_SHIFT (11U) 647 #define SPI_SREX_RXCTR4_WIDTH (1U) 648 #define SPI_SREX_RXCTR4(x) (((uint32_t)(((uint32_t)(x)) << SPI_SREX_RXCTR4_SHIFT)) & SPI_SREX_RXCTR4_MASK) 649 650 #define SPI_SREX_TXCTR4_MASK (0x4000U) 651 #define SPI_SREX_TXCTR4_SHIFT (14U) 652 #define SPI_SREX_TXCTR4_WIDTH (1U) 653 #define SPI_SREX_TXCTR4(x) (((uint32_t)(((uint32_t)(x)) << SPI_SREX_TXCTR4_SHIFT)) & SPI_SREX_TXCTR4_MASK) 654 /*! @} */ 655 656 /*! 657 * @} 658 */ /* end of group SPI_Register_Masks */ 659 660 /*! 661 * @} 662 */ /* end of group SPI_Peripheral_Access_Layer */ 663 664 #endif /* #if !defined(S32Z2_SPI_H_) */ 665
