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Searched refs:SPI_CFG_SPOL2_MASK (Results 1 – 25 of 58) sorted by relevance

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/hal_nxp-3.6.0/mcux/mcux-sdk/drivers/lpc_minispi/
Dfsl_spi.h117 kSPI_Spol2ActiveHigh = SPI_CFG_SPOL2_MASK,
127 | SPI_CFG_SPOL2_MASK
/hal_nxp-3.6.0/mcux/mcux-sdk/drivers/flexcomm/spi/
Dfsl_spi.c34 #define SPI_SSELPOL_MASK ((SPI_CFG_SPOL0_MASK) | (SPI_CFG_SPOL1_MASK) | (SPI_CFG_SPOL2_MASK))
39 #define SPI_SSELPOL_MASK ((SPI_CFG_SPOL0_MASK) | (SPI_CFG_SPOL1_MASK) | (SPI_CFG_SPOL2_MASK) | (SPI…
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC832/
DLPC832.h5270 #define SPI_CFG_SPOL2_MASK (0x400U) macro
5276 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC822/
DLPC822.h5426 #define SPI_CFG_SPOL2_MASK (0x400U) macro
5432 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC824/
DLPC824.h5426 #define SPI_CFG_SPOL2_MASK (0x400U) macro
5432 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC834/
DLPC834.h5270 #define SPI_CFG_SPOL2_MASK (0x400U) macro
5276 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC844/
DLPC844.h5926 #define SPI_CFG_SPOL2_MASK (0x400U) macro
5932 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC845/
DLPC845.h6450 #define SPI_CFG_SPOL2_MASK (0x400U) macro
6456 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC51U68/
DLPC51U68.h7050 #define SPI_CFG_SPOL2_MASK (0x400U) macro
7056 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54114/
DLPC54114_cm4.h7362 #define SPI_CFG_SPOL2_MASK (0x400U) macro
7368 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK)
DLPC54114_cm0plus.h7351 #define SPI_CFG_SPOL2_MASK (0x400U) macro
7357 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54113/
DLPC54113.h7363 #define SPI_CFG_SPOL2_MASK (0x400U) macro
7369 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54607/
DLPC54607.h11447 #define SPI_CFG_SPOL2_MASK (0x400U) macro
11453 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54S005/
DLPC54S005.h11465 #define SPI_CFG_SPOL2_MASK (0x400U) macro
11471 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54005/
DLPC54005.h10673 #define SPI_CFG_SPOL2_MASK (0x400U) macro
10679 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54605/
DLPC54605.h10803 #define SPI_CFG_SPOL2_MASK (0x400U) macro
10809 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54616/
DLPC54616.h15026 #define SPI_CFG_SPOL2_MASK (0x400U) macro
15032 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54016/
DLPC54016.h14054 #define SPI_CFG_SPOL2_MASK (0x400U) macro
14060 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54606/
DLPC54606.h14951 #define SPI_CFG_SPOL2_MASK (0x400U) macro
14957 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC5506/
DLPC5506.h19677 #define SPI_CFG_SPOL2_MASK (0x400U) macro
19683 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC5502CPXXXX/
DLPC5502CPXXXX.h19560 #define SPI_CFG_SPOL2_MASK (0x400U) macro
19566 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC5504/
DLPC5504.h19677 #define SPI_CFG_SPOL2_MASK (0x400U) macro
19683 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC5504CPXXXX/
DLPC5504CPXXXX.h19560 #define SPI_CFG_SPOL2_MASK (0x400U) macro
19566 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54628/
DLPC54628.h15872 #define SPI_CFG_SPOL2_MASK (0x400U) macro
15878 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC5506CPXXXX/
DLPC5506CPXXXX.h19560 #define SPI_CFG_SPOL2_MASK (0x400U) macro
19566 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK)

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