1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2023 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_SMU_MRU.h 10 * @version 2.1 11 * @date 2023-07-20 12 * @brief Peripheral Access Layer for S32Z2_SMU_MRU 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_SMU_MRU_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_SMU_MRU_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- SMU_MRU Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup SMU_MRU_Peripheral_Access_Layer SMU_MRU Peripheral Access Layer 68 * @{ 69 */ 70 71 /** SMU_MRU - Size of Registers Arrays */ 72 #define SMU_MRU_CHXCONFIG_COUNT 12u 73 #define SMU_MRU_NOTIFY_COUNT 2u 74 75 /** SMU_MRU - Register Layout Typedef */ 76 typedef struct { 77 struct { /* offset: 0x0, array step: 0x10 */ 78 __IO uint32_t CH_CFG0; /**< Channel (x) Configuration 0, array offset: 0x0, array step: 0x10 */ 79 __IO uint32_t CH_CFG1; /**< Channel (x) Configuration 1, array offset: 0x4, array step: 0x10 */ 80 __IO uint32_t CH_MBSTAT; /**< Channel (x) Mailbox Status, array offset: 0x8, array step: 0x10 */ 81 uint8_t RESERVED_0[4]; 82 } CHXCONFIG[SMU_MRU_CHXCONFIG_COUNT]; 83 uint8_t RESERVED_0[320]; 84 __I uint32_t NOTIFY[SMU_MRU_NOTIFY_COUNT]; /**< Notification 0 Status..Notification 1 Status, array offset: 0x200, array step: 0x4 */ 85 uint8_t RESERVED_1[65016]; 86 __IO uint32_t CH1_MB0; /**< Channel (x) Mailbox (n), offset: 0x10000 */ 87 __IO uint32_t CH1_MB1; /**< Channel (x) Mailbox (n), offset: 0x10004 */ 88 __IO uint32_t CH1_MB2; /**< Channel (x) Mailbox (n), offset: 0x10008 */ 89 __IO uint32_t CH1_MB3; /**< Channel (x) Mailbox (n), offset: 0x1000C */ 90 uint8_t RESERVED_2[65520]; 91 __IO uint32_t CH2_MB0; /**< Channel (x) Mailbox (n), offset: 0x20000 */ 92 __IO uint32_t CH2_MB1; /**< Channel (x) Mailbox (n), offset: 0x20004 */ 93 __IO uint32_t CH2_MB2; /**< Channel (x) Mailbox (n), offset: 0x20008 */ 94 __IO uint32_t CH2_MB3; /**< Channel (x) Mailbox (n), offset: 0x2000C */ 95 uint8_t RESERVED_3[65520]; 96 __IO uint32_t CH3_MB0; /**< Channel (x) Mailbox (n), offset: 0x30000 */ 97 __IO uint32_t CH3_MB1; /**< Channel (x) Mailbox (n), offset: 0x30004 */ 98 __IO uint32_t CH3_MB2; /**< Channel (x) Mailbox (n), offset: 0x30008 */ 99 __IO uint32_t CH3_MB3; /**< Channel (x) Mailbox (n), offset: 0x3000C */ 100 uint8_t RESERVED_4[65520]; 101 __IO uint32_t CH4_MB0; /**< Channel (x) Mailbox (n), offset: 0x40000 */ 102 __IO uint32_t CH4_MB1; /**< Channel (x) Mailbox (n), offset: 0x40004 */ 103 __IO uint32_t CH4_MB2; /**< Channel (x) Mailbox (n), offset: 0x40008 */ 104 __IO uint32_t CH4_MB3; /**< Channel (x) Mailbox (n), offset: 0x4000C */ 105 uint8_t RESERVED_5[65520]; 106 __IO uint32_t CH5_MB0; /**< Channel (x) Mailbox (n), offset: 0x50000 */ 107 __IO uint32_t CH5_MB1; /**< Channel (x) Mailbox (n), offset: 0x50004 */ 108 uint8_t RESERVED_6[65528]; 109 __IO uint32_t CH6_MB0; /**< Channel (x) Mailbox (n), offset: 0x60000 */ 110 __IO uint32_t CH6_MB1; /**< Channel (x) Mailbox (n), offset: 0x60004 */ 111 uint8_t RESERVED_7[65528]; 112 __IO uint32_t CH7_MB0; /**< Channel (x) Mailbox (n), offset: 0x70000 */ 113 __IO uint32_t CH7_MB1; /**< Channel (x) Mailbox (n), offset: 0x70004 */ 114 uint8_t RESERVED_8[65528]; 115 __IO uint32_t CH8_MB0; /**< Channel (x) Mailbox (n), offset: 0x80000 */ 116 __IO uint32_t CH8_MB1; /**< Channel (x) Mailbox (n), offset: 0x80004 */ 117 uint8_t RESERVED_9[65528]; 118 __IO uint32_t CH9_MB0; /**< Channel (x) Mailbox (n), offset: 0x90000 */ 119 __IO uint32_t CH9_MB1; /**< Channel (x) Mailbox (n), offset: 0x90004 */ 120 uint8_t RESERVED_10[65528]; 121 __IO uint32_t CH10_MB0; /**< Channel (x) Mailbox (n), offset: 0xA0000 */ 122 __IO uint32_t CH10_MB1; /**< Channel (x) Mailbox (n), offset: 0xA0004 */ 123 uint8_t RESERVED_11[65528]; 124 __IO uint32_t CH11_MB0; /**< Channel (x) Mailbox (n), offset: 0xB0000 */ 125 __IO uint32_t CH11_MB1; /**< Channel (x) Mailbox (n), offset: 0xB0004 */ 126 uint8_t RESERVED_12[65528]; 127 __IO uint32_t CH12_MB0; /**< Channel (x) Mailbox (n), offset: 0xC0000 */ 128 __IO uint32_t CH12_MB1; /**< Channel (x) Mailbox (n), offset: 0xC0004 */ 129 } SMU_MRU_Type, *SMU_MRU_MemMapPtr; 130 131 /** Number of instances of the SMU_MRU module. */ 132 #define SMU_MRU_INSTANCE_COUNT (1u) 133 134 /* SMU_MRU - Peripheral instance base addresses */ 135 /** Peripheral SMU__MRU base address */ 136 #define IP_SMU__MRU_BASE (0x45300000u) 137 /** Peripheral SMU__MRU base pointer */ 138 #define IP_SMU__MRU ((SMU_MRU_Type *)IP_SMU__MRU_BASE) 139 /** Array initializer of SMU_MRU peripheral base addresses */ 140 #define IP_SMU_MRU_BASE_ADDRS { IP_SMU__MRU_BASE } 141 /** Array initializer of SMU_MRU peripheral base pointers */ 142 #define IP_SMU_MRU_BASE_PTRS { IP_SMU__MRU } 143 144 /* ---------------------------------------------------------------------------- 145 -- SMU_MRU Register Masks 146 ---------------------------------------------------------------------------- */ 147 148 /*! 149 * @addtogroup SMU_MRU_Register_Masks SMU_MRU Register Masks 150 * @{ 151 */ 152 153 /*! @name CH_CFG0 - Channel (x) Configuration 0 */ 154 /*! @{ */ 155 156 #define SMU_MRU_CH_CFG0_CHE_MASK (0x1U) 157 #define SMU_MRU_CH_CFG0_CHE_SHIFT (0U) 158 #define SMU_MRU_CH_CFG0_CHE_WIDTH (1U) 159 #define SMU_MRU_CH_CFG0_CHE(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_CH_CFG0_CHE_SHIFT)) & SMU_MRU_CH_CFG0_CHE_MASK) 160 161 #define SMU_MRU_CH_CFG0_CHR_MASK (0x2U) 162 #define SMU_MRU_CH_CFG0_CHR_SHIFT (1U) 163 #define SMU_MRU_CH_CFG0_CHR_WIDTH (1U) 164 #define SMU_MRU_CH_CFG0_CHR(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_CH_CFG0_CHR_SHIFT)) & SMU_MRU_CH_CFG0_CHR_MASK) 165 166 #define SMU_MRU_CH_CFG0_IE_MASK (0x4U) 167 #define SMU_MRU_CH_CFG0_IE_SHIFT (2U) 168 #define SMU_MRU_CH_CFG0_IE_WIDTH (1U) 169 #define SMU_MRU_CH_CFG0_IE(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_CH_CFG0_IE_SHIFT)) & SMU_MRU_CH_CFG0_IE_MASK) 170 171 #define SMU_MRU_CH_CFG0_MBE0_MASK (0x10000U) 172 #define SMU_MRU_CH_CFG0_MBE0_SHIFT (16U) 173 #define SMU_MRU_CH_CFG0_MBE0_WIDTH (1U) 174 #define SMU_MRU_CH_CFG0_MBE0(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_CH_CFG0_MBE0_SHIFT)) & SMU_MRU_CH_CFG0_MBE0_MASK) 175 176 #define SMU_MRU_CH_CFG0_MBE1_MASK (0x20000U) 177 #define SMU_MRU_CH_CFG0_MBE1_SHIFT (17U) 178 #define SMU_MRU_CH_CFG0_MBE1_WIDTH (1U) 179 #define SMU_MRU_CH_CFG0_MBE1(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_CH_CFG0_MBE1_SHIFT)) & SMU_MRU_CH_CFG0_MBE1_MASK) 180 181 #define SMU_MRU_CH_CFG0_MBE2_MASK (0x40000U) 182 #define SMU_MRU_CH_CFG0_MBE2_SHIFT (18U) 183 #define SMU_MRU_CH_CFG0_MBE2_WIDTH (1U) 184 #define SMU_MRU_CH_CFG0_MBE2(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_CH_CFG0_MBE2_SHIFT)) & SMU_MRU_CH_CFG0_MBE2_MASK) 185 186 #define SMU_MRU_CH_CFG0_MBE3_MASK (0x80000U) 187 #define SMU_MRU_CH_CFG0_MBE3_SHIFT (19U) 188 #define SMU_MRU_CH_CFG0_MBE3_WIDTH (1U) 189 #define SMU_MRU_CH_CFG0_MBE3(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_CH_CFG0_MBE3_SHIFT)) & SMU_MRU_CH_CFG0_MBE3_MASK) 190 /*! @} */ 191 192 /*! @name CH_CFG1 - Channel (x) Configuration 1 */ 193 /*! @{ */ 194 195 #define SMU_MRU_CH_CFG1_MBIC0_MASK (0x10000U) 196 #define SMU_MRU_CH_CFG1_MBIC0_SHIFT (16U) 197 #define SMU_MRU_CH_CFG1_MBIC0_WIDTH (1U) 198 #define SMU_MRU_CH_CFG1_MBIC0(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_CH_CFG1_MBIC0_SHIFT)) & SMU_MRU_CH_CFG1_MBIC0_MASK) 199 200 #define SMU_MRU_CH_CFG1_MBIC1_MASK (0x20000U) 201 #define SMU_MRU_CH_CFG1_MBIC1_SHIFT (17U) 202 #define SMU_MRU_CH_CFG1_MBIC1_WIDTH (1U) 203 #define SMU_MRU_CH_CFG1_MBIC1(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_CH_CFG1_MBIC1_SHIFT)) & SMU_MRU_CH_CFG1_MBIC1_MASK) 204 205 #define SMU_MRU_CH_CFG1_MBIC2_MASK (0x40000U) 206 #define SMU_MRU_CH_CFG1_MBIC2_SHIFT (18U) 207 #define SMU_MRU_CH_CFG1_MBIC2_WIDTH (1U) 208 #define SMU_MRU_CH_CFG1_MBIC2(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_CH_CFG1_MBIC2_SHIFT)) & SMU_MRU_CH_CFG1_MBIC2_MASK) 209 210 #define SMU_MRU_CH_CFG1_MBIC3_MASK (0x80000U) 211 #define SMU_MRU_CH_CFG1_MBIC3_SHIFT (19U) 212 #define SMU_MRU_CH_CFG1_MBIC3_WIDTH (1U) 213 #define SMU_MRU_CH_CFG1_MBIC3(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_CH_CFG1_MBIC3_SHIFT)) & SMU_MRU_CH_CFG1_MBIC3_MASK) 214 /*! @} */ 215 216 /*! @name CH_MBSTAT - Channel (x) Mailbox Status */ 217 /*! @{ */ 218 219 #define SMU_MRU_CH_MBSTAT_MBS0_MASK (0x10000U) 220 #define SMU_MRU_CH_MBSTAT_MBS0_SHIFT (16U) 221 #define SMU_MRU_CH_MBSTAT_MBS0_WIDTH (1U) 222 #define SMU_MRU_CH_MBSTAT_MBS0(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_CH_MBSTAT_MBS0_SHIFT)) & SMU_MRU_CH_MBSTAT_MBS0_MASK) 223 224 #define SMU_MRU_CH_MBSTAT_MBS1_MASK (0x20000U) 225 #define SMU_MRU_CH_MBSTAT_MBS1_SHIFT (17U) 226 #define SMU_MRU_CH_MBSTAT_MBS1_WIDTH (1U) 227 #define SMU_MRU_CH_MBSTAT_MBS1(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_CH_MBSTAT_MBS1_SHIFT)) & SMU_MRU_CH_MBSTAT_MBS1_MASK) 228 229 #define SMU_MRU_CH_MBSTAT_MBS2_MASK (0x40000U) 230 #define SMU_MRU_CH_MBSTAT_MBS2_SHIFT (18U) 231 #define SMU_MRU_CH_MBSTAT_MBS2_WIDTH (1U) 232 #define SMU_MRU_CH_MBSTAT_MBS2(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_CH_MBSTAT_MBS2_SHIFT)) & SMU_MRU_CH_MBSTAT_MBS2_MASK) 233 234 #define SMU_MRU_CH_MBSTAT_MBS3_MASK (0x80000U) 235 #define SMU_MRU_CH_MBSTAT_MBS3_SHIFT (19U) 236 #define SMU_MRU_CH_MBSTAT_MBS3_WIDTH (1U) 237 #define SMU_MRU_CH_MBSTAT_MBS3(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_CH_MBSTAT_MBS3_SHIFT)) & SMU_MRU_CH_MBSTAT_MBS3_MASK) 238 /*! @} */ 239 240 /*! @name NOTIFY - Notification 0 Status..Notification 1 Status */ 241 /*! @{ */ 242 243 #define SMU_MRU_NOTIFY_CH1_IS0_MASK (0x1U) 244 #define SMU_MRU_NOTIFY_CH1_IS0_SHIFT (0U) 245 #define SMU_MRU_NOTIFY_CH1_IS0_WIDTH (1U) 246 #define SMU_MRU_NOTIFY_CH1_IS0(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_NOTIFY_CH1_IS0_SHIFT)) & SMU_MRU_NOTIFY_CH1_IS0_MASK) 247 248 #define SMU_MRU_NOTIFY_CH2_IS0_MASK (0x2U) 249 #define SMU_MRU_NOTIFY_CH2_IS0_SHIFT (1U) 250 #define SMU_MRU_NOTIFY_CH2_IS0_WIDTH (1U) 251 #define SMU_MRU_NOTIFY_CH2_IS0(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_NOTIFY_CH2_IS0_SHIFT)) & SMU_MRU_NOTIFY_CH2_IS0_MASK) 252 253 #define SMU_MRU_NOTIFY_CH3_IS0_MASK (0x4U) 254 #define SMU_MRU_NOTIFY_CH3_IS0_SHIFT (2U) 255 #define SMU_MRU_NOTIFY_CH3_IS0_WIDTH (1U) 256 #define SMU_MRU_NOTIFY_CH3_IS0(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_NOTIFY_CH3_IS0_SHIFT)) & SMU_MRU_NOTIFY_CH3_IS0_MASK) 257 258 #define SMU_MRU_NOTIFY_CH4_IS0_MASK (0x8U) 259 #define SMU_MRU_NOTIFY_CH4_IS0_SHIFT (3U) 260 #define SMU_MRU_NOTIFY_CH4_IS0_WIDTH (1U) 261 #define SMU_MRU_NOTIFY_CH4_IS0(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_NOTIFY_CH4_IS0_SHIFT)) & SMU_MRU_NOTIFY_CH4_IS0_MASK) 262 263 #define SMU_MRU_NOTIFY_CH5_IS0_MASK (0x10U) 264 #define SMU_MRU_NOTIFY_CH5_IS0_SHIFT (4U) 265 #define SMU_MRU_NOTIFY_CH5_IS0_WIDTH (1U) 266 #define SMU_MRU_NOTIFY_CH5_IS0(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_NOTIFY_CH5_IS0_SHIFT)) & SMU_MRU_NOTIFY_CH5_IS0_MASK) 267 268 #define SMU_MRU_NOTIFY_CH6_IS0_MASK (0x20U) 269 #define SMU_MRU_NOTIFY_CH6_IS0_SHIFT (5U) 270 #define SMU_MRU_NOTIFY_CH6_IS0_WIDTH (1U) 271 #define SMU_MRU_NOTIFY_CH6_IS0(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_NOTIFY_CH6_IS0_SHIFT)) & SMU_MRU_NOTIFY_CH6_IS0_MASK) 272 273 #define SMU_MRU_NOTIFY_CH7_IS0_MASK (0x40U) 274 #define SMU_MRU_NOTIFY_CH7_IS0_SHIFT (6U) 275 #define SMU_MRU_NOTIFY_CH7_IS0_WIDTH (1U) 276 #define SMU_MRU_NOTIFY_CH7_IS0(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_NOTIFY_CH7_IS0_SHIFT)) & SMU_MRU_NOTIFY_CH7_IS0_MASK) 277 278 #define SMU_MRU_NOTIFY_CH8_IS0_MASK (0x80U) 279 #define SMU_MRU_NOTIFY_CH8_IS0_SHIFT (7U) 280 #define SMU_MRU_NOTIFY_CH8_IS0_WIDTH (1U) 281 #define SMU_MRU_NOTIFY_CH8_IS0(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_NOTIFY_CH8_IS0_SHIFT)) & SMU_MRU_NOTIFY_CH8_IS0_MASK) 282 283 #define SMU_MRU_NOTIFY_CH9_IS0_MASK (0x100U) 284 #define SMU_MRU_NOTIFY_CH9_IS0_SHIFT (8U) 285 #define SMU_MRU_NOTIFY_CH9_IS0_WIDTH (1U) 286 #define SMU_MRU_NOTIFY_CH9_IS0(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_NOTIFY_CH9_IS0_SHIFT)) & SMU_MRU_NOTIFY_CH9_IS0_MASK) 287 288 #define SMU_MRU_NOTIFY_CH10_IS0_MASK (0x200U) 289 #define SMU_MRU_NOTIFY_CH10_IS0_SHIFT (9U) 290 #define SMU_MRU_NOTIFY_CH10_IS0_WIDTH (1U) 291 #define SMU_MRU_NOTIFY_CH10_IS0(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_NOTIFY_CH10_IS0_SHIFT)) & SMU_MRU_NOTIFY_CH10_IS0_MASK) 292 293 #define SMU_MRU_NOTIFY_CH11_IS0_MASK (0x400U) 294 #define SMU_MRU_NOTIFY_CH11_IS0_SHIFT (10U) 295 #define SMU_MRU_NOTIFY_CH11_IS0_WIDTH (1U) 296 #define SMU_MRU_NOTIFY_CH11_IS0(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_NOTIFY_CH11_IS0_SHIFT)) & SMU_MRU_NOTIFY_CH11_IS0_MASK) 297 298 #define SMU_MRU_NOTIFY_CH12_IS0_MASK (0x800U) 299 #define SMU_MRU_NOTIFY_CH12_IS0_SHIFT (11U) 300 #define SMU_MRU_NOTIFY_CH12_IS0_WIDTH (1U) 301 #define SMU_MRU_NOTIFY_CH12_IS0(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_NOTIFY_CH12_IS0_SHIFT)) & SMU_MRU_NOTIFY_CH12_IS0_MASK) 302 303 #define SMU_MRU_NOTIFY_CH1_IS1_MASK (0x1U) 304 #define SMU_MRU_NOTIFY_CH1_IS1_SHIFT (0U) 305 #define SMU_MRU_NOTIFY_CH1_IS1_WIDTH (1U) 306 #define SMU_MRU_NOTIFY_CH1_IS1(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_NOTIFY_CH1_IS1_SHIFT)) & SMU_MRU_NOTIFY_CH1_IS1_MASK) 307 308 #define SMU_MRU_NOTIFY_CH2_IS1_MASK (0x2U) 309 #define SMU_MRU_NOTIFY_CH2_IS1_SHIFT (1U) 310 #define SMU_MRU_NOTIFY_CH2_IS1_WIDTH (1U) 311 #define SMU_MRU_NOTIFY_CH2_IS1(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_NOTIFY_CH2_IS1_SHIFT)) & SMU_MRU_NOTIFY_CH2_IS1_MASK) 312 313 #define SMU_MRU_NOTIFY_CH3_IS1_MASK (0x4U) 314 #define SMU_MRU_NOTIFY_CH3_IS1_SHIFT (2U) 315 #define SMU_MRU_NOTIFY_CH3_IS1_WIDTH (1U) 316 #define SMU_MRU_NOTIFY_CH3_IS1(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_NOTIFY_CH3_IS1_SHIFT)) & SMU_MRU_NOTIFY_CH3_IS1_MASK) 317 318 #define SMU_MRU_NOTIFY_CH4_IS1_MASK (0x8U) 319 #define SMU_MRU_NOTIFY_CH4_IS1_SHIFT (3U) 320 #define SMU_MRU_NOTIFY_CH4_IS1_WIDTH (1U) 321 #define SMU_MRU_NOTIFY_CH4_IS1(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_NOTIFY_CH4_IS1_SHIFT)) & SMU_MRU_NOTIFY_CH4_IS1_MASK) 322 323 #define SMU_MRU_NOTIFY_CH5_IS1_MASK (0x10U) 324 #define SMU_MRU_NOTIFY_CH5_IS1_SHIFT (4U) 325 #define SMU_MRU_NOTIFY_CH5_IS1_WIDTH (1U) 326 #define SMU_MRU_NOTIFY_CH5_IS1(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_NOTIFY_CH5_IS1_SHIFT)) & SMU_MRU_NOTIFY_CH5_IS1_MASK) 327 328 #define SMU_MRU_NOTIFY_CH6_IS1_MASK (0x20U) 329 #define SMU_MRU_NOTIFY_CH6_IS1_SHIFT (5U) 330 #define SMU_MRU_NOTIFY_CH6_IS1_WIDTH (1U) 331 #define SMU_MRU_NOTIFY_CH6_IS1(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_NOTIFY_CH6_IS1_SHIFT)) & SMU_MRU_NOTIFY_CH6_IS1_MASK) 332 333 #define SMU_MRU_NOTIFY_CH7_IS1_MASK (0x40U) 334 #define SMU_MRU_NOTIFY_CH7_IS1_SHIFT (6U) 335 #define SMU_MRU_NOTIFY_CH7_IS1_WIDTH (1U) 336 #define SMU_MRU_NOTIFY_CH7_IS1(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_NOTIFY_CH7_IS1_SHIFT)) & SMU_MRU_NOTIFY_CH7_IS1_MASK) 337 338 #define SMU_MRU_NOTIFY_CH8_IS1_MASK (0x80U) 339 #define SMU_MRU_NOTIFY_CH8_IS1_SHIFT (7U) 340 #define SMU_MRU_NOTIFY_CH8_IS1_WIDTH (1U) 341 #define SMU_MRU_NOTIFY_CH8_IS1(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_NOTIFY_CH8_IS1_SHIFT)) & SMU_MRU_NOTIFY_CH8_IS1_MASK) 342 343 #define SMU_MRU_NOTIFY_CH9_IS1_MASK (0x100U) 344 #define SMU_MRU_NOTIFY_CH9_IS1_SHIFT (8U) 345 #define SMU_MRU_NOTIFY_CH9_IS1_WIDTH (1U) 346 #define SMU_MRU_NOTIFY_CH9_IS1(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_NOTIFY_CH9_IS1_SHIFT)) & SMU_MRU_NOTIFY_CH9_IS1_MASK) 347 348 #define SMU_MRU_NOTIFY_CH10_IS1_MASK (0x200U) 349 #define SMU_MRU_NOTIFY_CH10_IS1_SHIFT (9U) 350 #define SMU_MRU_NOTIFY_CH10_IS1_WIDTH (1U) 351 #define SMU_MRU_NOTIFY_CH10_IS1(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_NOTIFY_CH10_IS1_SHIFT)) & SMU_MRU_NOTIFY_CH10_IS1_MASK) 352 353 #define SMU_MRU_NOTIFY_CH11_IS1_MASK (0x400U) 354 #define SMU_MRU_NOTIFY_CH11_IS1_SHIFT (10U) 355 #define SMU_MRU_NOTIFY_CH11_IS1_WIDTH (1U) 356 #define SMU_MRU_NOTIFY_CH11_IS1(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_NOTIFY_CH11_IS1_SHIFT)) & SMU_MRU_NOTIFY_CH11_IS1_MASK) 357 358 #define SMU_MRU_NOTIFY_CH12_IS1_MASK (0x800U) 359 #define SMU_MRU_NOTIFY_CH12_IS1_SHIFT (11U) 360 #define SMU_MRU_NOTIFY_CH12_IS1_WIDTH (1U) 361 #define SMU_MRU_NOTIFY_CH12_IS1(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_NOTIFY_CH12_IS1_SHIFT)) & SMU_MRU_NOTIFY_CH12_IS1_MASK) 362 /*! @} */ 363 364 /*! @name CH1_MB0 - Channel (x) Mailbox (n) */ 365 /*! @{ */ 366 367 #define SMU_MRU_CH1_MB0_MBD_MASK (0xFFFFFFFFU) 368 #define SMU_MRU_CH1_MB0_MBD_SHIFT (0U) 369 #define SMU_MRU_CH1_MB0_MBD_WIDTH (32U) 370 #define SMU_MRU_CH1_MB0_MBD(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_CH1_MB0_MBD_SHIFT)) & SMU_MRU_CH1_MB0_MBD_MASK) 371 /*! @} */ 372 373 /*! @name CH1_MB1 - Channel (x) Mailbox (n) */ 374 /*! @{ */ 375 376 #define SMU_MRU_CH1_MB1_MBD_MASK (0xFFFFFFFFU) 377 #define SMU_MRU_CH1_MB1_MBD_SHIFT (0U) 378 #define SMU_MRU_CH1_MB1_MBD_WIDTH (32U) 379 #define SMU_MRU_CH1_MB1_MBD(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_CH1_MB1_MBD_SHIFT)) & SMU_MRU_CH1_MB1_MBD_MASK) 380 /*! @} */ 381 382 /*! @name CH1_MB2 - Channel (x) Mailbox (n) */ 383 /*! @{ */ 384 385 #define SMU_MRU_CH1_MB2_MBD_MASK (0xFFFFFFFFU) 386 #define SMU_MRU_CH1_MB2_MBD_SHIFT (0U) 387 #define SMU_MRU_CH1_MB2_MBD_WIDTH (32U) 388 #define SMU_MRU_CH1_MB2_MBD(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_CH1_MB2_MBD_SHIFT)) & SMU_MRU_CH1_MB2_MBD_MASK) 389 /*! @} */ 390 391 /*! @name CH1_MB3 - Channel (x) Mailbox (n) */ 392 /*! @{ */ 393 394 #define SMU_MRU_CH1_MB3_MBD_MASK (0xFFFFFFFFU) 395 #define SMU_MRU_CH1_MB3_MBD_SHIFT (0U) 396 #define SMU_MRU_CH1_MB3_MBD_WIDTH (32U) 397 #define SMU_MRU_CH1_MB3_MBD(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_CH1_MB3_MBD_SHIFT)) & SMU_MRU_CH1_MB3_MBD_MASK) 398 /*! @} */ 399 400 /*! @name CH2_MB0 - Channel (x) Mailbox (n) */ 401 /*! @{ */ 402 403 #define SMU_MRU_CH2_MB0_MBD_MASK (0xFFFFFFFFU) 404 #define SMU_MRU_CH2_MB0_MBD_SHIFT (0U) 405 #define SMU_MRU_CH2_MB0_MBD_WIDTH (32U) 406 #define SMU_MRU_CH2_MB0_MBD(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_CH2_MB0_MBD_SHIFT)) & SMU_MRU_CH2_MB0_MBD_MASK) 407 /*! @} */ 408 409 /*! @name CH2_MB1 - Channel (x) Mailbox (n) */ 410 /*! @{ */ 411 412 #define SMU_MRU_CH2_MB1_MBD_MASK (0xFFFFFFFFU) 413 #define SMU_MRU_CH2_MB1_MBD_SHIFT (0U) 414 #define SMU_MRU_CH2_MB1_MBD_WIDTH (32U) 415 #define SMU_MRU_CH2_MB1_MBD(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_CH2_MB1_MBD_SHIFT)) & SMU_MRU_CH2_MB1_MBD_MASK) 416 /*! @} */ 417 418 /*! @name CH2_MB2 - Channel (x) Mailbox (n) */ 419 /*! @{ */ 420 421 #define SMU_MRU_CH2_MB2_MBD_MASK (0xFFFFFFFFU) 422 #define SMU_MRU_CH2_MB2_MBD_SHIFT (0U) 423 #define SMU_MRU_CH2_MB2_MBD_WIDTH (32U) 424 #define SMU_MRU_CH2_MB2_MBD(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_CH2_MB2_MBD_SHIFT)) & SMU_MRU_CH2_MB2_MBD_MASK) 425 /*! @} */ 426 427 /*! @name CH2_MB3 - Channel (x) Mailbox (n) */ 428 /*! @{ */ 429 430 #define SMU_MRU_CH2_MB3_MBD_MASK (0xFFFFFFFFU) 431 #define SMU_MRU_CH2_MB3_MBD_SHIFT (0U) 432 #define SMU_MRU_CH2_MB3_MBD_WIDTH (32U) 433 #define SMU_MRU_CH2_MB3_MBD(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_CH2_MB3_MBD_SHIFT)) & SMU_MRU_CH2_MB3_MBD_MASK) 434 /*! @} */ 435 436 /*! @name CH3_MB0 - Channel (x) Mailbox (n) */ 437 /*! @{ */ 438 439 #define SMU_MRU_CH3_MB0_MBD_MASK (0xFFFFFFFFU) 440 #define SMU_MRU_CH3_MB0_MBD_SHIFT (0U) 441 #define SMU_MRU_CH3_MB0_MBD_WIDTH (32U) 442 #define SMU_MRU_CH3_MB0_MBD(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_CH3_MB0_MBD_SHIFT)) & SMU_MRU_CH3_MB0_MBD_MASK) 443 /*! @} */ 444 445 /*! @name CH3_MB1 - Channel (x) Mailbox (n) */ 446 /*! @{ */ 447 448 #define SMU_MRU_CH3_MB1_MBD_MASK (0xFFFFFFFFU) 449 #define SMU_MRU_CH3_MB1_MBD_SHIFT (0U) 450 #define SMU_MRU_CH3_MB1_MBD_WIDTH (32U) 451 #define SMU_MRU_CH3_MB1_MBD(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_CH3_MB1_MBD_SHIFT)) & SMU_MRU_CH3_MB1_MBD_MASK) 452 /*! @} */ 453 454 /*! @name CH3_MB2 - Channel (x) Mailbox (n) */ 455 /*! @{ */ 456 457 #define SMU_MRU_CH3_MB2_MBD_MASK (0xFFFFFFFFU) 458 #define SMU_MRU_CH3_MB2_MBD_SHIFT (0U) 459 #define SMU_MRU_CH3_MB2_MBD_WIDTH (32U) 460 #define SMU_MRU_CH3_MB2_MBD(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_CH3_MB2_MBD_SHIFT)) & SMU_MRU_CH3_MB2_MBD_MASK) 461 /*! @} */ 462 463 /*! @name CH3_MB3 - Channel (x) Mailbox (n) */ 464 /*! @{ */ 465 466 #define SMU_MRU_CH3_MB3_MBD_MASK (0xFFFFFFFFU) 467 #define SMU_MRU_CH3_MB3_MBD_SHIFT (0U) 468 #define SMU_MRU_CH3_MB3_MBD_WIDTH (32U) 469 #define SMU_MRU_CH3_MB3_MBD(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_CH3_MB3_MBD_SHIFT)) & SMU_MRU_CH3_MB3_MBD_MASK) 470 /*! @} */ 471 472 /*! @name CH4_MB0 - Channel (x) Mailbox (n) */ 473 /*! @{ */ 474 475 #define SMU_MRU_CH4_MB0_MBD_MASK (0xFFFFFFFFU) 476 #define SMU_MRU_CH4_MB0_MBD_SHIFT (0U) 477 #define SMU_MRU_CH4_MB0_MBD_WIDTH (32U) 478 #define SMU_MRU_CH4_MB0_MBD(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_CH4_MB0_MBD_SHIFT)) & SMU_MRU_CH4_MB0_MBD_MASK) 479 /*! @} */ 480 481 /*! @name CH4_MB1 - Channel (x) Mailbox (n) */ 482 /*! @{ */ 483 484 #define SMU_MRU_CH4_MB1_MBD_MASK (0xFFFFFFFFU) 485 #define SMU_MRU_CH4_MB1_MBD_SHIFT (0U) 486 #define SMU_MRU_CH4_MB1_MBD_WIDTH (32U) 487 #define SMU_MRU_CH4_MB1_MBD(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_CH4_MB1_MBD_SHIFT)) & SMU_MRU_CH4_MB1_MBD_MASK) 488 /*! @} */ 489 490 /*! @name CH4_MB2 - Channel (x) Mailbox (n) */ 491 /*! @{ */ 492 493 #define SMU_MRU_CH4_MB2_MBD_MASK (0xFFFFFFFFU) 494 #define SMU_MRU_CH4_MB2_MBD_SHIFT (0U) 495 #define SMU_MRU_CH4_MB2_MBD_WIDTH (32U) 496 #define SMU_MRU_CH4_MB2_MBD(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_CH4_MB2_MBD_SHIFT)) & SMU_MRU_CH4_MB2_MBD_MASK) 497 /*! @} */ 498 499 /*! @name CH4_MB3 - Channel (x) Mailbox (n) */ 500 /*! @{ */ 501 502 #define SMU_MRU_CH4_MB3_MBD_MASK (0xFFFFFFFFU) 503 #define SMU_MRU_CH4_MB3_MBD_SHIFT (0U) 504 #define SMU_MRU_CH4_MB3_MBD_WIDTH (32U) 505 #define SMU_MRU_CH4_MB3_MBD(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_CH4_MB3_MBD_SHIFT)) & SMU_MRU_CH4_MB3_MBD_MASK) 506 /*! @} */ 507 508 /*! @name CH5_MB0 - Channel (x) Mailbox (n) */ 509 /*! @{ */ 510 511 #define SMU_MRU_CH5_MB0_MBD_MASK (0xFFFFFFFFU) 512 #define SMU_MRU_CH5_MB0_MBD_SHIFT (0U) 513 #define SMU_MRU_CH5_MB0_MBD_WIDTH (32U) 514 #define SMU_MRU_CH5_MB0_MBD(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_CH5_MB0_MBD_SHIFT)) & SMU_MRU_CH5_MB0_MBD_MASK) 515 /*! @} */ 516 517 /*! @name CH5_MB1 - Channel (x) Mailbox (n) */ 518 /*! @{ */ 519 520 #define SMU_MRU_CH5_MB1_MBD_MASK (0xFFFFFFFFU) 521 #define SMU_MRU_CH5_MB1_MBD_SHIFT (0U) 522 #define SMU_MRU_CH5_MB1_MBD_WIDTH (32U) 523 #define SMU_MRU_CH5_MB1_MBD(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_CH5_MB1_MBD_SHIFT)) & SMU_MRU_CH5_MB1_MBD_MASK) 524 /*! @} */ 525 526 /*! @name CH6_MB0 - Channel (x) Mailbox (n) */ 527 /*! @{ */ 528 529 #define SMU_MRU_CH6_MB0_MBD_MASK (0xFFFFFFFFU) 530 #define SMU_MRU_CH6_MB0_MBD_SHIFT (0U) 531 #define SMU_MRU_CH6_MB0_MBD_WIDTH (32U) 532 #define SMU_MRU_CH6_MB0_MBD(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_CH6_MB0_MBD_SHIFT)) & SMU_MRU_CH6_MB0_MBD_MASK) 533 /*! @} */ 534 535 /*! @name CH6_MB1 - Channel (x) Mailbox (n) */ 536 /*! @{ */ 537 538 #define SMU_MRU_CH6_MB1_MBD_MASK (0xFFFFFFFFU) 539 #define SMU_MRU_CH6_MB1_MBD_SHIFT (0U) 540 #define SMU_MRU_CH6_MB1_MBD_WIDTH (32U) 541 #define SMU_MRU_CH6_MB1_MBD(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_CH6_MB1_MBD_SHIFT)) & SMU_MRU_CH6_MB1_MBD_MASK) 542 /*! @} */ 543 544 /*! @name CH7_MB0 - Channel (x) Mailbox (n) */ 545 /*! @{ */ 546 547 #define SMU_MRU_CH7_MB0_MBD_MASK (0xFFFFFFFFU) 548 #define SMU_MRU_CH7_MB0_MBD_SHIFT (0U) 549 #define SMU_MRU_CH7_MB0_MBD_WIDTH (32U) 550 #define SMU_MRU_CH7_MB0_MBD(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_CH7_MB0_MBD_SHIFT)) & SMU_MRU_CH7_MB0_MBD_MASK) 551 /*! @} */ 552 553 /*! @name CH7_MB1 - Channel (x) Mailbox (n) */ 554 /*! @{ */ 555 556 #define SMU_MRU_CH7_MB1_MBD_MASK (0xFFFFFFFFU) 557 #define SMU_MRU_CH7_MB1_MBD_SHIFT (0U) 558 #define SMU_MRU_CH7_MB1_MBD_WIDTH (32U) 559 #define SMU_MRU_CH7_MB1_MBD(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_CH7_MB1_MBD_SHIFT)) & SMU_MRU_CH7_MB1_MBD_MASK) 560 /*! @} */ 561 562 /*! @name CH8_MB0 - Channel (x) Mailbox (n) */ 563 /*! @{ */ 564 565 #define SMU_MRU_CH8_MB0_MBD_MASK (0xFFFFFFFFU) 566 #define SMU_MRU_CH8_MB0_MBD_SHIFT (0U) 567 #define SMU_MRU_CH8_MB0_MBD_WIDTH (32U) 568 #define SMU_MRU_CH8_MB0_MBD(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_CH8_MB0_MBD_SHIFT)) & SMU_MRU_CH8_MB0_MBD_MASK) 569 /*! @} */ 570 571 /*! @name CH8_MB1 - Channel (x) Mailbox (n) */ 572 /*! @{ */ 573 574 #define SMU_MRU_CH8_MB1_MBD_MASK (0xFFFFFFFFU) 575 #define SMU_MRU_CH8_MB1_MBD_SHIFT (0U) 576 #define SMU_MRU_CH8_MB1_MBD_WIDTH (32U) 577 #define SMU_MRU_CH8_MB1_MBD(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_CH8_MB1_MBD_SHIFT)) & SMU_MRU_CH8_MB1_MBD_MASK) 578 /*! @} */ 579 580 /*! @name CH9_MB0 - Channel (x) Mailbox (n) */ 581 /*! @{ */ 582 583 #define SMU_MRU_CH9_MB0_MBD_MASK (0xFFFFFFFFU) 584 #define SMU_MRU_CH9_MB0_MBD_SHIFT (0U) 585 #define SMU_MRU_CH9_MB0_MBD_WIDTH (32U) 586 #define SMU_MRU_CH9_MB0_MBD(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_CH9_MB0_MBD_SHIFT)) & SMU_MRU_CH9_MB0_MBD_MASK) 587 /*! @} */ 588 589 /*! @name CH9_MB1 - Channel (x) Mailbox (n) */ 590 /*! @{ */ 591 592 #define SMU_MRU_CH9_MB1_MBD_MASK (0xFFFFFFFFU) 593 #define SMU_MRU_CH9_MB1_MBD_SHIFT (0U) 594 #define SMU_MRU_CH9_MB1_MBD_WIDTH (32U) 595 #define SMU_MRU_CH9_MB1_MBD(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_CH9_MB1_MBD_SHIFT)) & SMU_MRU_CH9_MB1_MBD_MASK) 596 /*! @} */ 597 598 /*! @name CH10_MB0 - Channel (x) Mailbox (n) */ 599 /*! @{ */ 600 601 #define SMU_MRU_CH10_MB0_MBD_MASK (0xFFFFFFFFU) 602 #define SMU_MRU_CH10_MB0_MBD_SHIFT (0U) 603 #define SMU_MRU_CH10_MB0_MBD_WIDTH (32U) 604 #define SMU_MRU_CH10_MB0_MBD(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_CH10_MB0_MBD_SHIFT)) & SMU_MRU_CH10_MB0_MBD_MASK) 605 /*! @} */ 606 607 /*! @name CH10_MB1 - Channel (x) Mailbox (n) */ 608 /*! @{ */ 609 610 #define SMU_MRU_CH10_MB1_MBD_MASK (0xFFFFFFFFU) 611 #define SMU_MRU_CH10_MB1_MBD_SHIFT (0U) 612 #define SMU_MRU_CH10_MB1_MBD_WIDTH (32U) 613 #define SMU_MRU_CH10_MB1_MBD(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_CH10_MB1_MBD_SHIFT)) & SMU_MRU_CH10_MB1_MBD_MASK) 614 /*! @} */ 615 616 /*! @name CH11_MB0 - Channel (x) Mailbox (n) */ 617 /*! @{ */ 618 619 #define SMU_MRU_CH11_MB0_MBD_MASK (0xFFFFFFFFU) 620 #define SMU_MRU_CH11_MB0_MBD_SHIFT (0U) 621 #define SMU_MRU_CH11_MB0_MBD_WIDTH (32U) 622 #define SMU_MRU_CH11_MB0_MBD(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_CH11_MB0_MBD_SHIFT)) & SMU_MRU_CH11_MB0_MBD_MASK) 623 /*! @} */ 624 625 /*! @name CH11_MB1 - Channel (x) Mailbox (n) */ 626 /*! @{ */ 627 628 #define SMU_MRU_CH11_MB1_MBD_MASK (0xFFFFFFFFU) 629 #define SMU_MRU_CH11_MB1_MBD_SHIFT (0U) 630 #define SMU_MRU_CH11_MB1_MBD_WIDTH (32U) 631 #define SMU_MRU_CH11_MB1_MBD(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_CH11_MB1_MBD_SHIFT)) & SMU_MRU_CH11_MB1_MBD_MASK) 632 /*! @} */ 633 634 /*! @name CH12_MB0 - Channel (x) Mailbox (n) */ 635 /*! @{ */ 636 637 #define SMU_MRU_CH12_MB0_MBD_MASK (0xFFFFFFFFU) 638 #define SMU_MRU_CH12_MB0_MBD_SHIFT (0U) 639 #define SMU_MRU_CH12_MB0_MBD_WIDTH (32U) 640 #define SMU_MRU_CH12_MB0_MBD(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_CH12_MB0_MBD_SHIFT)) & SMU_MRU_CH12_MB0_MBD_MASK) 641 /*! @} */ 642 643 /*! @name CH12_MB1 - Channel (x) Mailbox (n) */ 644 /*! @{ */ 645 646 #define SMU_MRU_CH12_MB1_MBD_MASK (0xFFFFFFFFU) 647 #define SMU_MRU_CH12_MB1_MBD_SHIFT (0U) 648 #define SMU_MRU_CH12_MB1_MBD_WIDTH (32U) 649 #define SMU_MRU_CH12_MB1_MBD(x) (((uint32_t)(((uint32_t)(x)) << SMU_MRU_CH12_MB1_MBD_SHIFT)) & SMU_MRU_CH12_MB1_MBD_MASK) 650 /*! @} */ 651 652 /*! 653 * @} 654 */ /* end of group SMU_MRU_Register_Masks */ 655 656 /*! 657 * @} 658 */ /* end of group SMU_MRU_Peripheral_Access_Layer */ 659 660 #endif /* #if !defined(S32Z2_SMU_MRU_H_) */ 661
