1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K344_SIUL2.h 10 * @version 1.9 11 * @date 2021-10-27 12 * @brief Peripheral Access Layer for S32K344_SIUL2 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K344_SIUL2_H_) /* Check if memory map has not been already included */ 58 #define S32K344_SIUL2_H_ 59 60 #include "S32K344_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- SIUL2 Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup SIUL2_Peripheral_Access_Layer SIUL2 Peripheral Access Layer 68 * @{ 69 */ 70 71 /** SIUL2 - Size of Registers Arrays */ 72 #define SIUL2_IFMCR_COUNT 32u 73 #define SIUL2_MSCR_COUNT 220u 74 #define SIUL2_IMCR_COUNT 379u 75 #define SIUL2_MPGPDO_COUNT 14u 76 77 /** SIUL2 - Register Layout Typedef */ 78 typedef struct { 79 uint8_t RESERVED_0[4]; 80 __I uint32_t MIDR1; /**< SIUL2 MCU ID Register #1, offset: 0x4 */ 81 __I uint32_t MIDR2; /**< SIUL2 MCU ID Register #2, offset: 0x8 */ 82 uint8_t RESERVED_1[4]; 83 __IO uint32_t DISR0; /**< SIUL2 DMA/Interrupt Status Flag Register0, offset: 0x10 */ 84 uint8_t RESERVED_2[4]; 85 __IO uint32_t DIRER0; /**< SIUL2 DMA/Interrupt Request Enable Register0, offset: 0x18 */ 86 uint8_t RESERVED_3[4]; 87 __IO uint32_t DIRSR0; /**< SIUL2 DMA/Interrupt Request Select Register0, offset: 0x20 */ 88 uint8_t RESERVED_4[4]; 89 __IO uint32_t IREER0; /**< SIUL2 Interrupt Rising-Edge Event Enable Register 0, offset: 0x28 */ 90 uint8_t RESERVED_5[4]; 91 __IO uint32_t IFEER0; /**< SIUL2 Interrupt Falling-Edge Event Enable Register 0, offset: 0x30 */ 92 uint8_t RESERVED_6[4]; 93 __IO uint32_t IFER0; /**< SIUL2 Interrupt Filter Enable Register 0, offset: 0x38 */ 94 uint8_t RESERVED_7[4]; 95 __IO uint32_t IFMCR[SIUL2_IFMCR_COUNT]; /**< SIUL2 Interrupt Filter Maximum Counter Register, array offset: 0x40, array step: 0x4 */ 96 __IO uint32_t IFCPR; /**< SIUL2 Interrupt Filter Clock Prescaler Register, offset: 0xC0 */ 97 uint8_t RESERVED_8[316]; 98 __I uint32_t MIDR3; /**< SIUL2 MCU ID Register #3, offset: 0x200 */ 99 __I uint32_t MIDR4; /**< SIUL2 MCU ID Register #4, offset: 0x204 */ 100 uint8_t RESERVED_9[56]; 101 __IO uint32_t MSCR[SIUL2_MSCR_COUNT]; /**< SIUL2 Multiplexed Signal Configuration Register, array offset: 0x240, array step: 0x4 */ 102 uint8_t RESERVED_10[1168]; 103 __IO uint32_t IMCR[SIUL2_IMCR_COUNT]; /**< SIUL2 Input Multiplexed Signal Configuration Register, array offset: 0xA40, array step: 0x4 */ 104 uint8_t RESERVED_11[724]; 105 __IO uint8_t GPDO3; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1300 */ 106 __IO uint8_t GPDO2; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1301 */ 107 __IO uint8_t GPDO1; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1302 */ 108 __IO uint8_t GPDO0; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1303 */ 109 __IO uint8_t GPDO7; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1304 */ 110 __IO uint8_t GPDO6; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1305 */ 111 __IO uint8_t GPDO5; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1306 */ 112 __IO uint8_t GPDO4; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1307 */ 113 __IO uint8_t GPDO11; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1308 */ 114 __IO uint8_t GPDO10; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1309 */ 115 __IO uint8_t GPDO9; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x130A */ 116 __IO uint8_t GPDO8; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x130B */ 117 __IO uint8_t GPDO15; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x130C */ 118 __IO uint8_t GPDO14; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x130D */ 119 __IO uint8_t GPDO13; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x130E */ 120 __IO uint8_t GPDO12; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x130F */ 121 __IO uint8_t GPDO19; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1310 */ 122 __IO uint8_t GPDO18; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1311 */ 123 __IO uint8_t GPDO17; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1312 */ 124 __IO uint8_t GPDO16; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1313 */ 125 __IO uint8_t GPDO23; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1314 */ 126 __IO uint8_t GPDO22; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1315 */ 127 __IO uint8_t GPDO21; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1316 */ 128 __IO uint8_t GPDO20; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1317 */ 129 __IO uint8_t GPDO27; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1318 */ 130 __IO uint8_t GPDO26; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1319 */ 131 __IO uint8_t GPDO25; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x131A */ 132 __IO uint8_t GPDO24; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x131B */ 133 __IO uint8_t GPDO31; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x131C */ 134 __IO uint8_t GPDO30; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x131D */ 135 __IO uint8_t GPDO29; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x131E */ 136 __IO uint8_t GPDO28; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x131F */ 137 __IO uint8_t GPDO35; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1320 */ 138 __IO uint8_t GPDO34; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1321 */ 139 __IO uint8_t GPDO33; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1322 */ 140 __IO uint8_t GPDO32; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1323 */ 141 uint8_t RESERVED_12[2]; 142 __IO uint8_t GPDO37; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1326 */ 143 __IO uint8_t GPDO36; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1327 */ 144 __IO uint8_t GPDO43; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1328 */ 145 __IO uint8_t GPDO42; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1329 */ 146 __IO uint8_t GPDO41; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x132A */ 147 __IO uint8_t GPDO40; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x132B */ 148 __IO uint8_t GPDO47; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x132C */ 149 __IO uint8_t GPDO46; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x132D */ 150 __IO uint8_t GPDO45; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x132E */ 151 __IO uint8_t GPDO44; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x132F */ 152 __IO uint8_t GPDO51; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1330 */ 153 __IO uint8_t GPDO50; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1331 */ 154 __IO uint8_t GPDO49; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1332 */ 155 __IO uint8_t GPDO48; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1333 */ 156 __IO uint8_t GPDO55; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1334 */ 157 __IO uint8_t GPDO54; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1335 */ 158 __IO uint8_t GPDO53; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1336 */ 159 __IO uint8_t GPDO52; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1337 */ 160 __IO uint8_t GPDO59; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1338 */ 161 __IO uint8_t GPDO58; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1339 */ 162 __IO uint8_t GPDO57; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x133A */ 163 __IO uint8_t GPDO56; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x133B */ 164 __IO uint8_t GPDO63; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x133C */ 165 __IO uint8_t GPDO62; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x133D */ 166 __IO uint8_t GPDO61; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x133E */ 167 __IO uint8_t GPDO60; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x133F */ 168 __IO uint8_t GPDO67; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1340 */ 169 __IO uint8_t GPDO66; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1341 */ 170 __IO uint8_t GPDO65; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1342 */ 171 __IO uint8_t GPDO64; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1343 */ 172 __IO uint8_t GPDO71; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1344 */ 173 __IO uint8_t GPDO70; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1345 */ 174 __IO uint8_t GPDO69; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1346 */ 175 __IO uint8_t GPDO68; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1347 */ 176 __IO uint8_t GPDO75; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1348 */ 177 __IO uint8_t GPDO74; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1349 */ 178 __IO uint8_t GPDO73; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x134A */ 179 __IO uint8_t GPDO72; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x134B */ 180 __IO uint8_t GPDO79; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x134C */ 181 __IO uint8_t GPDO78; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x134D */ 182 __IO uint8_t GPDO77; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x134E */ 183 __IO uint8_t GPDO76; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x134F */ 184 __IO uint8_t GPDO83; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1350 */ 185 __IO uint8_t GPDO82; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1351 */ 186 __IO uint8_t GPDO81; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1352 */ 187 __IO uint8_t GPDO80; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1353 */ 188 __IO uint8_t GPDO87; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1354 */ 189 __IO uint8_t GPDO86; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1355 */ 190 __IO uint8_t GPDO85; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1356 */ 191 __IO uint8_t GPDO84; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1357 */ 192 __IO uint8_t GPDO91; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1358 */ 193 __IO uint8_t GPDO90; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1359 */ 194 __IO uint8_t GPDO89; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x135A */ 195 __IO uint8_t GPDO88; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x135B */ 196 __IO uint8_t GPDO95; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x135C */ 197 __IO uint8_t GPDO94; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x135D */ 198 __IO uint8_t GPDO93; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x135E */ 199 __IO uint8_t GPDO92; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x135F */ 200 __IO uint8_t GPDO99; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1360 */ 201 __IO uint8_t GPDO98; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1361 */ 202 __IO uint8_t GPDO97; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1362 */ 203 __IO uint8_t GPDO96; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1363 */ 204 __IO uint8_t GPDO103; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1364 */ 205 __IO uint8_t GPDO102; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1365 */ 206 __IO uint8_t GPDO101; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1366 */ 207 __IO uint8_t GPDO100; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1367 */ 208 __IO uint8_t GPDO107; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1368 */ 209 __IO uint8_t GPDO106; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1369 */ 210 __IO uint8_t GPDO105; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x136A */ 211 __IO uint8_t GPDO104; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x136B */ 212 __IO uint8_t GPDO111; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x136C */ 213 __IO uint8_t GPDO110; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x136D */ 214 __IO uint8_t GPDO109; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x136E */ 215 __IO uint8_t GPDO108; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x136F */ 216 __IO uint8_t GPDO115; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1370 */ 217 __IO uint8_t GPDO114; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1371 */ 218 __IO uint8_t GPDO113; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1372 */ 219 __IO uint8_t GPDO112; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1373 */ 220 __IO uint8_t GPDO119; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1374 */ 221 __IO uint8_t GPDO118; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1375 */ 222 __IO uint8_t GPDO117; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1376 */ 223 __IO uint8_t GPDO116; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1377 */ 224 __IO uint8_t GPDO123; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1378 */ 225 __IO uint8_t GPDO122; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1379 */ 226 __IO uint8_t GPDO121; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x137A */ 227 __IO uint8_t GPDO120; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x137B */ 228 __IO uint8_t GPDO127; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x137C */ 229 __IO uint8_t GPDO126; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x137D */ 230 __IO uint8_t GPDO125; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x137E */ 231 __IO uint8_t GPDO124; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x137F */ 232 __IO uint8_t GPDO131; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1380 */ 233 __IO uint8_t GPDO130; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1381 */ 234 __IO uint8_t GPDO129; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1382 */ 235 __IO uint8_t GPDO128; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1383 */ 236 __IO uint8_t GPDO135; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1384 */ 237 __IO uint8_t GPDO134; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1385 */ 238 __IO uint8_t GPDO133; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1386 */ 239 __IO uint8_t GPDO132; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1387 */ 240 __IO uint8_t GPDO139; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1388 */ 241 __IO uint8_t GPDO138; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1389 */ 242 __IO uint8_t GPDO137; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x138A */ 243 __IO uint8_t GPDO136; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x138B */ 244 __IO uint8_t GPDO143; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x138C */ 245 __IO uint8_t GPDO142; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x138D */ 246 __IO uint8_t GPDO141; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x138E */ 247 __IO uint8_t GPDO140; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x138F */ 248 __IO uint8_t GPDO147; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1390 */ 249 __IO uint8_t GPDO146; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1391 */ 250 __IO uint8_t GPDO145; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1392 */ 251 __IO uint8_t GPDO144; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1393 */ 252 __IO uint8_t GPDO151; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1394 */ 253 __IO uint8_t GPDO150; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1395 */ 254 __IO uint8_t GPDO149; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1396 */ 255 __IO uint8_t GPDO148; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1397 */ 256 __IO uint8_t GPDO155; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1398 */ 257 __IO uint8_t GPDO154; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1399 */ 258 __IO uint8_t GPDO153; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x139A */ 259 __IO uint8_t GPDO152; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x139B */ 260 __IO uint8_t GPDO159; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x139C */ 261 __IO uint8_t GPDO158; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x139D */ 262 __IO uint8_t GPDO157; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x139E */ 263 __IO uint8_t GPDO156; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x139F */ 264 __IO uint8_t GPDO163; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13A0 */ 265 __IO uint8_t GPDO162; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13A1 */ 266 __IO uint8_t GPDO161; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13A2 */ 267 __IO uint8_t GPDO160; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13A3 */ 268 __IO uint8_t GPDO167; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13A4 */ 269 __IO uint8_t GPDO166; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13A5 */ 270 __IO uint8_t GPDO165; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13A6 */ 271 __IO uint8_t GPDO164; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13A7 */ 272 __IO uint8_t GPDO171; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13A8 */ 273 __IO uint8_t GPDO170; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13A9 */ 274 __IO uint8_t GPDO169; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13AA */ 275 __IO uint8_t GPDO168; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13AB */ 276 __IO uint8_t GPDO175; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13AC */ 277 __IO uint8_t GPDO174; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13AD */ 278 __IO uint8_t GPDO173; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13AE */ 279 __IO uint8_t GPDO172; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13AF */ 280 __IO uint8_t GPDO179; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13B0 */ 281 __IO uint8_t GPDO178; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13B1 */ 282 __IO uint8_t GPDO177; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13B2 */ 283 __IO uint8_t GPDO176; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13B3 */ 284 __IO uint8_t GPDO183; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13B4 */ 285 __IO uint8_t GPDO182; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13B5 */ 286 __IO uint8_t GPDO181; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13B6 */ 287 __IO uint8_t GPDO180; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13B7 */ 288 __IO uint8_t GPDO187; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13B8 */ 289 __IO uint8_t GPDO186; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13B9 */ 290 __IO uint8_t GPDO185; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13BA */ 291 __IO uint8_t GPDO184; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13BB */ 292 __IO uint8_t GPDO191; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13BC */ 293 __IO uint8_t GPDO190; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13BD */ 294 __IO uint8_t GPDO189; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13BE */ 295 __IO uint8_t GPDO188; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13BF */ 296 __IO uint8_t GPDO195; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13C0 */ 297 __IO uint8_t GPDO194; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13C1 */ 298 __IO uint8_t GPDO193; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13C2 */ 299 __IO uint8_t GPDO192; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13C3 */ 300 __IO uint8_t GPDO199; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13C4 */ 301 __IO uint8_t GPDO198; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13C5 */ 302 __IO uint8_t GPDO197; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13C6 */ 303 __IO uint8_t GPDO196; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13C7 */ 304 __IO uint8_t GPDO203; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13C8 */ 305 __IO uint8_t GPDO202; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13C9 */ 306 __IO uint8_t GPDO201; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13CA */ 307 __IO uint8_t GPDO200; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13CB */ 308 __IO uint8_t GPDO207; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13CC */ 309 __IO uint8_t GPDO206; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13CD */ 310 __IO uint8_t GPDO205; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13CE */ 311 __IO uint8_t GPDO204; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13CF */ 312 __IO uint8_t GPDO211; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13D0 */ 313 __IO uint8_t GPDO210; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13D1 */ 314 __IO uint8_t GPDO209; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13D2 */ 315 __IO uint8_t GPDO208; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13D3 */ 316 __IO uint8_t GPDO215; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13D4 */ 317 __IO uint8_t GPDO214; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13D5 */ 318 __IO uint8_t GPDO213; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13D6 */ 319 __IO uint8_t GPDO212; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13D7 */ 320 __IO uint8_t GPDO219; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13D8 */ 321 __IO uint8_t GPDO218; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13D9 */ 322 __IO uint8_t GPDO217; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13DA */ 323 __IO uint8_t GPDO216; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13DB */ 324 uint8_t RESERVED_13[292]; 325 __I uint8_t GPDI3; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1500 */ 326 __I uint8_t GPDI2; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1501 */ 327 __I uint8_t GPDI1; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1502 */ 328 __I uint8_t GPDI0; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1503 */ 329 __I uint8_t GPDI7; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1504 */ 330 __I uint8_t GPDI6; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1505 */ 331 __I uint8_t GPDI5; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1506 */ 332 __I uint8_t GPDI4; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1507 */ 333 __I uint8_t GPDI11; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1508 */ 334 __I uint8_t GPDI10; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1509 */ 335 __I uint8_t GPDI9; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x150A */ 336 __I uint8_t GPDI8; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x150B */ 337 __I uint8_t GPDI15; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x150C */ 338 __I uint8_t GPDI14; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x150D */ 339 __I uint8_t GPDI13; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x150E */ 340 __I uint8_t GPDI12; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x150F */ 341 __I uint8_t GPDI19; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1510 */ 342 __I uint8_t GPDI18; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1511 */ 343 __I uint8_t GPDI17; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1512 */ 344 __I uint8_t GPDI16; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1513 */ 345 __I uint8_t GPDI23; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1514 */ 346 __I uint8_t GPDI22; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1515 */ 347 __I uint8_t GPDI21; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1516 */ 348 __I uint8_t GPDI20; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1517 */ 349 __I uint8_t GPDI27; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1518 */ 350 __I uint8_t GPDI26; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1519 */ 351 __I uint8_t GPDI25; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x151A */ 352 __I uint8_t GPDI24; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x151B */ 353 __I uint8_t GPDI31; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x151C */ 354 __I uint8_t GPDI30; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x151D */ 355 __I uint8_t GPDI29; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x151E */ 356 __I uint8_t GPDI28; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x151F */ 357 __I uint8_t GPDI35; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1520 */ 358 __I uint8_t GPDI34; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1521 */ 359 __I uint8_t GPDI33; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1522 */ 360 __I uint8_t GPDI32; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1523 */ 361 uint8_t RESERVED_14[2]; 362 __I uint8_t GPDI37; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1526 */ 363 __I uint8_t GPDI36; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1527 */ 364 __I uint8_t GPDI43; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1528 */ 365 __I uint8_t GPDI42; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1529 */ 366 __I uint8_t GPDI41; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x152A */ 367 __I uint8_t GPDI40; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x152B */ 368 __I uint8_t GPDI47; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x152C */ 369 __I uint8_t GPDI46; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x152D */ 370 __I uint8_t GPDI45; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x152E */ 371 __I uint8_t GPDI44; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x152F */ 372 __I uint8_t GPDI51; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1530 */ 373 __I uint8_t GPDI50; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1531 */ 374 __I uint8_t GPDI49; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1532 */ 375 __I uint8_t GPDI48; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1533 */ 376 __I uint8_t GPDI55; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1534 */ 377 __I uint8_t GPDI54; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1535 */ 378 __I uint8_t GPDI53; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1536 */ 379 __I uint8_t GPDI52; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1537 */ 380 __I uint8_t GPDI59; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1538 */ 381 __I uint8_t GPDI58; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1539 */ 382 __I uint8_t GPDI57; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x153A */ 383 __I uint8_t GPDI56; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x153B */ 384 __I uint8_t GPDI63; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x153C */ 385 __I uint8_t GPDI62; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x153D */ 386 __I uint8_t GPDI61; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x153E */ 387 __I uint8_t GPDI60; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x153F */ 388 __I uint8_t GPDI67; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1540 */ 389 __I uint8_t GPDI66; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1541 */ 390 __I uint8_t GPDI65; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1542 */ 391 __I uint8_t GPDI64; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1543 */ 392 __I uint8_t GPDI71; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1544 */ 393 __I uint8_t GPDI70; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1545 */ 394 __I uint8_t GPDI69; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1546 */ 395 __I uint8_t GPDI68; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1547 */ 396 __I uint8_t GPDI75; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1548 */ 397 __I uint8_t GPDI74; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1549 */ 398 __I uint8_t GPDI73; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x154A */ 399 __I uint8_t GPDI72; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x154B */ 400 __I uint8_t GPDI79; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x154C */ 401 __I uint8_t GPDI78; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x154D */ 402 __I uint8_t GPDI77; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x154E */ 403 __I uint8_t GPDI76; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x154F */ 404 __I uint8_t GPDI83; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1550 */ 405 __I uint8_t GPDI82; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1551 */ 406 __I uint8_t GPDI81; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1552 */ 407 __I uint8_t GPDI80; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1553 */ 408 __I uint8_t GPDI87; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1554 */ 409 __I uint8_t GPDI86; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1555 */ 410 __I uint8_t GPDI85; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1556 */ 411 __I uint8_t GPDI84; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1557 */ 412 __I uint8_t GPDI91; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1558 */ 413 __I uint8_t GPDI90; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1559 */ 414 __I uint8_t GPDI89; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x155A */ 415 __I uint8_t GPDI88; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x155B */ 416 __I uint8_t GPDI95; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x155C */ 417 __I uint8_t GPDI94; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x155D */ 418 __I uint8_t GPDI93; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x155E */ 419 __I uint8_t GPDI92; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x155F */ 420 __I uint8_t GPDI99; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1560 */ 421 __I uint8_t GPDI98; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1561 */ 422 __I uint8_t GPDI97; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1562 */ 423 __I uint8_t GPDI96; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1563 */ 424 __I uint8_t GPDI103; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1564 */ 425 __I uint8_t GPDI102; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1565 */ 426 __I uint8_t GPDI101; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1566 */ 427 __I uint8_t GPDI100; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1567 */ 428 __I uint8_t GPDI107; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1568 */ 429 __I uint8_t GPDI106; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1569 */ 430 __I uint8_t GPDI105; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x156A */ 431 __I uint8_t GPDI104; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x156B */ 432 __I uint8_t GPDI111; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x156C */ 433 __I uint8_t GPDI110; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x156D */ 434 __I uint8_t GPDI109; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x156E */ 435 __I uint8_t GPDI108; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x156F */ 436 __I uint8_t GPDI115; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1570 */ 437 __I uint8_t GPDI114; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1571 */ 438 __I uint8_t GPDI113; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1572 */ 439 __I uint8_t GPDI112; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1573 */ 440 __I uint8_t GPDI119; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1574 */ 441 __I uint8_t GPDI118; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1575 */ 442 __I uint8_t GPDI117; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1576 */ 443 __I uint8_t GPDI116; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1577 */ 444 __I uint8_t GPDI123; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1578 */ 445 __I uint8_t GPDI122; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1579 */ 446 __I uint8_t GPDI121; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x157A */ 447 __I uint8_t GPDI120; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x157B */ 448 __I uint8_t GPDI127; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x157C */ 449 __I uint8_t GPDI126; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x157D */ 450 __I uint8_t GPDI125; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x157E */ 451 __I uint8_t GPDI124; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x157F */ 452 __I uint8_t GPDI131; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1580 */ 453 __I uint8_t GPDI130; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1581 */ 454 __I uint8_t GPDI129; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1582 */ 455 __I uint8_t GPDI128; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1583 */ 456 __I uint8_t GPDI135; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1584 */ 457 __I uint8_t GPDI134; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1585 */ 458 __I uint8_t GPDI133; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1586 */ 459 __I uint8_t GPDI132; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1587 */ 460 __I uint8_t GPDI139; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1588 */ 461 __I uint8_t GPDI138; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1589 */ 462 __I uint8_t GPDI137; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x158A */ 463 __I uint8_t GPDI136; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x158B */ 464 __I uint8_t GPDI143; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x158C */ 465 __I uint8_t GPDI142; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x158D */ 466 __I uint8_t GPDI141; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x158E */ 467 __I uint8_t GPDI140; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x158F */ 468 __I uint8_t GPDI147; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1590 */ 469 __I uint8_t GPDI146; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1591 */ 470 __I uint8_t GPDI145; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1592 */ 471 __I uint8_t GPDI144; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1593 */ 472 __I uint8_t GPDI151; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1594 */ 473 __I uint8_t GPDI150; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1595 */ 474 __I uint8_t GPDI149; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1596 */ 475 __I uint8_t GPDI148; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1597 */ 476 __I uint8_t GPDI155; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1598 */ 477 __I uint8_t GPDI154; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1599 */ 478 __I uint8_t GPDI153; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x159A */ 479 __I uint8_t GPDI152; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x159B */ 480 __I uint8_t GPDI159; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x159C */ 481 __I uint8_t GPDI158; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x159D */ 482 __I uint8_t GPDI157; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x159E */ 483 __I uint8_t GPDI156; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x159F */ 484 __I uint8_t GPDI163; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15A0 */ 485 __I uint8_t GPDI162; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15A1 */ 486 __I uint8_t GPDI161; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15A2 */ 487 __I uint8_t GPDI160; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15A3 */ 488 __I uint8_t GPDI167; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15A4 */ 489 __I uint8_t GPDI166; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15A5 */ 490 __I uint8_t GPDI165; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15A6 */ 491 __I uint8_t GPDI164; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15A7 */ 492 __I uint8_t GPDI171; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15A8 */ 493 __I uint8_t GPDI170; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15A9 */ 494 __I uint8_t GPDI169; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15AA */ 495 __I uint8_t GPDI168; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15AB */ 496 __I uint8_t GPDI175; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15AC */ 497 __I uint8_t GPDI174; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15AD */ 498 __I uint8_t GPDI173; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15AE */ 499 __I uint8_t GPDI172; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15AF */ 500 __I uint8_t GPDI179; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15B0 */ 501 __I uint8_t GPDI178; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15B1 */ 502 __I uint8_t GPDI177; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15B2 */ 503 __I uint8_t GPDI176; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15B3 */ 504 __I uint8_t GPDI183; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15B4 */ 505 __I uint8_t GPDI182; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15B5 */ 506 __I uint8_t GPDI181; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15B6 */ 507 __I uint8_t GPDI180; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15B7 */ 508 __I uint8_t GPDI187; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15B8 */ 509 __I uint8_t GPDI186; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15B9 */ 510 __I uint8_t GPDI185; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15BA */ 511 __I uint8_t GPDI184; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15BB */ 512 __I uint8_t GPDI191; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15BC */ 513 __I uint8_t GPDI190; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15BD */ 514 __I uint8_t GPDI189; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15BE */ 515 __I uint8_t GPDI188; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15BF */ 516 __I uint8_t GPDI195; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15C0 */ 517 __I uint8_t GPDI194; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15C1 */ 518 __I uint8_t GPDI193; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15C2 */ 519 __I uint8_t GPDI192; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15C3 */ 520 __I uint8_t GPDI199; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15C4 */ 521 __I uint8_t GPDI198; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15C5 */ 522 __I uint8_t GPDI197; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15C6 */ 523 __I uint8_t GPDI196; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15C7 */ 524 __I uint8_t GPDI203; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15C8 */ 525 __I uint8_t GPDI202; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15C9 */ 526 __I uint8_t GPDI201; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15CA */ 527 __I uint8_t GPDI200; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15CB */ 528 __I uint8_t GPDI207; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15CC */ 529 __I uint8_t GPDI206; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15CD */ 530 __I uint8_t GPDI205; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15CE */ 531 __I uint8_t GPDI204; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15CF */ 532 __I uint8_t GPDI211; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15D0 */ 533 __I uint8_t GPDI210; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15D1 */ 534 __I uint8_t GPDI209; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15D2 */ 535 __I uint8_t GPDI208; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15D3 */ 536 __I uint8_t GPDI215; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15D4 */ 537 __I uint8_t GPDI214; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15D5 */ 538 __I uint8_t GPDI213; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15D6 */ 539 __I uint8_t GPDI212; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15D7 */ 540 __I uint8_t GPDI219; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15D8 */ 541 __I uint8_t GPDI218; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15D9 */ 542 __I uint8_t GPDI217; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15DA */ 543 __I uint8_t GPDI216; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15DB */ 544 uint8_t RESERVED_15[292]; 545 __IO uint16_t PGPDO1; /**< SIUL2 Parallel GPIO Pad Data Out Register, offset: 0x1700 */ 546 __IO uint16_t PGPDO0; /**< SIUL2 Parallel GPIO Pad Data Out Register, offset: 0x1702 */ 547 __IO uint16_t PGPDO3; /**< SIUL2 Parallel GPIO Pad Data Out Register, offset: 0x1704 */ 548 __IO uint16_t PGPDO2; /**< SIUL2 Parallel GPIO Pad Data Out Register, offset: 0x1706 */ 549 __IO uint16_t PGPDO5; /**< SIUL2 Parallel GPIO Pad Data Out Register, offset: 0x1708 */ 550 __IO uint16_t PGPDO4; /**< SIUL2 Parallel GPIO Pad Data Out Register, offset: 0x170A */ 551 __IO uint16_t PGPDO7; /**< SIUL2 Parallel GPIO Pad Data Out Register, offset: 0x170C */ 552 __IO uint16_t PGPDO6; /**< SIUL2 Parallel GPIO Pad Data Out Register, offset: 0x170E */ 553 __IO uint16_t PGPDO9; /**< SIUL2 Parallel GPIO Pad Data Out Register, offset: 0x1710 */ 554 __IO uint16_t PGPDO8; /**< SIUL2 Parallel GPIO Pad Data Out Register, offset: 0x1712 */ 555 __IO uint16_t PGPDO11; /**< SIUL2 Parallel GPIO Pad Data Out Register, offset: 0x1714 */ 556 __IO uint16_t PGPDO10; /**< SIUL2 Parallel GPIO Pad Data Out Register, offset: 0x1716 */ 557 __IO uint16_t PGPDO13; /**< SIUL2 Parallel GPIO Pad Data Out Register, offset: 0x1718 */ 558 __IO uint16_t PGPDO12; /**< SIUL2 Parallel GPIO Pad Data Out Register, offset: 0x171A */ 559 uint8_t RESERVED_16[36]; 560 __I uint16_t PGPDI1; /**< SIUL2 Parallel GPIO Pad Data In Register, offset: 0x1740 */ 561 __I uint16_t PGPDI0; /**< SIUL2 Parallel GPIO Pad Data In Register, offset: 0x1742 */ 562 __I uint16_t PGPDI3; /**< SIUL2 Parallel GPIO Pad Data In Register, offset: 0x1744 */ 563 __I uint16_t PGPDI2; /**< SIUL2 Parallel GPIO Pad Data In Register, offset: 0x1746 */ 564 __I uint16_t PGPDI5; /**< SIUL2 Parallel GPIO Pad Data In Register, offset: 0x1748 */ 565 __I uint16_t PGPDI4; /**< SIUL2 Parallel GPIO Pad Data In Register, offset: 0x174A */ 566 __I uint16_t PGPDI7; /**< SIUL2 Parallel GPIO Pad Data In Register, offset: 0x174C */ 567 __I uint16_t PGPDI6; /**< SIUL2 Parallel GPIO Pad Data In Register, offset: 0x174E */ 568 __I uint16_t PGPDI9; /**< SIUL2 Parallel GPIO Pad Data In Register, offset: 0x1750 */ 569 __I uint16_t PGPDI8; /**< SIUL2 Parallel GPIO Pad Data In Register, offset: 0x1752 */ 570 __I uint16_t PGPDI11; /**< SIUL2 Parallel GPIO Pad Data In Register, offset: 0x1754 */ 571 __I uint16_t PGPDI10; /**< SIUL2 Parallel GPIO Pad Data In Register, offset: 0x1756 */ 572 __I uint16_t PGPDI13; /**< SIUL2 Parallel GPIO Pad Data In Register, offset: 0x1758 */ 573 __I uint16_t PGPDI12; /**< SIUL2 Parallel GPIO Pad Data In Register, offset: 0x175A */ 574 uint8_t RESERVED_17[36]; 575 __O uint32_t MPGPDO[SIUL2_MPGPDO_COUNT]; /**< SIUL2 Masked Parallel GPIO Pad Data Out Register, array offset: 0x1780, array step: 0x4 */ 576 } SIUL2_Type, *SIUL2_MemMapPtr; 577 578 /** Number of instances of the SIUL2 module. */ 579 #define SIUL2_INSTANCE_COUNT (1) 580 581 /* SIUL2 - Peripheral instance base addresses */ 582 /** Peripheral SIUL2 base address */ 583 #define IP_SIUL2_BASE (0x40290000u) 584 /** Peripheral SIUL2 base pointer */ 585 #define IP_SIUL2 ((SIUL2_Type *)IP_SIUL2_BASE) 586 /** Array initializer of SIUL2 peripheral base addresses */ 587 #define IP_SIUL2_BASE_ADDRS { IP_SIUL2_BASE } 588 /** Array initializer of SIUL2 peripheral base pointers */ 589 #define IP_SIUL2_BASE_PTRS { IP_SIUL2 } 590 591 /* ---------------------------------------------------------------------------- 592 -- SIUL2 Register Masks 593 ---------------------------------------------------------------------------- */ 594 595 /*! 596 * @addtogroup SIUL2_Register_Masks SIUL2 Register Masks 597 * @{ 598 */ 599 600 /*! @name MIDR1 - SIUL2 MCU ID Register #1 */ 601 /*! @{ */ 602 603 #define SIUL2_MIDR1_MINOR_MASK_MASK (0xFU) 604 #define SIUL2_MIDR1_MINOR_MASK_SHIFT (0U) 605 #define SIUL2_MIDR1_MINOR_MASK_WIDTH (4U) 606 #define SIUL2_MIDR1_MINOR_MASK(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MIDR1_MINOR_MASK_SHIFT)) & SIUL2_MIDR1_MINOR_MASK_MASK) 607 608 #define SIUL2_MIDR1_MAJOR_MASK_MASK (0xF0U) 609 #define SIUL2_MIDR1_MAJOR_MASK_SHIFT (4U) 610 #define SIUL2_MIDR1_MAJOR_MASK_WIDTH (4U) 611 #define SIUL2_MIDR1_MAJOR_MASK(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MIDR1_MAJOR_MASK_SHIFT)) & SIUL2_MIDR1_MAJOR_MASK_MASK) 612 613 #define SIUL2_MIDR1_PART_NO_MASK (0x3FF0000U) 614 #define SIUL2_MIDR1_PART_NO_SHIFT (16U) 615 #define SIUL2_MIDR1_PART_NO_WIDTH (10U) 616 #define SIUL2_MIDR1_PART_NO(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MIDR1_PART_NO_SHIFT)) & SIUL2_MIDR1_PART_NO_MASK) 617 618 #define SIUL2_MIDR1_PRODUCT_LINE_LETTER_MASK (0xFC000000U) 619 #define SIUL2_MIDR1_PRODUCT_LINE_LETTER_SHIFT (26U) 620 #define SIUL2_MIDR1_PRODUCT_LINE_LETTER_WIDTH (6U) 621 #define SIUL2_MIDR1_PRODUCT_LINE_LETTER(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MIDR1_PRODUCT_LINE_LETTER_SHIFT)) & SIUL2_MIDR1_PRODUCT_LINE_LETTER_MASK) 622 /*! @} */ 623 624 /*! @name MIDR2 - SIUL2 MCU ID Register #2 */ 625 /*! @{ */ 626 627 #define SIUL2_MIDR2_FLASH_SIZE_CODE_MASK (0xFFU) 628 #define SIUL2_MIDR2_FLASH_SIZE_CODE_SHIFT (0U) 629 #define SIUL2_MIDR2_FLASH_SIZE_CODE_WIDTH (8U) 630 #define SIUL2_MIDR2_FLASH_SIZE_CODE(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MIDR2_FLASH_SIZE_CODE_SHIFT)) & SIUL2_MIDR2_FLASH_SIZE_CODE_MASK) 631 632 #define SIUL2_MIDR2_FLASH_SIZE_DATA_MASK (0xF00U) 633 #define SIUL2_MIDR2_FLASH_SIZE_DATA_SHIFT (8U) 634 #define SIUL2_MIDR2_FLASH_SIZE_DATA_WIDTH (4U) 635 #define SIUL2_MIDR2_FLASH_SIZE_DATA(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MIDR2_FLASH_SIZE_DATA_SHIFT)) & SIUL2_MIDR2_FLASH_SIZE_DATA_MASK) 636 637 #define SIUL2_MIDR2_FLASH_DATA_MASK (0x3000U) 638 #define SIUL2_MIDR2_FLASH_DATA_SHIFT (12U) 639 #define SIUL2_MIDR2_FLASH_DATA_WIDTH (2U) 640 #define SIUL2_MIDR2_FLASH_DATA(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MIDR2_FLASH_DATA_SHIFT)) & SIUL2_MIDR2_FLASH_DATA_MASK) 641 642 #define SIUL2_MIDR2_FLASH_CODE_MASK (0xC000U) 643 #define SIUL2_MIDR2_FLASH_CODE_SHIFT (14U) 644 #define SIUL2_MIDR2_FLASH_CODE_WIDTH (2U) 645 #define SIUL2_MIDR2_FLASH_CODE(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MIDR2_FLASH_CODE_SHIFT)) & SIUL2_MIDR2_FLASH_CODE_MASK) 646 647 #define SIUL2_MIDR2_FREQUENCY_MASK (0xF0000U) 648 #define SIUL2_MIDR2_FREQUENCY_SHIFT (16U) 649 #define SIUL2_MIDR2_FREQUENCY_WIDTH (4U) 650 #define SIUL2_MIDR2_FREQUENCY(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MIDR2_FREQUENCY_SHIFT)) & SIUL2_MIDR2_FREQUENCY_MASK) 651 652 #define SIUL2_MIDR2_PACKAGE_MASK (0x3F00000U) 653 #define SIUL2_MIDR2_PACKAGE_SHIFT (20U) 654 #define SIUL2_MIDR2_PACKAGE_WIDTH (6U) 655 #define SIUL2_MIDR2_PACKAGE(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MIDR2_PACKAGE_SHIFT)) & SIUL2_MIDR2_PACKAGE_MASK) 656 657 #define SIUL2_MIDR2_TEMPERATURE_MASK (0x1C000000U) 658 #define SIUL2_MIDR2_TEMPERATURE_SHIFT (26U) 659 #define SIUL2_MIDR2_TEMPERATURE_WIDTH (3U) 660 #define SIUL2_MIDR2_TEMPERATURE(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MIDR2_TEMPERATURE_SHIFT)) & SIUL2_MIDR2_TEMPERATURE_MASK) 661 662 #define SIUL2_MIDR2_TECHNOLOGY_MASK (0xE0000000U) 663 #define SIUL2_MIDR2_TECHNOLOGY_SHIFT (29U) 664 #define SIUL2_MIDR2_TECHNOLOGY_WIDTH (3U) 665 #define SIUL2_MIDR2_TECHNOLOGY(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MIDR2_TECHNOLOGY_SHIFT)) & SIUL2_MIDR2_TECHNOLOGY_MASK) 666 /*! @} */ 667 668 /*! @name DISR0 - SIUL2 DMA/Interrupt Status Flag Register0 */ 669 /*! @{ */ 670 671 #define SIUL2_DISR0_EIF0_MASK (0x1U) 672 #define SIUL2_DISR0_EIF0_SHIFT (0U) 673 #define SIUL2_DISR0_EIF0_WIDTH (1U) 674 #define SIUL2_DISR0_EIF0(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DISR0_EIF0_SHIFT)) & SIUL2_DISR0_EIF0_MASK) 675 676 #define SIUL2_DISR0_EIF1_MASK (0x2U) 677 #define SIUL2_DISR0_EIF1_SHIFT (1U) 678 #define SIUL2_DISR0_EIF1_WIDTH (1U) 679 #define SIUL2_DISR0_EIF1(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DISR0_EIF1_SHIFT)) & SIUL2_DISR0_EIF1_MASK) 680 681 #define SIUL2_DISR0_EIF2_MASK (0x4U) 682 #define SIUL2_DISR0_EIF2_SHIFT (2U) 683 #define SIUL2_DISR0_EIF2_WIDTH (1U) 684 #define SIUL2_DISR0_EIF2(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DISR0_EIF2_SHIFT)) & SIUL2_DISR0_EIF2_MASK) 685 686 #define SIUL2_DISR0_EIF3_MASK (0x8U) 687 #define SIUL2_DISR0_EIF3_SHIFT (3U) 688 #define SIUL2_DISR0_EIF3_WIDTH (1U) 689 #define SIUL2_DISR0_EIF3(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DISR0_EIF3_SHIFT)) & SIUL2_DISR0_EIF3_MASK) 690 691 #define SIUL2_DISR0_EIF4_MASK (0x10U) 692 #define SIUL2_DISR0_EIF4_SHIFT (4U) 693 #define SIUL2_DISR0_EIF4_WIDTH (1U) 694 #define SIUL2_DISR0_EIF4(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DISR0_EIF4_SHIFT)) & SIUL2_DISR0_EIF4_MASK) 695 696 #define SIUL2_DISR0_EIF5_MASK (0x20U) 697 #define SIUL2_DISR0_EIF5_SHIFT (5U) 698 #define SIUL2_DISR0_EIF5_WIDTH (1U) 699 #define SIUL2_DISR0_EIF5(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DISR0_EIF5_SHIFT)) & SIUL2_DISR0_EIF5_MASK) 700 701 #define SIUL2_DISR0_EIF6_MASK (0x40U) 702 #define SIUL2_DISR0_EIF6_SHIFT (6U) 703 #define SIUL2_DISR0_EIF6_WIDTH (1U) 704 #define SIUL2_DISR0_EIF6(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DISR0_EIF6_SHIFT)) & SIUL2_DISR0_EIF6_MASK) 705 706 #define SIUL2_DISR0_EIF7_MASK (0x80U) 707 #define SIUL2_DISR0_EIF7_SHIFT (7U) 708 #define SIUL2_DISR0_EIF7_WIDTH (1U) 709 #define SIUL2_DISR0_EIF7(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DISR0_EIF7_SHIFT)) & SIUL2_DISR0_EIF7_MASK) 710 711 #define SIUL2_DISR0_EIF8_MASK (0x100U) 712 #define SIUL2_DISR0_EIF8_SHIFT (8U) 713 #define SIUL2_DISR0_EIF8_WIDTH (1U) 714 #define SIUL2_DISR0_EIF8(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DISR0_EIF8_SHIFT)) & SIUL2_DISR0_EIF8_MASK) 715 716 #define SIUL2_DISR0_EIF9_MASK (0x200U) 717 #define SIUL2_DISR0_EIF9_SHIFT (9U) 718 #define SIUL2_DISR0_EIF9_WIDTH (1U) 719 #define SIUL2_DISR0_EIF9(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DISR0_EIF9_SHIFT)) & SIUL2_DISR0_EIF9_MASK) 720 721 #define SIUL2_DISR0_EIF10_MASK (0x400U) 722 #define SIUL2_DISR0_EIF10_SHIFT (10U) 723 #define SIUL2_DISR0_EIF10_WIDTH (1U) 724 #define SIUL2_DISR0_EIF10(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DISR0_EIF10_SHIFT)) & SIUL2_DISR0_EIF10_MASK) 725 726 #define SIUL2_DISR0_EIF11_MASK (0x800U) 727 #define SIUL2_DISR0_EIF11_SHIFT (11U) 728 #define SIUL2_DISR0_EIF11_WIDTH (1U) 729 #define SIUL2_DISR0_EIF11(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DISR0_EIF11_SHIFT)) & SIUL2_DISR0_EIF11_MASK) 730 731 #define SIUL2_DISR0_EIF12_MASK (0x1000U) 732 #define SIUL2_DISR0_EIF12_SHIFT (12U) 733 #define SIUL2_DISR0_EIF12_WIDTH (1U) 734 #define SIUL2_DISR0_EIF12(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DISR0_EIF12_SHIFT)) & SIUL2_DISR0_EIF12_MASK) 735 736 #define SIUL2_DISR0_EIF13_MASK (0x2000U) 737 #define SIUL2_DISR0_EIF13_SHIFT (13U) 738 #define SIUL2_DISR0_EIF13_WIDTH (1U) 739 #define SIUL2_DISR0_EIF13(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DISR0_EIF13_SHIFT)) & SIUL2_DISR0_EIF13_MASK) 740 741 #define SIUL2_DISR0_EIF14_MASK (0x4000U) 742 #define SIUL2_DISR0_EIF14_SHIFT (14U) 743 #define SIUL2_DISR0_EIF14_WIDTH (1U) 744 #define SIUL2_DISR0_EIF14(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DISR0_EIF14_SHIFT)) & SIUL2_DISR0_EIF14_MASK) 745 746 #define SIUL2_DISR0_EIF15_MASK (0x8000U) 747 #define SIUL2_DISR0_EIF15_SHIFT (15U) 748 #define SIUL2_DISR0_EIF15_WIDTH (1U) 749 #define SIUL2_DISR0_EIF15(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DISR0_EIF15_SHIFT)) & SIUL2_DISR0_EIF15_MASK) 750 751 #define SIUL2_DISR0_EIF16_MASK (0x10000U) 752 #define SIUL2_DISR0_EIF16_SHIFT (16U) 753 #define SIUL2_DISR0_EIF16_WIDTH (1U) 754 #define SIUL2_DISR0_EIF16(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DISR0_EIF16_SHIFT)) & SIUL2_DISR0_EIF16_MASK) 755 756 #define SIUL2_DISR0_EIF17_MASK (0x20000U) 757 #define SIUL2_DISR0_EIF17_SHIFT (17U) 758 #define SIUL2_DISR0_EIF17_WIDTH (1U) 759 #define SIUL2_DISR0_EIF17(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DISR0_EIF17_SHIFT)) & SIUL2_DISR0_EIF17_MASK) 760 761 #define SIUL2_DISR0_EIF18_MASK (0x40000U) 762 #define SIUL2_DISR0_EIF18_SHIFT (18U) 763 #define SIUL2_DISR0_EIF18_WIDTH (1U) 764 #define SIUL2_DISR0_EIF18(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DISR0_EIF18_SHIFT)) & SIUL2_DISR0_EIF18_MASK) 765 766 #define SIUL2_DISR0_EIF19_MASK (0x80000U) 767 #define SIUL2_DISR0_EIF19_SHIFT (19U) 768 #define SIUL2_DISR0_EIF19_WIDTH (1U) 769 #define SIUL2_DISR0_EIF19(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DISR0_EIF19_SHIFT)) & SIUL2_DISR0_EIF19_MASK) 770 771 #define SIUL2_DISR0_EIF20_MASK (0x100000U) 772 #define SIUL2_DISR0_EIF20_SHIFT (20U) 773 #define SIUL2_DISR0_EIF20_WIDTH (1U) 774 #define SIUL2_DISR0_EIF20(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DISR0_EIF20_SHIFT)) & SIUL2_DISR0_EIF20_MASK) 775 776 #define SIUL2_DISR0_EIF21_MASK (0x200000U) 777 #define SIUL2_DISR0_EIF21_SHIFT (21U) 778 #define SIUL2_DISR0_EIF21_WIDTH (1U) 779 #define SIUL2_DISR0_EIF21(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DISR0_EIF21_SHIFT)) & SIUL2_DISR0_EIF21_MASK) 780 781 #define SIUL2_DISR0_EIF22_MASK (0x400000U) 782 #define SIUL2_DISR0_EIF22_SHIFT (22U) 783 #define SIUL2_DISR0_EIF22_WIDTH (1U) 784 #define SIUL2_DISR0_EIF22(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DISR0_EIF22_SHIFT)) & SIUL2_DISR0_EIF22_MASK) 785 786 #define SIUL2_DISR0_EIF23_MASK (0x800000U) 787 #define SIUL2_DISR0_EIF23_SHIFT (23U) 788 #define SIUL2_DISR0_EIF23_WIDTH (1U) 789 #define SIUL2_DISR0_EIF23(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DISR0_EIF23_SHIFT)) & SIUL2_DISR0_EIF23_MASK) 790 791 #define SIUL2_DISR0_EIF24_MASK (0x1000000U) 792 #define SIUL2_DISR0_EIF24_SHIFT (24U) 793 #define SIUL2_DISR0_EIF24_WIDTH (1U) 794 #define SIUL2_DISR0_EIF24(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DISR0_EIF24_SHIFT)) & SIUL2_DISR0_EIF24_MASK) 795 796 #define SIUL2_DISR0_EIF25_MASK (0x2000000U) 797 #define SIUL2_DISR0_EIF25_SHIFT (25U) 798 #define SIUL2_DISR0_EIF25_WIDTH (1U) 799 #define SIUL2_DISR0_EIF25(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DISR0_EIF25_SHIFT)) & SIUL2_DISR0_EIF25_MASK) 800 801 #define SIUL2_DISR0_EIF26_MASK (0x4000000U) 802 #define SIUL2_DISR0_EIF26_SHIFT (26U) 803 #define SIUL2_DISR0_EIF26_WIDTH (1U) 804 #define SIUL2_DISR0_EIF26(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DISR0_EIF26_SHIFT)) & SIUL2_DISR0_EIF26_MASK) 805 806 #define SIUL2_DISR0_EIF27_MASK (0x8000000U) 807 #define SIUL2_DISR0_EIF27_SHIFT (27U) 808 #define SIUL2_DISR0_EIF27_WIDTH (1U) 809 #define SIUL2_DISR0_EIF27(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DISR0_EIF27_SHIFT)) & SIUL2_DISR0_EIF27_MASK) 810 811 #define SIUL2_DISR0_EIF28_MASK (0x10000000U) 812 #define SIUL2_DISR0_EIF28_SHIFT (28U) 813 #define SIUL2_DISR0_EIF28_WIDTH (1U) 814 #define SIUL2_DISR0_EIF28(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DISR0_EIF28_SHIFT)) & SIUL2_DISR0_EIF28_MASK) 815 816 #define SIUL2_DISR0_EIF29_MASK (0x20000000U) 817 #define SIUL2_DISR0_EIF29_SHIFT (29U) 818 #define SIUL2_DISR0_EIF29_WIDTH (1U) 819 #define SIUL2_DISR0_EIF29(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DISR0_EIF29_SHIFT)) & SIUL2_DISR0_EIF29_MASK) 820 821 #define SIUL2_DISR0_EIF30_MASK (0x40000000U) 822 #define SIUL2_DISR0_EIF30_SHIFT (30U) 823 #define SIUL2_DISR0_EIF30_WIDTH (1U) 824 #define SIUL2_DISR0_EIF30(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DISR0_EIF30_SHIFT)) & SIUL2_DISR0_EIF30_MASK) 825 826 #define SIUL2_DISR0_EIF31_MASK (0x80000000U) 827 #define SIUL2_DISR0_EIF31_SHIFT (31U) 828 #define SIUL2_DISR0_EIF31_WIDTH (1U) 829 #define SIUL2_DISR0_EIF31(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DISR0_EIF31_SHIFT)) & SIUL2_DISR0_EIF31_MASK) 830 /*! @} */ 831 832 /*! @name DIRER0 - SIUL2 DMA/Interrupt Request Enable Register0 */ 833 /*! @{ */ 834 835 #define SIUL2_DIRER0_EIRE0_MASK (0x1U) 836 #define SIUL2_DIRER0_EIRE0_SHIFT (0U) 837 #define SIUL2_DIRER0_EIRE0_WIDTH (1U) 838 #define SIUL2_DIRER0_EIRE0(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRER0_EIRE0_SHIFT)) & SIUL2_DIRER0_EIRE0_MASK) 839 840 #define SIUL2_DIRER0_EIRE1_MASK (0x2U) 841 #define SIUL2_DIRER0_EIRE1_SHIFT (1U) 842 #define SIUL2_DIRER0_EIRE1_WIDTH (1U) 843 #define SIUL2_DIRER0_EIRE1(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRER0_EIRE1_SHIFT)) & SIUL2_DIRER0_EIRE1_MASK) 844 845 #define SIUL2_DIRER0_EIRE2_MASK (0x4U) 846 #define SIUL2_DIRER0_EIRE2_SHIFT (2U) 847 #define SIUL2_DIRER0_EIRE2_WIDTH (1U) 848 #define SIUL2_DIRER0_EIRE2(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRER0_EIRE2_SHIFT)) & SIUL2_DIRER0_EIRE2_MASK) 849 850 #define SIUL2_DIRER0_EIRE3_MASK (0x8U) 851 #define SIUL2_DIRER0_EIRE3_SHIFT (3U) 852 #define SIUL2_DIRER0_EIRE3_WIDTH (1U) 853 #define SIUL2_DIRER0_EIRE3(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRER0_EIRE3_SHIFT)) & SIUL2_DIRER0_EIRE3_MASK) 854 855 #define SIUL2_DIRER0_EIRE4_MASK (0x10U) 856 #define SIUL2_DIRER0_EIRE4_SHIFT (4U) 857 #define SIUL2_DIRER0_EIRE4_WIDTH (1U) 858 #define SIUL2_DIRER0_EIRE4(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRER0_EIRE4_SHIFT)) & SIUL2_DIRER0_EIRE4_MASK) 859 860 #define SIUL2_DIRER0_EIRE5_MASK (0x20U) 861 #define SIUL2_DIRER0_EIRE5_SHIFT (5U) 862 #define SIUL2_DIRER0_EIRE5_WIDTH (1U) 863 #define SIUL2_DIRER0_EIRE5(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRER0_EIRE5_SHIFT)) & SIUL2_DIRER0_EIRE5_MASK) 864 865 #define SIUL2_DIRER0_EIRE6_MASK (0x40U) 866 #define SIUL2_DIRER0_EIRE6_SHIFT (6U) 867 #define SIUL2_DIRER0_EIRE6_WIDTH (1U) 868 #define SIUL2_DIRER0_EIRE6(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRER0_EIRE6_SHIFT)) & SIUL2_DIRER0_EIRE6_MASK) 869 870 #define SIUL2_DIRER0_EIRE7_MASK (0x80U) 871 #define SIUL2_DIRER0_EIRE7_SHIFT (7U) 872 #define SIUL2_DIRER0_EIRE7_WIDTH (1U) 873 #define SIUL2_DIRER0_EIRE7(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRER0_EIRE7_SHIFT)) & SIUL2_DIRER0_EIRE7_MASK) 874 875 #define SIUL2_DIRER0_EIRE8_MASK (0x100U) 876 #define SIUL2_DIRER0_EIRE8_SHIFT (8U) 877 #define SIUL2_DIRER0_EIRE8_WIDTH (1U) 878 #define SIUL2_DIRER0_EIRE8(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRER0_EIRE8_SHIFT)) & SIUL2_DIRER0_EIRE8_MASK) 879 880 #define SIUL2_DIRER0_EIRE9_MASK (0x200U) 881 #define SIUL2_DIRER0_EIRE9_SHIFT (9U) 882 #define SIUL2_DIRER0_EIRE9_WIDTH (1U) 883 #define SIUL2_DIRER0_EIRE9(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRER0_EIRE9_SHIFT)) & SIUL2_DIRER0_EIRE9_MASK) 884 885 #define SIUL2_DIRER0_EIRE10_MASK (0x400U) 886 #define SIUL2_DIRER0_EIRE10_SHIFT (10U) 887 #define SIUL2_DIRER0_EIRE10_WIDTH (1U) 888 #define SIUL2_DIRER0_EIRE10(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRER0_EIRE10_SHIFT)) & SIUL2_DIRER0_EIRE10_MASK) 889 890 #define SIUL2_DIRER0_EIRE11_MASK (0x800U) 891 #define SIUL2_DIRER0_EIRE11_SHIFT (11U) 892 #define SIUL2_DIRER0_EIRE11_WIDTH (1U) 893 #define SIUL2_DIRER0_EIRE11(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRER0_EIRE11_SHIFT)) & SIUL2_DIRER0_EIRE11_MASK) 894 895 #define SIUL2_DIRER0_EIRE12_MASK (0x1000U) 896 #define SIUL2_DIRER0_EIRE12_SHIFT (12U) 897 #define SIUL2_DIRER0_EIRE12_WIDTH (1U) 898 #define SIUL2_DIRER0_EIRE12(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRER0_EIRE12_SHIFT)) & SIUL2_DIRER0_EIRE12_MASK) 899 900 #define SIUL2_DIRER0_EIRE13_MASK (0x2000U) 901 #define SIUL2_DIRER0_EIRE13_SHIFT (13U) 902 #define SIUL2_DIRER0_EIRE13_WIDTH (1U) 903 #define SIUL2_DIRER0_EIRE13(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRER0_EIRE13_SHIFT)) & SIUL2_DIRER0_EIRE13_MASK) 904 905 #define SIUL2_DIRER0_EIRE14_MASK (0x4000U) 906 #define SIUL2_DIRER0_EIRE14_SHIFT (14U) 907 #define SIUL2_DIRER0_EIRE14_WIDTH (1U) 908 #define SIUL2_DIRER0_EIRE14(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRER0_EIRE14_SHIFT)) & SIUL2_DIRER0_EIRE14_MASK) 909 910 #define SIUL2_DIRER0_EIRE15_MASK (0x8000U) 911 #define SIUL2_DIRER0_EIRE15_SHIFT (15U) 912 #define SIUL2_DIRER0_EIRE15_WIDTH (1U) 913 #define SIUL2_DIRER0_EIRE15(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRER0_EIRE15_SHIFT)) & SIUL2_DIRER0_EIRE15_MASK) 914 915 #define SIUL2_DIRER0_EIRE16_MASK (0x10000U) 916 #define SIUL2_DIRER0_EIRE16_SHIFT (16U) 917 #define SIUL2_DIRER0_EIRE16_WIDTH (1U) 918 #define SIUL2_DIRER0_EIRE16(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRER0_EIRE16_SHIFT)) & SIUL2_DIRER0_EIRE16_MASK) 919 920 #define SIUL2_DIRER0_EIRE17_MASK (0x20000U) 921 #define SIUL2_DIRER0_EIRE17_SHIFT (17U) 922 #define SIUL2_DIRER0_EIRE17_WIDTH (1U) 923 #define SIUL2_DIRER0_EIRE17(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRER0_EIRE17_SHIFT)) & SIUL2_DIRER0_EIRE17_MASK) 924 925 #define SIUL2_DIRER0_EIRE18_MASK (0x40000U) 926 #define SIUL2_DIRER0_EIRE18_SHIFT (18U) 927 #define SIUL2_DIRER0_EIRE18_WIDTH (1U) 928 #define SIUL2_DIRER0_EIRE18(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRER0_EIRE18_SHIFT)) & SIUL2_DIRER0_EIRE18_MASK) 929 930 #define SIUL2_DIRER0_EIRE19_MASK (0x80000U) 931 #define SIUL2_DIRER0_EIRE19_SHIFT (19U) 932 #define SIUL2_DIRER0_EIRE19_WIDTH (1U) 933 #define SIUL2_DIRER0_EIRE19(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRER0_EIRE19_SHIFT)) & SIUL2_DIRER0_EIRE19_MASK) 934 935 #define SIUL2_DIRER0_EIRE20_MASK (0x100000U) 936 #define SIUL2_DIRER0_EIRE20_SHIFT (20U) 937 #define SIUL2_DIRER0_EIRE20_WIDTH (1U) 938 #define SIUL2_DIRER0_EIRE20(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRER0_EIRE20_SHIFT)) & SIUL2_DIRER0_EIRE20_MASK) 939 940 #define SIUL2_DIRER0_EIRE21_MASK (0x200000U) 941 #define SIUL2_DIRER0_EIRE21_SHIFT (21U) 942 #define SIUL2_DIRER0_EIRE21_WIDTH (1U) 943 #define SIUL2_DIRER0_EIRE21(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRER0_EIRE21_SHIFT)) & SIUL2_DIRER0_EIRE21_MASK) 944 945 #define SIUL2_DIRER0_EIRE22_MASK (0x400000U) 946 #define SIUL2_DIRER0_EIRE22_SHIFT (22U) 947 #define SIUL2_DIRER0_EIRE22_WIDTH (1U) 948 #define SIUL2_DIRER0_EIRE22(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRER0_EIRE22_SHIFT)) & SIUL2_DIRER0_EIRE22_MASK) 949 950 #define SIUL2_DIRER0_EIRE23_MASK (0x800000U) 951 #define SIUL2_DIRER0_EIRE23_SHIFT (23U) 952 #define SIUL2_DIRER0_EIRE23_WIDTH (1U) 953 #define SIUL2_DIRER0_EIRE23(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRER0_EIRE23_SHIFT)) & SIUL2_DIRER0_EIRE23_MASK) 954 955 #define SIUL2_DIRER0_EIRE24_MASK (0x1000000U) 956 #define SIUL2_DIRER0_EIRE24_SHIFT (24U) 957 #define SIUL2_DIRER0_EIRE24_WIDTH (1U) 958 #define SIUL2_DIRER0_EIRE24(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRER0_EIRE24_SHIFT)) & SIUL2_DIRER0_EIRE24_MASK) 959 960 #define SIUL2_DIRER0_EIRE25_MASK (0x2000000U) 961 #define SIUL2_DIRER0_EIRE25_SHIFT (25U) 962 #define SIUL2_DIRER0_EIRE25_WIDTH (1U) 963 #define SIUL2_DIRER0_EIRE25(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRER0_EIRE25_SHIFT)) & SIUL2_DIRER0_EIRE25_MASK) 964 965 #define SIUL2_DIRER0_EIRE26_MASK (0x4000000U) 966 #define SIUL2_DIRER0_EIRE26_SHIFT (26U) 967 #define SIUL2_DIRER0_EIRE26_WIDTH (1U) 968 #define SIUL2_DIRER0_EIRE26(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRER0_EIRE26_SHIFT)) & SIUL2_DIRER0_EIRE26_MASK) 969 970 #define SIUL2_DIRER0_EIRE27_MASK (0x8000000U) 971 #define SIUL2_DIRER0_EIRE27_SHIFT (27U) 972 #define SIUL2_DIRER0_EIRE27_WIDTH (1U) 973 #define SIUL2_DIRER0_EIRE27(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRER0_EIRE27_SHIFT)) & SIUL2_DIRER0_EIRE27_MASK) 974 975 #define SIUL2_DIRER0_EIRE28_MASK (0x10000000U) 976 #define SIUL2_DIRER0_EIRE28_SHIFT (28U) 977 #define SIUL2_DIRER0_EIRE28_WIDTH (1U) 978 #define SIUL2_DIRER0_EIRE28(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRER0_EIRE28_SHIFT)) & SIUL2_DIRER0_EIRE28_MASK) 979 980 #define SIUL2_DIRER0_EIRE29_MASK (0x20000000U) 981 #define SIUL2_DIRER0_EIRE29_SHIFT (29U) 982 #define SIUL2_DIRER0_EIRE29_WIDTH (1U) 983 #define SIUL2_DIRER0_EIRE29(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRER0_EIRE29_SHIFT)) & SIUL2_DIRER0_EIRE29_MASK) 984 985 #define SIUL2_DIRER0_EIRE30_MASK (0x40000000U) 986 #define SIUL2_DIRER0_EIRE30_SHIFT (30U) 987 #define SIUL2_DIRER0_EIRE30_WIDTH (1U) 988 #define SIUL2_DIRER0_EIRE30(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRER0_EIRE30_SHIFT)) & SIUL2_DIRER0_EIRE30_MASK) 989 990 #define SIUL2_DIRER0_EIRE31_MASK (0x80000000U) 991 #define SIUL2_DIRER0_EIRE31_SHIFT (31U) 992 #define SIUL2_DIRER0_EIRE31_WIDTH (1U) 993 #define SIUL2_DIRER0_EIRE31(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRER0_EIRE31_SHIFT)) & SIUL2_DIRER0_EIRE31_MASK) 994 /*! @} */ 995 996 /*! @name DIRSR0 - SIUL2 DMA/Interrupt Request Select Register0 */ 997 /*! @{ */ 998 999 #define SIUL2_DIRSR0_DIRSR0_MASK (0x1U) 1000 #define SIUL2_DIRSR0_DIRSR0_SHIFT (0U) 1001 #define SIUL2_DIRSR0_DIRSR0_WIDTH (1U) 1002 #define SIUL2_DIRSR0_DIRSR0(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRSR0_DIRSR0_SHIFT)) & SIUL2_DIRSR0_DIRSR0_MASK) 1003 1004 #define SIUL2_DIRSR0_DIRSR1_MASK (0x2U) 1005 #define SIUL2_DIRSR0_DIRSR1_SHIFT (1U) 1006 #define SIUL2_DIRSR0_DIRSR1_WIDTH (1U) 1007 #define SIUL2_DIRSR0_DIRSR1(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRSR0_DIRSR1_SHIFT)) & SIUL2_DIRSR0_DIRSR1_MASK) 1008 1009 #define SIUL2_DIRSR0_DIRSR2_MASK (0x4U) 1010 #define SIUL2_DIRSR0_DIRSR2_SHIFT (2U) 1011 #define SIUL2_DIRSR0_DIRSR2_WIDTH (1U) 1012 #define SIUL2_DIRSR0_DIRSR2(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRSR0_DIRSR2_SHIFT)) & SIUL2_DIRSR0_DIRSR2_MASK) 1013 1014 #define SIUL2_DIRSR0_DIRSR3_MASK (0x8U) 1015 #define SIUL2_DIRSR0_DIRSR3_SHIFT (3U) 1016 #define SIUL2_DIRSR0_DIRSR3_WIDTH (1U) 1017 #define SIUL2_DIRSR0_DIRSR3(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRSR0_DIRSR3_SHIFT)) & SIUL2_DIRSR0_DIRSR3_MASK) 1018 1019 #define SIUL2_DIRSR0_DIRSR4_MASK (0x10U) 1020 #define SIUL2_DIRSR0_DIRSR4_SHIFT (4U) 1021 #define SIUL2_DIRSR0_DIRSR4_WIDTH (1U) 1022 #define SIUL2_DIRSR0_DIRSR4(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRSR0_DIRSR4_SHIFT)) & SIUL2_DIRSR0_DIRSR4_MASK) 1023 1024 #define SIUL2_DIRSR0_DIRSR5_MASK (0x20U) 1025 #define SIUL2_DIRSR0_DIRSR5_SHIFT (5U) 1026 #define SIUL2_DIRSR0_DIRSR5_WIDTH (1U) 1027 #define SIUL2_DIRSR0_DIRSR5(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRSR0_DIRSR5_SHIFT)) & SIUL2_DIRSR0_DIRSR5_MASK) 1028 1029 #define SIUL2_DIRSR0_DIRSR6_MASK (0x40U) 1030 #define SIUL2_DIRSR0_DIRSR6_SHIFT (6U) 1031 #define SIUL2_DIRSR0_DIRSR6_WIDTH (1U) 1032 #define SIUL2_DIRSR0_DIRSR6(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRSR0_DIRSR6_SHIFT)) & SIUL2_DIRSR0_DIRSR6_MASK) 1033 1034 #define SIUL2_DIRSR0_DIRSR7_MASK (0x80U) 1035 #define SIUL2_DIRSR0_DIRSR7_SHIFT (7U) 1036 #define SIUL2_DIRSR0_DIRSR7_WIDTH (1U) 1037 #define SIUL2_DIRSR0_DIRSR7(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRSR0_DIRSR7_SHIFT)) & SIUL2_DIRSR0_DIRSR7_MASK) 1038 1039 #define SIUL2_DIRSR0_DIRSR8_MASK (0x100U) 1040 #define SIUL2_DIRSR0_DIRSR8_SHIFT (8U) 1041 #define SIUL2_DIRSR0_DIRSR8_WIDTH (1U) 1042 #define SIUL2_DIRSR0_DIRSR8(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRSR0_DIRSR8_SHIFT)) & SIUL2_DIRSR0_DIRSR8_MASK) 1043 1044 #define SIUL2_DIRSR0_DIRSR9_MASK (0x200U) 1045 #define SIUL2_DIRSR0_DIRSR9_SHIFT (9U) 1046 #define SIUL2_DIRSR0_DIRSR9_WIDTH (1U) 1047 #define SIUL2_DIRSR0_DIRSR9(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRSR0_DIRSR9_SHIFT)) & SIUL2_DIRSR0_DIRSR9_MASK) 1048 1049 #define SIUL2_DIRSR0_DIRSR10_MASK (0x400U) 1050 #define SIUL2_DIRSR0_DIRSR10_SHIFT (10U) 1051 #define SIUL2_DIRSR0_DIRSR10_WIDTH (1U) 1052 #define SIUL2_DIRSR0_DIRSR10(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRSR0_DIRSR10_SHIFT)) & SIUL2_DIRSR0_DIRSR10_MASK) 1053 1054 #define SIUL2_DIRSR0_DIRSR11_MASK (0x800U) 1055 #define SIUL2_DIRSR0_DIRSR11_SHIFT (11U) 1056 #define SIUL2_DIRSR0_DIRSR11_WIDTH (1U) 1057 #define SIUL2_DIRSR0_DIRSR11(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRSR0_DIRSR11_SHIFT)) & SIUL2_DIRSR0_DIRSR11_MASK) 1058 1059 #define SIUL2_DIRSR0_DIRSR12_MASK (0x1000U) 1060 #define SIUL2_DIRSR0_DIRSR12_SHIFT (12U) 1061 #define SIUL2_DIRSR0_DIRSR12_WIDTH (1U) 1062 #define SIUL2_DIRSR0_DIRSR12(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRSR0_DIRSR12_SHIFT)) & SIUL2_DIRSR0_DIRSR12_MASK) 1063 1064 #define SIUL2_DIRSR0_DIRSR13_MASK (0x2000U) 1065 #define SIUL2_DIRSR0_DIRSR13_SHIFT (13U) 1066 #define SIUL2_DIRSR0_DIRSR13_WIDTH (1U) 1067 #define SIUL2_DIRSR0_DIRSR13(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRSR0_DIRSR13_SHIFT)) & SIUL2_DIRSR0_DIRSR13_MASK) 1068 1069 #define SIUL2_DIRSR0_DIRSR14_MASK (0x4000U) 1070 #define SIUL2_DIRSR0_DIRSR14_SHIFT (14U) 1071 #define SIUL2_DIRSR0_DIRSR14_WIDTH (1U) 1072 #define SIUL2_DIRSR0_DIRSR14(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRSR0_DIRSR14_SHIFT)) & SIUL2_DIRSR0_DIRSR14_MASK) 1073 1074 #define SIUL2_DIRSR0_DIRSR15_MASK (0x8000U) 1075 #define SIUL2_DIRSR0_DIRSR15_SHIFT (15U) 1076 #define SIUL2_DIRSR0_DIRSR15_WIDTH (1U) 1077 #define SIUL2_DIRSR0_DIRSR15(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRSR0_DIRSR15_SHIFT)) & SIUL2_DIRSR0_DIRSR15_MASK) 1078 1079 #define SIUL2_DIRSR0_DIRSR16_MASK (0x10000U) 1080 #define SIUL2_DIRSR0_DIRSR16_SHIFT (16U) 1081 #define SIUL2_DIRSR0_DIRSR16_WIDTH (1U) 1082 #define SIUL2_DIRSR0_DIRSR16(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRSR0_DIRSR16_SHIFT)) & SIUL2_DIRSR0_DIRSR16_MASK) 1083 1084 #define SIUL2_DIRSR0_DIRSR17_MASK (0x20000U) 1085 #define SIUL2_DIRSR0_DIRSR17_SHIFT (17U) 1086 #define SIUL2_DIRSR0_DIRSR17_WIDTH (1U) 1087 #define SIUL2_DIRSR0_DIRSR17(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRSR0_DIRSR17_SHIFT)) & SIUL2_DIRSR0_DIRSR17_MASK) 1088 1089 #define SIUL2_DIRSR0_DIRSR18_MASK (0x40000U) 1090 #define SIUL2_DIRSR0_DIRSR18_SHIFT (18U) 1091 #define SIUL2_DIRSR0_DIRSR18_WIDTH (1U) 1092 #define SIUL2_DIRSR0_DIRSR18(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRSR0_DIRSR18_SHIFT)) & SIUL2_DIRSR0_DIRSR18_MASK) 1093 1094 #define SIUL2_DIRSR0_DIRSR19_MASK (0x80000U) 1095 #define SIUL2_DIRSR0_DIRSR19_SHIFT (19U) 1096 #define SIUL2_DIRSR0_DIRSR19_WIDTH (1U) 1097 #define SIUL2_DIRSR0_DIRSR19(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRSR0_DIRSR19_SHIFT)) & SIUL2_DIRSR0_DIRSR19_MASK) 1098 1099 #define SIUL2_DIRSR0_DIRSR20_MASK (0x100000U) 1100 #define SIUL2_DIRSR0_DIRSR20_SHIFT (20U) 1101 #define SIUL2_DIRSR0_DIRSR20_WIDTH (1U) 1102 #define SIUL2_DIRSR0_DIRSR20(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRSR0_DIRSR20_SHIFT)) & SIUL2_DIRSR0_DIRSR20_MASK) 1103 1104 #define SIUL2_DIRSR0_DIRSR21_MASK (0x200000U) 1105 #define SIUL2_DIRSR0_DIRSR21_SHIFT (21U) 1106 #define SIUL2_DIRSR0_DIRSR21_WIDTH (1U) 1107 #define SIUL2_DIRSR0_DIRSR21(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRSR0_DIRSR21_SHIFT)) & SIUL2_DIRSR0_DIRSR21_MASK) 1108 1109 #define SIUL2_DIRSR0_DIRSR22_MASK (0x400000U) 1110 #define SIUL2_DIRSR0_DIRSR22_SHIFT (22U) 1111 #define SIUL2_DIRSR0_DIRSR22_WIDTH (1U) 1112 #define SIUL2_DIRSR0_DIRSR22(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRSR0_DIRSR22_SHIFT)) & SIUL2_DIRSR0_DIRSR22_MASK) 1113 1114 #define SIUL2_DIRSR0_DIRSR23_MASK (0x800000U) 1115 #define SIUL2_DIRSR0_DIRSR23_SHIFT (23U) 1116 #define SIUL2_DIRSR0_DIRSR23_WIDTH (1U) 1117 #define SIUL2_DIRSR0_DIRSR23(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRSR0_DIRSR23_SHIFT)) & SIUL2_DIRSR0_DIRSR23_MASK) 1118 1119 #define SIUL2_DIRSR0_DIRSR24_MASK (0x1000000U) 1120 #define SIUL2_DIRSR0_DIRSR24_SHIFT (24U) 1121 #define SIUL2_DIRSR0_DIRSR24_WIDTH (1U) 1122 #define SIUL2_DIRSR0_DIRSR24(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRSR0_DIRSR24_SHIFT)) & SIUL2_DIRSR0_DIRSR24_MASK) 1123 1124 #define SIUL2_DIRSR0_DIRSR25_MASK (0x2000000U) 1125 #define SIUL2_DIRSR0_DIRSR25_SHIFT (25U) 1126 #define SIUL2_DIRSR0_DIRSR25_WIDTH (1U) 1127 #define SIUL2_DIRSR0_DIRSR25(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRSR0_DIRSR25_SHIFT)) & SIUL2_DIRSR0_DIRSR25_MASK) 1128 1129 #define SIUL2_DIRSR0_DIRSR26_MASK (0x4000000U) 1130 #define SIUL2_DIRSR0_DIRSR26_SHIFT (26U) 1131 #define SIUL2_DIRSR0_DIRSR26_WIDTH (1U) 1132 #define SIUL2_DIRSR0_DIRSR26(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRSR0_DIRSR26_SHIFT)) & SIUL2_DIRSR0_DIRSR26_MASK) 1133 1134 #define SIUL2_DIRSR0_DIRSR27_MASK (0x8000000U) 1135 #define SIUL2_DIRSR0_DIRSR27_SHIFT (27U) 1136 #define SIUL2_DIRSR0_DIRSR27_WIDTH (1U) 1137 #define SIUL2_DIRSR0_DIRSR27(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRSR0_DIRSR27_SHIFT)) & SIUL2_DIRSR0_DIRSR27_MASK) 1138 1139 #define SIUL2_DIRSR0_DIRSR28_MASK (0x10000000U) 1140 #define SIUL2_DIRSR0_DIRSR28_SHIFT (28U) 1141 #define SIUL2_DIRSR0_DIRSR28_WIDTH (1U) 1142 #define SIUL2_DIRSR0_DIRSR28(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRSR0_DIRSR28_SHIFT)) & SIUL2_DIRSR0_DIRSR28_MASK) 1143 1144 #define SIUL2_DIRSR0_DIRSR29_MASK (0x20000000U) 1145 #define SIUL2_DIRSR0_DIRSR29_SHIFT (29U) 1146 #define SIUL2_DIRSR0_DIRSR29_WIDTH (1U) 1147 #define SIUL2_DIRSR0_DIRSR29(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRSR0_DIRSR29_SHIFT)) & SIUL2_DIRSR0_DIRSR29_MASK) 1148 1149 #define SIUL2_DIRSR0_DIRSR30_MASK (0x40000000U) 1150 #define SIUL2_DIRSR0_DIRSR30_SHIFT (30U) 1151 #define SIUL2_DIRSR0_DIRSR30_WIDTH (1U) 1152 #define SIUL2_DIRSR0_DIRSR30(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRSR0_DIRSR30_SHIFT)) & SIUL2_DIRSR0_DIRSR30_MASK) 1153 1154 #define SIUL2_DIRSR0_DIRSR31_MASK (0x80000000U) 1155 #define SIUL2_DIRSR0_DIRSR31_SHIFT (31U) 1156 #define SIUL2_DIRSR0_DIRSR31_WIDTH (1U) 1157 #define SIUL2_DIRSR0_DIRSR31(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRSR0_DIRSR31_SHIFT)) & SIUL2_DIRSR0_DIRSR31_MASK) 1158 /*! @} */ 1159 1160 /*! @name IREER0 - SIUL2 Interrupt Rising-Edge Event Enable Register 0 */ 1161 /*! @{ */ 1162 1163 #define SIUL2_IREER0_IREE0_MASK (0x1U) 1164 #define SIUL2_IREER0_IREE0_SHIFT (0U) 1165 #define SIUL2_IREER0_IREE0_WIDTH (1U) 1166 #define SIUL2_IREER0_IREE0(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IREER0_IREE0_SHIFT)) & SIUL2_IREER0_IREE0_MASK) 1167 1168 #define SIUL2_IREER0_IREE1_MASK (0x2U) 1169 #define SIUL2_IREER0_IREE1_SHIFT (1U) 1170 #define SIUL2_IREER0_IREE1_WIDTH (1U) 1171 #define SIUL2_IREER0_IREE1(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IREER0_IREE1_SHIFT)) & SIUL2_IREER0_IREE1_MASK) 1172 1173 #define SIUL2_IREER0_IREE2_MASK (0x4U) 1174 #define SIUL2_IREER0_IREE2_SHIFT (2U) 1175 #define SIUL2_IREER0_IREE2_WIDTH (1U) 1176 #define SIUL2_IREER0_IREE2(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IREER0_IREE2_SHIFT)) & SIUL2_IREER0_IREE2_MASK) 1177 1178 #define SIUL2_IREER0_IREE3_MASK (0x8U) 1179 #define SIUL2_IREER0_IREE3_SHIFT (3U) 1180 #define SIUL2_IREER0_IREE3_WIDTH (1U) 1181 #define SIUL2_IREER0_IREE3(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IREER0_IREE3_SHIFT)) & SIUL2_IREER0_IREE3_MASK) 1182 1183 #define SIUL2_IREER0_IREE4_MASK (0x10U) 1184 #define SIUL2_IREER0_IREE4_SHIFT (4U) 1185 #define SIUL2_IREER0_IREE4_WIDTH (1U) 1186 #define SIUL2_IREER0_IREE4(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IREER0_IREE4_SHIFT)) & SIUL2_IREER0_IREE4_MASK) 1187 1188 #define SIUL2_IREER0_IREE5_MASK (0x20U) 1189 #define SIUL2_IREER0_IREE5_SHIFT (5U) 1190 #define SIUL2_IREER0_IREE5_WIDTH (1U) 1191 #define SIUL2_IREER0_IREE5(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IREER0_IREE5_SHIFT)) & SIUL2_IREER0_IREE5_MASK) 1192 1193 #define SIUL2_IREER0_IREE6_MASK (0x40U) 1194 #define SIUL2_IREER0_IREE6_SHIFT (6U) 1195 #define SIUL2_IREER0_IREE6_WIDTH (1U) 1196 #define SIUL2_IREER0_IREE6(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IREER0_IREE6_SHIFT)) & SIUL2_IREER0_IREE6_MASK) 1197 1198 #define SIUL2_IREER0_IREE7_MASK (0x80U) 1199 #define SIUL2_IREER0_IREE7_SHIFT (7U) 1200 #define SIUL2_IREER0_IREE7_WIDTH (1U) 1201 #define SIUL2_IREER0_IREE7(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IREER0_IREE7_SHIFT)) & SIUL2_IREER0_IREE7_MASK) 1202 1203 #define SIUL2_IREER0_IREE8_MASK (0x100U) 1204 #define SIUL2_IREER0_IREE8_SHIFT (8U) 1205 #define SIUL2_IREER0_IREE8_WIDTH (1U) 1206 #define SIUL2_IREER0_IREE8(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IREER0_IREE8_SHIFT)) & SIUL2_IREER0_IREE8_MASK) 1207 1208 #define SIUL2_IREER0_IREE9_MASK (0x200U) 1209 #define SIUL2_IREER0_IREE9_SHIFT (9U) 1210 #define SIUL2_IREER0_IREE9_WIDTH (1U) 1211 #define SIUL2_IREER0_IREE9(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IREER0_IREE9_SHIFT)) & SIUL2_IREER0_IREE9_MASK) 1212 1213 #define SIUL2_IREER0_IREE10_MASK (0x400U) 1214 #define SIUL2_IREER0_IREE10_SHIFT (10U) 1215 #define SIUL2_IREER0_IREE10_WIDTH (1U) 1216 #define SIUL2_IREER0_IREE10(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IREER0_IREE10_SHIFT)) & SIUL2_IREER0_IREE10_MASK) 1217 1218 #define SIUL2_IREER0_IREE11_MASK (0x800U) 1219 #define SIUL2_IREER0_IREE11_SHIFT (11U) 1220 #define SIUL2_IREER0_IREE11_WIDTH (1U) 1221 #define SIUL2_IREER0_IREE11(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IREER0_IREE11_SHIFT)) & SIUL2_IREER0_IREE11_MASK) 1222 1223 #define SIUL2_IREER0_IREE12_MASK (0x1000U) 1224 #define SIUL2_IREER0_IREE12_SHIFT (12U) 1225 #define SIUL2_IREER0_IREE12_WIDTH (1U) 1226 #define SIUL2_IREER0_IREE12(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IREER0_IREE12_SHIFT)) & SIUL2_IREER0_IREE12_MASK) 1227 1228 #define SIUL2_IREER0_IREE13_MASK (0x2000U) 1229 #define SIUL2_IREER0_IREE13_SHIFT (13U) 1230 #define SIUL2_IREER0_IREE13_WIDTH (1U) 1231 #define SIUL2_IREER0_IREE13(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IREER0_IREE13_SHIFT)) & SIUL2_IREER0_IREE13_MASK) 1232 1233 #define SIUL2_IREER0_IREE14_MASK (0x4000U) 1234 #define SIUL2_IREER0_IREE14_SHIFT (14U) 1235 #define SIUL2_IREER0_IREE14_WIDTH (1U) 1236 #define SIUL2_IREER0_IREE14(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IREER0_IREE14_SHIFT)) & SIUL2_IREER0_IREE14_MASK) 1237 1238 #define SIUL2_IREER0_IREE15_MASK (0x8000U) 1239 #define SIUL2_IREER0_IREE15_SHIFT (15U) 1240 #define SIUL2_IREER0_IREE15_WIDTH (1U) 1241 #define SIUL2_IREER0_IREE15(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IREER0_IREE15_SHIFT)) & SIUL2_IREER0_IREE15_MASK) 1242 1243 #define SIUL2_IREER0_IREE16_MASK (0x10000U) 1244 #define SIUL2_IREER0_IREE16_SHIFT (16U) 1245 #define SIUL2_IREER0_IREE16_WIDTH (1U) 1246 #define SIUL2_IREER0_IREE16(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IREER0_IREE16_SHIFT)) & SIUL2_IREER0_IREE16_MASK) 1247 1248 #define SIUL2_IREER0_IREE17_MASK (0x20000U) 1249 #define SIUL2_IREER0_IREE17_SHIFT (17U) 1250 #define SIUL2_IREER0_IREE17_WIDTH (1U) 1251 #define SIUL2_IREER0_IREE17(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IREER0_IREE17_SHIFT)) & SIUL2_IREER0_IREE17_MASK) 1252 1253 #define SIUL2_IREER0_IREE18_MASK (0x40000U) 1254 #define SIUL2_IREER0_IREE18_SHIFT (18U) 1255 #define SIUL2_IREER0_IREE18_WIDTH (1U) 1256 #define SIUL2_IREER0_IREE18(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IREER0_IREE18_SHIFT)) & SIUL2_IREER0_IREE18_MASK) 1257 1258 #define SIUL2_IREER0_IREE19_MASK (0x80000U) 1259 #define SIUL2_IREER0_IREE19_SHIFT (19U) 1260 #define SIUL2_IREER0_IREE19_WIDTH (1U) 1261 #define SIUL2_IREER0_IREE19(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IREER0_IREE19_SHIFT)) & SIUL2_IREER0_IREE19_MASK) 1262 1263 #define SIUL2_IREER0_IREE20_MASK (0x100000U) 1264 #define SIUL2_IREER0_IREE20_SHIFT (20U) 1265 #define SIUL2_IREER0_IREE20_WIDTH (1U) 1266 #define SIUL2_IREER0_IREE20(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IREER0_IREE20_SHIFT)) & SIUL2_IREER0_IREE20_MASK) 1267 1268 #define SIUL2_IREER0_IREE21_MASK (0x200000U) 1269 #define SIUL2_IREER0_IREE21_SHIFT (21U) 1270 #define SIUL2_IREER0_IREE21_WIDTH (1U) 1271 #define SIUL2_IREER0_IREE21(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IREER0_IREE21_SHIFT)) & SIUL2_IREER0_IREE21_MASK) 1272 1273 #define SIUL2_IREER0_IREE22_MASK (0x400000U) 1274 #define SIUL2_IREER0_IREE22_SHIFT (22U) 1275 #define SIUL2_IREER0_IREE22_WIDTH (1U) 1276 #define SIUL2_IREER0_IREE22(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IREER0_IREE22_SHIFT)) & SIUL2_IREER0_IREE22_MASK) 1277 1278 #define SIUL2_IREER0_IREE23_MASK (0x800000U) 1279 #define SIUL2_IREER0_IREE23_SHIFT (23U) 1280 #define SIUL2_IREER0_IREE23_WIDTH (1U) 1281 #define SIUL2_IREER0_IREE23(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IREER0_IREE23_SHIFT)) & SIUL2_IREER0_IREE23_MASK) 1282 1283 #define SIUL2_IREER0_IREE24_MASK (0x1000000U) 1284 #define SIUL2_IREER0_IREE24_SHIFT (24U) 1285 #define SIUL2_IREER0_IREE24_WIDTH (1U) 1286 #define SIUL2_IREER0_IREE24(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IREER0_IREE24_SHIFT)) & SIUL2_IREER0_IREE24_MASK) 1287 1288 #define SIUL2_IREER0_IREE25_MASK (0x2000000U) 1289 #define SIUL2_IREER0_IREE25_SHIFT (25U) 1290 #define SIUL2_IREER0_IREE25_WIDTH (1U) 1291 #define SIUL2_IREER0_IREE25(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IREER0_IREE25_SHIFT)) & SIUL2_IREER0_IREE25_MASK) 1292 1293 #define SIUL2_IREER0_IREE26_MASK (0x4000000U) 1294 #define SIUL2_IREER0_IREE26_SHIFT (26U) 1295 #define SIUL2_IREER0_IREE26_WIDTH (1U) 1296 #define SIUL2_IREER0_IREE26(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IREER0_IREE26_SHIFT)) & SIUL2_IREER0_IREE26_MASK) 1297 1298 #define SIUL2_IREER0_IREE27_MASK (0x8000000U) 1299 #define SIUL2_IREER0_IREE27_SHIFT (27U) 1300 #define SIUL2_IREER0_IREE27_WIDTH (1U) 1301 #define SIUL2_IREER0_IREE27(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IREER0_IREE27_SHIFT)) & SIUL2_IREER0_IREE27_MASK) 1302 1303 #define SIUL2_IREER0_IREE28_MASK (0x10000000U) 1304 #define SIUL2_IREER0_IREE28_SHIFT (28U) 1305 #define SIUL2_IREER0_IREE28_WIDTH (1U) 1306 #define SIUL2_IREER0_IREE28(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IREER0_IREE28_SHIFT)) & SIUL2_IREER0_IREE28_MASK) 1307 1308 #define SIUL2_IREER0_IREE29_MASK (0x20000000U) 1309 #define SIUL2_IREER0_IREE29_SHIFT (29U) 1310 #define SIUL2_IREER0_IREE29_WIDTH (1U) 1311 #define SIUL2_IREER0_IREE29(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IREER0_IREE29_SHIFT)) & SIUL2_IREER0_IREE29_MASK) 1312 1313 #define SIUL2_IREER0_IREE30_MASK (0x40000000U) 1314 #define SIUL2_IREER0_IREE30_SHIFT (30U) 1315 #define SIUL2_IREER0_IREE30_WIDTH (1U) 1316 #define SIUL2_IREER0_IREE30(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IREER0_IREE30_SHIFT)) & SIUL2_IREER0_IREE30_MASK) 1317 1318 #define SIUL2_IREER0_IREE31_MASK (0x80000000U) 1319 #define SIUL2_IREER0_IREE31_SHIFT (31U) 1320 #define SIUL2_IREER0_IREE31_WIDTH (1U) 1321 #define SIUL2_IREER0_IREE31(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IREER0_IREE31_SHIFT)) & SIUL2_IREER0_IREE31_MASK) 1322 /*! @} */ 1323 1324 /*! @name IFEER0 - SIUL2 Interrupt Falling-Edge Event Enable Register 0 */ 1325 /*! @{ */ 1326 1327 #define SIUL2_IFEER0_IFEE0_MASK (0x1U) 1328 #define SIUL2_IFEER0_IFEE0_SHIFT (0U) 1329 #define SIUL2_IFEER0_IFEE0_WIDTH (1U) 1330 #define SIUL2_IFEER0_IFEE0(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFEER0_IFEE0_SHIFT)) & SIUL2_IFEER0_IFEE0_MASK) 1331 1332 #define SIUL2_IFEER0_IFEE1_MASK (0x2U) 1333 #define SIUL2_IFEER0_IFEE1_SHIFT (1U) 1334 #define SIUL2_IFEER0_IFEE1_WIDTH (1U) 1335 #define SIUL2_IFEER0_IFEE1(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFEER0_IFEE1_SHIFT)) & SIUL2_IFEER0_IFEE1_MASK) 1336 1337 #define SIUL2_IFEER0_IFEE2_MASK (0x4U) 1338 #define SIUL2_IFEER0_IFEE2_SHIFT (2U) 1339 #define SIUL2_IFEER0_IFEE2_WIDTH (1U) 1340 #define SIUL2_IFEER0_IFEE2(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFEER0_IFEE2_SHIFT)) & SIUL2_IFEER0_IFEE2_MASK) 1341 1342 #define SIUL2_IFEER0_IFEE3_MASK (0x8U) 1343 #define SIUL2_IFEER0_IFEE3_SHIFT (3U) 1344 #define SIUL2_IFEER0_IFEE3_WIDTH (1U) 1345 #define SIUL2_IFEER0_IFEE3(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFEER0_IFEE3_SHIFT)) & SIUL2_IFEER0_IFEE3_MASK) 1346 1347 #define SIUL2_IFEER0_IFEE4_MASK (0x10U) 1348 #define SIUL2_IFEER0_IFEE4_SHIFT (4U) 1349 #define SIUL2_IFEER0_IFEE4_WIDTH (1U) 1350 #define SIUL2_IFEER0_IFEE4(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFEER0_IFEE4_SHIFT)) & SIUL2_IFEER0_IFEE4_MASK) 1351 1352 #define SIUL2_IFEER0_IFEE5_MASK (0x20U) 1353 #define SIUL2_IFEER0_IFEE5_SHIFT (5U) 1354 #define SIUL2_IFEER0_IFEE5_WIDTH (1U) 1355 #define SIUL2_IFEER0_IFEE5(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFEER0_IFEE5_SHIFT)) & SIUL2_IFEER0_IFEE5_MASK) 1356 1357 #define SIUL2_IFEER0_IFEE6_MASK (0x40U) 1358 #define SIUL2_IFEER0_IFEE6_SHIFT (6U) 1359 #define SIUL2_IFEER0_IFEE6_WIDTH (1U) 1360 #define SIUL2_IFEER0_IFEE6(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFEER0_IFEE6_SHIFT)) & SIUL2_IFEER0_IFEE6_MASK) 1361 1362 #define SIUL2_IFEER0_IFEE7_MASK (0x80U) 1363 #define SIUL2_IFEER0_IFEE7_SHIFT (7U) 1364 #define SIUL2_IFEER0_IFEE7_WIDTH (1U) 1365 #define SIUL2_IFEER0_IFEE7(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFEER0_IFEE7_SHIFT)) & SIUL2_IFEER0_IFEE7_MASK) 1366 1367 #define SIUL2_IFEER0_IFEE8_MASK (0x100U) 1368 #define SIUL2_IFEER0_IFEE8_SHIFT (8U) 1369 #define SIUL2_IFEER0_IFEE8_WIDTH (1U) 1370 #define SIUL2_IFEER0_IFEE8(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFEER0_IFEE8_SHIFT)) & SIUL2_IFEER0_IFEE8_MASK) 1371 1372 #define SIUL2_IFEER0_IFEE9_MASK (0x200U) 1373 #define SIUL2_IFEER0_IFEE9_SHIFT (9U) 1374 #define SIUL2_IFEER0_IFEE9_WIDTH (1U) 1375 #define SIUL2_IFEER0_IFEE9(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFEER0_IFEE9_SHIFT)) & SIUL2_IFEER0_IFEE9_MASK) 1376 1377 #define SIUL2_IFEER0_IFEE10_MASK (0x400U) 1378 #define SIUL2_IFEER0_IFEE10_SHIFT (10U) 1379 #define SIUL2_IFEER0_IFEE10_WIDTH (1U) 1380 #define SIUL2_IFEER0_IFEE10(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFEER0_IFEE10_SHIFT)) & SIUL2_IFEER0_IFEE10_MASK) 1381 1382 #define SIUL2_IFEER0_IFEE11_MASK (0x800U) 1383 #define SIUL2_IFEER0_IFEE11_SHIFT (11U) 1384 #define SIUL2_IFEER0_IFEE11_WIDTH (1U) 1385 #define SIUL2_IFEER0_IFEE11(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFEER0_IFEE11_SHIFT)) & SIUL2_IFEER0_IFEE11_MASK) 1386 1387 #define SIUL2_IFEER0_IFEE12_MASK (0x1000U) 1388 #define SIUL2_IFEER0_IFEE12_SHIFT (12U) 1389 #define SIUL2_IFEER0_IFEE12_WIDTH (1U) 1390 #define SIUL2_IFEER0_IFEE12(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFEER0_IFEE12_SHIFT)) & SIUL2_IFEER0_IFEE12_MASK) 1391 1392 #define SIUL2_IFEER0_IFEE13_MASK (0x2000U) 1393 #define SIUL2_IFEER0_IFEE13_SHIFT (13U) 1394 #define SIUL2_IFEER0_IFEE13_WIDTH (1U) 1395 #define SIUL2_IFEER0_IFEE13(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFEER0_IFEE13_SHIFT)) & SIUL2_IFEER0_IFEE13_MASK) 1396 1397 #define SIUL2_IFEER0_IFEE14_MASK (0x4000U) 1398 #define SIUL2_IFEER0_IFEE14_SHIFT (14U) 1399 #define SIUL2_IFEER0_IFEE14_WIDTH (1U) 1400 #define SIUL2_IFEER0_IFEE14(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFEER0_IFEE14_SHIFT)) & SIUL2_IFEER0_IFEE14_MASK) 1401 1402 #define SIUL2_IFEER0_IFEE15_MASK (0x8000U) 1403 #define SIUL2_IFEER0_IFEE15_SHIFT (15U) 1404 #define SIUL2_IFEER0_IFEE15_WIDTH (1U) 1405 #define SIUL2_IFEER0_IFEE15(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFEER0_IFEE15_SHIFT)) & SIUL2_IFEER0_IFEE15_MASK) 1406 1407 #define SIUL2_IFEER0_IFEE16_MASK (0x10000U) 1408 #define SIUL2_IFEER0_IFEE16_SHIFT (16U) 1409 #define SIUL2_IFEER0_IFEE16_WIDTH (1U) 1410 #define SIUL2_IFEER0_IFEE16(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFEER0_IFEE16_SHIFT)) & SIUL2_IFEER0_IFEE16_MASK) 1411 1412 #define SIUL2_IFEER0_IFEE17_MASK (0x20000U) 1413 #define SIUL2_IFEER0_IFEE17_SHIFT (17U) 1414 #define SIUL2_IFEER0_IFEE17_WIDTH (1U) 1415 #define SIUL2_IFEER0_IFEE17(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFEER0_IFEE17_SHIFT)) & SIUL2_IFEER0_IFEE17_MASK) 1416 1417 #define SIUL2_IFEER0_IFEE18_MASK (0x40000U) 1418 #define SIUL2_IFEER0_IFEE18_SHIFT (18U) 1419 #define SIUL2_IFEER0_IFEE18_WIDTH (1U) 1420 #define SIUL2_IFEER0_IFEE18(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFEER0_IFEE18_SHIFT)) & SIUL2_IFEER0_IFEE18_MASK) 1421 1422 #define SIUL2_IFEER0_IFEE19_MASK (0x80000U) 1423 #define SIUL2_IFEER0_IFEE19_SHIFT (19U) 1424 #define SIUL2_IFEER0_IFEE19_WIDTH (1U) 1425 #define SIUL2_IFEER0_IFEE19(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFEER0_IFEE19_SHIFT)) & SIUL2_IFEER0_IFEE19_MASK) 1426 1427 #define SIUL2_IFEER0_IFEE20_MASK (0x100000U) 1428 #define SIUL2_IFEER0_IFEE20_SHIFT (20U) 1429 #define SIUL2_IFEER0_IFEE20_WIDTH (1U) 1430 #define SIUL2_IFEER0_IFEE20(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFEER0_IFEE20_SHIFT)) & SIUL2_IFEER0_IFEE20_MASK) 1431 1432 #define SIUL2_IFEER0_IFEE21_MASK (0x200000U) 1433 #define SIUL2_IFEER0_IFEE21_SHIFT (21U) 1434 #define SIUL2_IFEER0_IFEE21_WIDTH (1U) 1435 #define SIUL2_IFEER0_IFEE21(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFEER0_IFEE21_SHIFT)) & SIUL2_IFEER0_IFEE21_MASK) 1436 1437 #define SIUL2_IFEER0_IFEE22_MASK (0x400000U) 1438 #define SIUL2_IFEER0_IFEE22_SHIFT (22U) 1439 #define SIUL2_IFEER0_IFEE22_WIDTH (1U) 1440 #define SIUL2_IFEER0_IFEE22(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFEER0_IFEE22_SHIFT)) & SIUL2_IFEER0_IFEE22_MASK) 1441 1442 #define SIUL2_IFEER0_IFEE23_MASK (0x800000U) 1443 #define SIUL2_IFEER0_IFEE23_SHIFT (23U) 1444 #define SIUL2_IFEER0_IFEE23_WIDTH (1U) 1445 #define SIUL2_IFEER0_IFEE23(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFEER0_IFEE23_SHIFT)) & SIUL2_IFEER0_IFEE23_MASK) 1446 1447 #define SIUL2_IFEER0_IFEE24_MASK (0x1000000U) 1448 #define SIUL2_IFEER0_IFEE24_SHIFT (24U) 1449 #define SIUL2_IFEER0_IFEE24_WIDTH (1U) 1450 #define SIUL2_IFEER0_IFEE24(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFEER0_IFEE24_SHIFT)) & SIUL2_IFEER0_IFEE24_MASK) 1451 1452 #define SIUL2_IFEER0_IFEE25_MASK (0x2000000U) 1453 #define SIUL2_IFEER0_IFEE25_SHIFT (25U) 1454 #define SIUL2_IFEER0_IFEE25_WIDTH (1U) 1455 #define SIUL2_IFEER0_IFEE25(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFEER0_IFEE25_SHIFT)) & SIUL2_IFEER0_IFEE25_MASK) 1456 1457 #define SIUL2_IFEER0_IFEE26_MASK (0x4000000U) 1458 #define SIUL2_IFEER0_IFEE26_SHIFT (26U) 1459 #define SIUL2_IFEER0_IFEE26_WIDTH (1U) 1460 #define SIUL2_IFEER0_IFEE26(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFEER0_IFEE26_SHIFT)) & SIUL2_IFEER0_IFEE26_MASK) 1461 1462 #define SIUL2_IFEER0_IFEE27_MASK (0x8000000U) 1463 #define SIUL2_IFEER0_IFEE27_SHIFT (27U) 1464 #define SIUL2_IFEER0_IFEE27_WIDTH (1U) 1465 #define SIUL2_IFEER0_IFEE27(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFEER0_IFEE27_SHIFT)) & SIUL2_IFEER0_IFEE27_MASK) 1466 1467 #define SIUL2_IFEER0_IFEE28_MASK (0x10000000U) 1468 #define SIUL2_IFEER0_IFEE28_SHIFT (28U) 1469 #define SIUL2_IFEER0_IFEE28_WIDTH (1U) 1470 #define SIUL2_IFEER0_IFEE28(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFEER0_IFEE28_SHIFT)) & SIUL2_IFEER0_IFEE28_MASK) 1471 1472 #define SIUL2_IFEER0_IFEE29_MASK (0x20000000U) 1473 #define SIUL2_IFEER0_IFEE29_SHIFT (29U) 1474 #define SIUL2_IFEER0_IFEE29_WIDTH (1U) 1475 #define SIUL2_IFEER0_IFEE29(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFEER0_IFEE29_SHIFT)) & SIUL2_IFEER0_IFEE29_MASK) 1476 1477 #define SIUL2_IFEER0_IFEE30_MASK (0x40000000U) 1478 #define SIUL2_IFEER0_IFEE30_SHIFT (30U) 1479 #define SIUL2_IFEER0_IFEE30_WIDTH (1U) 1480 #define SIUL2_IFEER0_IFEE30(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFEER0_IFEE30_SHIFT)) & SIUL2_IFEER0_IFEE30_MASK) 1481 1482 #define SIUL2_IFEER0_IFEE31_MASK (0x80000000U) 1483 #define SIUL2_IFEER0_IFEE31_SHIFT (31U) 1484 #define SIUL2_IFEER0_IFEE31_WIDTH (1U) 1485 #define SIUL2_IFEER0_IFEE31(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFEER0_IFEE31_SHIFT)) & SIUL2_IFEER0_IFEE31_MASK) 1486 /*! @} */ 1487 1488 /*! @name IFER0 - SIUL2 Interrupt Filter Enable Register 0 */ 1489 /*! @{ */ 1490 1491 #define SIUL2_IFER0_IFE0_MASK (0x1U) 1492 #define SIUL2_IFER0_IFE0_SHIFT (0U) 1493 #define SIUL2_IFER0_IFE0_WIDTH (1U) 1494 #define SIUL2_IFER0_IFE0(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFER0_IFE0_SHIFT)) & SIUL2_IFER0_IFE0_MASK) 1495 1496 #define SIUL2_IFER0_IFE1_MASK (0x2U) 1497 #define SIUL2_IFER0_IFE1_SHIFT (1U) 1498 #define SIUL2_IFER0_IFE1_WIDTH (1U) 1499 #define SIUL2_IFER0_IFE1(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFER0_IFE1_SHIFT)) & SIUL2_IFER0_IFE1_MASK) 1500 1501 #define SIUL2_IFER0_IFE2_MASK (0x4U) 1502 #define SIUL2_IFER0_IFE2_SHIFT (2U) 1503 #define SIUL2_IFER0_IFE2_WIDTH (1U) 1504 #define SIUL2_IFER0_IFE2(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFER0_IFE2_SHIFT)) & SIUL2_IFER0_IFE2_MASK) 1505 1506 #define SIUL2_IFER0_IFE3_MASK (0x8U) 1507 #define SIUL2_IFER0_IFE3_SHIFT (3U) 1508 #define SIUL2_IFER0_IFE3_WIDTH (1U) 1509 #define SIUL2_IFER0_IFE3(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFER0_IFE3_SHIFT)) & SIUL2_IFER0_IFE3_MASK) 1510 1511 #define SIUL2_IFER0_IFE4_MASK (0x10U) 1512 #define SIUL2_IFER0_IFE4_SHIFT (4U) 1513 #define SIUL2_IFER0_IFE4_WIDTH (1U) 1514 #define SIUL2_IFER0_IFE4(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFER0_IFE4_SHIFT)) & SIUL2_IFER0_IFE4_MASK) 1515 1516 #define SIUL2_IFER0_IFE5_MASK (0x20U) 1517 #define SIUL2_IFER0_IFE5_SHIFT (5U) 1518 #define SIUL2_IFER0_IFE5_WIDTH (1U) 1519 #define SIUL2_IFER0_IFE5(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFER0_IFE5_SHIFT)) & SIUL2_IFER0_IFE5_MASK) 1520 1521 #define SIUL2_IFER0_IFE6_MASK (0x40U) 1522 #define SIUL2_IFER0_IFE6_SHIFT (6U) 1523 #define SIUL2_IFER0_IFE6_WIDTH (1U) 1524 #define SIUL2_IFER0_IFE6(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFER0_IFE6_SHIFT)) & SIUL2_IFER0_IFE6_MASK) 1525 1526 #define SIUL2_IFER0_IFE7_MASK (0x80U) 1527 #define SIUL2_IFER0_IFE7_SHIFT (7U) 1528 #define SIUL2_IFER0_IFE7_WIDTH (1U) 1529 #define SIUL2_IFER0_IFE7(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFER0_IFE7_SHIFT)) & SIUL2_IFER0_IFE7_MASK) 1530 1531 #define SIUL2_IFER0_IFE8_MASK (0x100U) 1532 #define SIUL2_IFER0_IFE8_SHIFT (8U) 1533 #define SIUL2_IFER0_IFE8_WIDTH (1U) 1534 #define SIUL2_IFER0_IFE8(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFER0_IFE8_SHIFT)) & SIUL2_IFER0_IFE8_MASK) 1535 1536 #define SIUL2_IFER0_IFE9_MASK (0x200U) 1537 #define SIUL2_IFER0_IFE9_SHIFT (9U) 1538 #define SIUL2_IFER0_IFE9_WIDTH (1U) 1539 #define SIUL2_IFER0_IFE9(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFER0_IFE9_SHIFT)) & SIUL2_IFER0_IFE9_MASK) 1540 1541 #define SIUL2_IFER0_IFE10_MASK (0x400U) 1542 #define SIUL2_IFER0_IFE10_SHIFT (10U) 1543 #define SIUL2_IFER0_IFE10_WIDTH (1U) 1544 #define SIUL2_IFER0_IFE10(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFER0_IFE10_SHIFT)) & SIUL2_IFER0_IFE10_MASK) 1545 1546 #define SIUL2_IFER0_IFE11_MASK (0x800U) 1547 #define SIUL2_IFER0_IFE11_SHIFT (11U) 1548 #define SIUL2_IFER0_IFE11_WIDTH (1U) 1549 #define SIUL2_IFER0_IFE11(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFER0_IFE11_SHIFT)) & SIUL2_IFER0_IFE11_MASK) 1550 1551 #define SIUL2_IFER0_IFE12_MASK (0x1000U) 1552 #define SIUL2_IFER0_IFE12_SHIFT (12U) 1553 #define SIUL2_IFER0_IFE12_WIDTH (1U) 1554 #define SIUL2_IFER0_IFE12(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFER0_IFE12_SHIFT)) & SIUL2_IFER0_IFE12_MASK) 1555 1556 #define SIUL2_IFER0_IFE13_MASK (0x2000U) 1557 #define SIUL2_IFER0_IFE13_SHIFT (13U) 1558 #define SIUL2_IFER0_IFE13_WIDTH (1U) 1559 #define SIUL2_IFER0_IFE13(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFER0_IFE13_SHIFT)) & SIUL2_IFER0_IFE13_MASK) 1560 1561 #define SIUL2_IFER0_IFE14_MASK (0x4000U) 1562 #define SIUL2_IFER0_IFE14_SHIFT (14U) 1563 #define SIUL2_IFER0_IFE14_WIDTH (1U) 1564 #define SIUL2_IFER0_IFE14(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFER0_IFE14_SHIFT)) & SIUL2_IFER0_IFE14_MASK) 1565 1566 #define SIUL2_IFER0_IFE15_MASK (0x8000U) 1567 #define SIUL2_IFER0_IFE15_SHIFT (15U) 1568 #define SIUL2_IFER0_IFE15_WIDTH (1U) 1569 #define SIUL2_IFER0_IFE15(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFER0_IFE15_SHIFT)) & SIUL2_IFER0_IFE15_MASK) 1570 1571 #define SIUL2_IFER0_IFE16_MASK (0x10000U) 1572 #define SIUL2_IFER0_IFE16_SHIFT (16U) 1573 #define SIUL2_IFER0_IFE16_WIDTH (1U) 1574 #define SIUL2_IFER0_IFE16(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFER0_IFE16_SHIFT)) & SIUL2_IFER0_IFE16_MASK) 1575 1576 #define SIUL2_IFER0_IFE17_MASK (0x20000U) 1577 #define SIUL2_IFER0_IFE17_SHIFT (17U) 1578 #define SIUL2_IFER0_IFE17_WIDTH (1U) 1579 #define SIUL2_IFER0_IFE17(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFER0_IFE17_SHIFT)) & SIUL2_IFER0_IFE17_MASK) 1580 1581 #define SIUL2_IFER0_IFE18_MASK (0x40000U) 1582 #define SIUL2_IFER0_IFE18_SHIFT (18U) 1583 #define SIUL2_IFER0_IFE18_WIDTH (1U) 1584 #define SIUL2_IFER0_IFE18(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFER0_IFE18_SHIFT)) & SIUL2_IFER0_IFE18_MASK) 1585 1586 #define SIUL2_IFER0_IFE19_MASK (0x80000U) 1587 #define SIUL2_IFER0_IFE19_SHIFT (19U) 1588 #define SIUL2_IFER0_IFE19_WIDTH (1U) 1589 #define SIUL2_IFER0_IFE19(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFER0_IFE19_SHIFT)) & SIUL2_IFER0_IFE19_MASK) 1590 1591 #define SIUL2_IFER0_IFE20_MASK (0x100000U) 1592 #define SIUL2_IFER0_IFE20_SHIFT (20U) 1593 #define SIUL2_IFER0_IFE20_WIDTH (1U) 1594 #define SIUL2_IFER0_IFE20(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFER0_IFE20_SHIFT)) & SIUL2_IFER0_IFE20_MASK) 1595 1596 #define SIUL2_IFER0_IFE21_MASK (0x200000U) 1597 #define SIUL2_IFER0_IFE21_SHIFT (21U) 1598 #define SIUL2_IFER0_IFE21_WIDTH (1U) 1599 #define SIUL2_IFER0_IFE21(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFER0_IFE21_SHIFT)) & SIUL2_IFER0_IFE21_MASK) 1600 1601 #define SIUL2_IFER0_IFE22_MASK (0x400000U) 1602 #define SIUL2_IFER0_IFE22_SHIFT (22U) 1603 #define SIUL2_IFER0_IFE22_WIDTH (1U) 1604 #define SIUL2_IFER0_IFE22(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFER0_IFE22_SHIFT)) & SIUL2_IFER0_IFE22_MASK) 1605 1606 #define SIUL2_IFER0_IFE23_MASK (0x800000U) 1607 #define SIUL2_IFER0_IFE23_SHIFT (23U) 1608 #define SIUL2_IFER0_IFE23_WIDTH (1U) 1609 #define SIUL2_IFER0_IFE23(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFER0_IFE23_SHIFT)) & SIUL2_IFER0_IFE23_MASK) 1610 1611 #define SIUL2_IFER0_IFE24_MASK (0x1000000U) 1612 #define SIUL2_IFER0_IFE24_SHIFT (24U) 1613 #define SIUL2_IFER0_IFE24_WIDTH (1U) 1614 #define SIUL2_IFER0_IFE24(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFER0_IFE24_SHIFT)) & SIUL2_IFER0_IFE24_MASK) 1615 1616 #define SIUL2_IFER0_IFE25_MASK (0x2000000U) 1617 #define SIUL2_IFER0_IFE25_SHIFT (25U) 1618 #define SIUL2_IFER0_IFE25_WIDTH (1U) 1619 #define SIUL2_IFER0_IFE25(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFER0_IFE25_SHIFT)) & SIUL2_IFER0_IFE25_MASK) 1620 1621 #define SIUL2_IFER0_IFE26_MASK (0x4000000U) 1622 #define SIUL2_IFER0_IFE26_SHIFT (26U) 1623 #define SIUL2_IFER0_IFE26_WIDTH (1U) 1624 #define SIUL2_IFER0_IFE26(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFER0_IFE26_SHIFT)) & SIUL2_IFER0_IFE26_MASK) 1625 1626 #define SIUL2_IFER0_IFE27_MASK (0x8000000U) 1627 #define SIUL2_IFER0_IFE27_SHIFT (27U) 1628 #define SIUL2_IFER0_IFE27_WIDTH (1U) 1629 #define SIUL2_IFER0_IFE27(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFER0_IFE27_SHIFT)) & SIUL2_IFER0_IFE27_MASK) 1630 1631 #define SIUL2_IFER0_IFE28_MASK (0x10000000U) 1632 #define SIUL2_IFER0_IFE28_SHIFT (28U) 1633 #define SIUL2_IFER0_IFE28_WIDTH (1U) 1634 #define SIUL2_IFER0_IFE28(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFER0_IFE28_SHIFT)) & SIUL2_IFER0_IFE28_MASK) 1635 1636 #define SIUL2_IFER0_IFE29_MASK (0x20000000U) 1637 #define SIUL2_IFER0_IFE29_SHIFT (29U) 1638 #define SIUL2_IFER0_IFE29_WIDTH (1U) 1639 #define SIUL2_IFER0_IFE29(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFER0_IFE29_SHIFT)) & SIUL2_IFER0_IFE29_MASK) 1640 1641 #define SIUL2_IFER0_IFE30_MASK (0x40000000U) 1642 #define SIUL2_IFER0_IFE30_SHIFT (30U) 1643 #define SIUL2_IFER0_IFE30_WIDTH (1U) 1644 #define SIUL2_IFER0_IFE30(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFER0_IFE30_SHIFT)) & SIUL2_IFER0_IFE30_MASK) 1645 1646 #define SIUL2_IFER0_IFE31_MASK (0x80000000U) 1647 #define SIUL2_IFER0_IFE31_SHIFT (31U) 1648 #define SIUL2_IFER0_IFE31_WIDTH (1U) 1649 #define SIUL2_IFER0_IFE31(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFER0_IFE31_SHIFT)) & SIUL2_IFER0_IFE31_MASK) 1650 /*! @} */ 1651 1652 /*! @name IFMCR - SIUL2 Interrupt Filter Maximum Counter Register */ 1653 /*! @{ */ 1654 1655 #define SIUL2_IFMCR_MAXCNT_MASK (0xFU) 1656 #define SIUL2_IFMCR_MAXCNT_SHIFT (0U) 1657 #define SIUL2_IFMCR_MAXCNT_WIDTH (4U) 1658 #define SIUL2_IFMCR_MAXCNT(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFMCR_MAXCNT_SHIFT)) & SIUL2_IFMCR_MAXCNT_MASK) 1659 /*! @} */ 1660 1661 /*! @name IFCPR - SIUL2 Interrupt Filter Clock Prescaler Register */ 1662 /*! @{ */ 1663 1664 #define SIUL2_IFCPR_IFCP_MASK (0xFU) 1665 #define SIUL2_IFCPR_IFCP_SHIFT (0U) 1666 #define SIUL2_IFCPR_IFCP_WIDTH (4U) 1667 #define SIUL2_IFCPR_IFCP(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFCPR_IFCP_SHIFT)) & SIUL2_IFCPR_IFCP_MASK) 1668 /*! @} */ 1669 1670 /*! @name MIDR3 - SIUL2 MCU ID Register #3 */ 1671 /*! @{ */ 1672 1673 #define SIUL2_MIDR3_SYS_RAM_SIZE_MASK (0x3FU) 1674 #define SIUL2_MIDR3_SYS_RAM_SIZE_SHIFT (0U) 1675 #define SIUL2_MIDR3_SYS_RAM_SIZE_WIDTH (6U) 1676 #define SIUL2_MIDR3_SYS_RAM_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MIDR3_SYS_RAM_SIZE_SHIFT)) & SIUL2_MIDR3_SYS_RAM_SIZE_MASK) 1677 1678 #define SIUL2_MIDR3_PART_NO_SUF_MASK (0xFC00U) 1679 #define SIUL2_MIDR3_PART_NO_SUF_SHIFT (10U) 1680 #define SIUL2_MIDR3_PART_NO_SUF_WIDTH (6U) 1681 #define SIUL2_MIDR3_PART_NO_SUF(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MIDR3_PART_NO_SUF_SHIFT)) & SIUL2_MIDR3_PART_NO_SUF_MASK) 1682 1683 #define SIUL2_MIDR3_PROD_FAM_NO_MASK (0x3FF0000U) 1684 #define SIUL2_MIDR3_PROD_FAM_NO_SHIFT (16U) 1685 #define SIUL2_MIDR3_PROD_FAM_NO_WIDTH (10U) 1686 #define SIUL2_MIDR3_PROD_FAM_NO(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MIDR3_PROD_FAM_NO_SHIFT)) & SIUL2_MIDR3_PROD_FAM_NO_MASK) 1687 1688 #define SIUL2_MIDR3_PROD_FAM_LET_MASK (0xFC000000U) 1689 #define SIUL2_MIDR3_PROD_FAM_LET_SHIFT (26U) 1690 #define SIUL2_MIDR3_PROD_FAM_LET_WIDTH (6U) 1691 #define SIUL2_MIDR3_PROD_FAM_LET(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MIDR3_PROD_FAM_LET_SHIFT)) & SIUL2_MIDR3_PROD_FAM_LET_MASK) 1692 /*! @} */ 1693 1694 /*! @name MIDR4 - SIUL2 MCU ID Register #4 */ 1695 /*! @{ */ 1696 1697 #define SIUL2_MIDR4_CORE_PLAT_FET_MASK (0x7U) 1698 #define SIUL2_MIDR4_CORE_PLAT_FET_SHIFT (0U) 1699 #define SIUL2_MIDR4_CORE_PLAT_FET_WIDTH (3U) 1700 #define SIUL2_MIDR4_CORE_PLAT_FET(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MIDR4_CORE_PLAT_FET_SHIFT)) & SIUL2_MIDR4_CORE_PLAT_FET_MASK) 1701 1702 #define SIUL2_MIDR4_EMAC_FET_MASK (0x18U) 1703 #define SIUL2_MIDR4_EMAC_FET_SHIFT (3U) 1704 #define SIUL2_MIDR4_EMAC_FET_WIDTH (2U) 1705 #define SIUL2_MIDR4_EMAC_FET(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MIDR4_EMAC_FET_SHIFT)) & SIUL2_MIDR4_EMAC_FET_MASK) 1706 1707 #define SIUL2_MIDR4_SEC_FET_MASK (0x60U) 1708 #define SIUL2_MIDR4_SEC_FET_SHIFT (5U) 1709 #define SIUL2_MIDR4_SEC_FET_WIDTH (2U) 1710 #define SIUL2_MIDR4_SEC_FET(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MIDR4_SEC_FET_SHIFT)) & SIUL2_MIDR4_SEC_FET_MASK) 1711 /*! @} */ 1712 1713 /*! @name MSCR - SIUL2 Multiplexed Signal Configuration Register */ 1714 /*! @{ */ 1715 1716 #define SIUL2_MSCR_SSS_0_MASK (0x1U) 1717 #define SIUL2_MSCR_SSS_0_SHIFT (0U) 1718 #define SIUL2_MSCR_SSS_0_WIDTH (1U) 1719 #define SIUL2_MSCR_SSS_0(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MSCR_SSS_0_SHIFT)) & SIUL2_MSCR_SSS_0_MASK) 1720 1721 #define SIUL2_MSCR_SSS_1_MASK (0x2U) 1722 #define SIUL2_MSCR_SSS_1_SHIFT (1U) 1723 #define SIUL2_MSCR_SSS_1_WIDTH (1U) 1724 #define SIUL2_MSCR_SSS_1(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MSCR_SSS_1_SHIFT)) & SIUL2_MSCR_SSS_1_MASK) 1725 1726 #define SIUL2_MSCR_SSS_2_MASK (0x4U) 1727 #define SIUL2_MSCR_SSS_2_SHIFT (2U) 1728 #define SIUL2_MSCR_SSS_2_WIDTH (1U) 1729 #define SIUL2_MSCR_SSS_2(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MSCR_SSS_2_SHIFT)) & SIUL2_MSCR_SSS_2_MASK) 1730 1731 #define SIUL2_MSCR_SMC_MASK (0x20U) 1732 #define SIUL2_MSCR_SMC_SHIFT (5U) 1733 #define SIUL2_MSCR_SMC_WIDTH (1U) 1734 #define SIUL2_MSCR_SMC(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MSCR_SMC_SHIFT)) & SIUL2_MSCR_SMC_MASK) 1735 1736 #define SIUL2_MSCR_IFE_MASK (0x40U) 1737 #define SIUL2_MSCR_IFE_SHIFT (6U) 1738 #define SIUL2_MSCR_IFE_WIDTH (1U) 1739 #define SIUL2_MSCR_IFE(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MSCR_IFE_SHIFT)) & SIUL2_MSCR_IFE_MASK) 1740 1741 #define SIUL2_MSCR_DSE_MASK (0x100U) 1742 #define SIUL2_MSCR_DSE_SHIFT (8U) 1743 #define SIUL2_MSCR_DSE_WIDTH (1U) 1744 #define SIUL2_MSCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MSCR_DSE_SHIFT)) & SIUL2_MSCR_DSE_MASK) 1745 1746 #define SIUL2_MSCR_PUS_MASK (0x800U) 1747 #define SIUL2_MSCR_PUS_SHIFT (11U) 1748 #define SIUL2_MSCR_PUS_WIDTH (1U) 1749 #define SIUL2_MSCR_PUS(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MSCR_PUS_SHIFT)) & SIUL2_MSCR_PUS_MASK) 1750 1751 #define SIUL2_MSCR_PUE_MASK (0x2000U) 1752 #define SIUL2_MSCR_PUE_SHIFT (13U) 1753 #define SIUL2_MSCR_PUE_WIDTH (1U) 1754 #define SIUL2_MSCR_PUE(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MSCR_PUE_SHIFT)) & SIUL2_MSCR_PUE_MASK) 1755 1756 #define SIUL2_MSCR_SRC_MASK (0x4000U) 1757 #define SIUL2_MSCR_SRC_SHIFT (14U) 1758 #define SIUL2_MSCR_SRC_WIDTH (1U) 1759 #define SIUL2_MSCR_SRC(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MSCR_SRC_SHIFT)) & SIUL2_MSCR_SRC_MASK) 1760 1761 #define SIUL2_MSCR_PKE_MASK (0x10000U) 1762 #define SIUL2_MSCR_PKE_SHIFT (16U) 1763 #define SIUL2_MSCR_PKE_WIDTH (1U) 1764 #define SIUL2_MSCR_PKE(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MSCR_PKE_SHIFT)) & SIUL2_MSCR_PKE_MASK) 1765 1766 #define SIUL2_MSCR_INV_MASK (0x20000U) 1767 #define SIUL2_MSCR_INV_SHIFT (17U) 1768 #define SIUL2_MSCR_INV_WIDTH (1U) 1769 #define SIUL2_MSCR_INV(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MSCR_INV_SHIFT)) & SIUL2_MSCR_INV_MASK) 1770 1771 #define SIUL2_MSCR_IBE_MASK (0x80000U) 1772 #define SIUL2_MSCR_IBE_SHIFT (19U) 1773 #define SIUL2_MSCR_IBE_WIDTH (1U) 1774 #define SIUL2_MSCR_IBE(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MSCR_IBE_SHIFT)) & SIUL2_MSCR_IBE_MASK) 1775 1776 #define SIUL2_MSCR_OBE_MASK (0x200000U) 1777 #define SIUL2_MSCR_OBE_SHIFT (21U) 1778 #define SIUL2_MSCR_OBE_WIDTH (1U) 1779 #define SIUL2_MSCR_OBE(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MSCR_OBE_SHIFT)) & SIUL2_MSCR_OBE_MASK) 1780 /*! @} */ 1781 1782 /*! @name IMCR - SIUL2 Input Multiplexed Signal Configuration Register */ 1783 /*! @{ */ 1784 1785 #define SIUL2_IMCR_SSS_MASK (0xFU) 1786 #define SIUL2_IMCR_SSS_SHIFT (0U) 1787 #define SIUL2_IMCR_SSS_WIDTH (4U) 1788 #define SIUL2_IMCR_SSS(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IMCR_SSS_SHIFT)) & SIUL2_IMCR_SSS_MASK) 1789 /*! @} */ 1790 1791 /*! @name GPDO3 - SIUL2 GPIO Pad Data Output Register */ 1792 /*! @{ */ 1793 1794 #define SIUL2_GPDO3_PDO_n_MASK (0x1U) 1795 #define SIUL2_GPDO3_PDO_n_SHIFT (0U) 1796 #define SIUL2_GPDO3_PDO_n_WIDTH (1U) 1797 #define SIUL2_GPDO3_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO3_PDO_n_SHIFT)) & SIUL2_GPDO3_PDO_n_MASK) 1798 /*! @} */ 1799 1800 /*! @name GPDO2 - SIUL2 GPIO Pad Data Output Register */ 1801 /*! @{ */ 1802 1803 #define SIUL2_GPDO2_PDO_n_MASK (0x1U) 1804 #define SIUL2_GPDO2_PDO_n_SHIFT (0U) 1805 #define SIUL2_GPDO2_PDO_n_WIDTH (1U) 1806 #define SIUL2_GPDO2_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO2_PDO_n_SHIFT)) & SIUL2_GPDO2_PDO_n_MASK) 1807 /*! @} */ 1808 1809 /*! @name GPDO1 - SIUL2 GPIO Pad Data Output Register */ 1810 /*! @{ */ 1811 1812 #define SIUL2_GPDO1_PDO_n_MASK (0x1U) 1813 #define SIUL2_GPDO1_PDO_n_SHIFT (0U) 1814 #define SIUL2_GPDO1_PDO_n_WIDTH (1U) 1815 #define SIUL2_GPDO1_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO1_PDO_n_SHIFT)) & SIUL2_GPDO1_PDO_n_MASK) 1816 /*! @} */ 1817 1818 /*! @name GPDO0 - SIUL2 GPIO Pad Data Output Register */ 1819 /*! @{ */ 1820 1821 #define SIUL2_GPDO0_PDO_n_MASK (0x1U) 1822 #define SIUL2_GPDO0_PDO_n_SHIFT (0U) 1823 #define SIUL2_GPDO0_PDO_n_WIDTH (1U) 1824 #define SIUL2_GPDO0_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO0_PDO_n_SHIFT)) & SIUL2_GPDO0_PDO_n_MASK) 1825 /*! @} */ 1826 1827 /*! @name GPDO7 - SIUL2 GPIO Pad Data Output Register */ 1828 /*! @{ */ 1829 1830 #define SIUL2_GPDO7_PDO_n_MASK (0x1U) 1831 #define SIUL2_GPDO7_PDO_n_SHIFT (0U) 1832 #define SIUL2_GPDO7_PDO_n_WIDTH (1U) 1833 #define SIUL2_GPDO7_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO7_PDO_n_SHIFT)) & SIUL2_GPDO7_PDO_n_MASK) 1834 /*! @} */ 1835 1836 /*! @name GPDO6 - SIUL2 GPIO Pad Data Output Register */ 1837 /*! @{ */ 1838 1839 #define SIUL2_GPDO6_PDO_n_MASK (0x1U) 1840 #define SIUL2_GPDO6_PDO_n_SHIFT (0U) 1841 #define SIUL2_GPDO6_PDO_n_WIDTH (1U) 1842 #define SIUL2_GPDO6_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO6_PDO_n_SHIFT)) & SIUL2_GPDO6_PDO_n_MASK) 1843 /*! @} */ 1844 1845 /*! @name GPDO5 - SIUL2 GPIO Pad Data Output Register */ 1846 /*! @{ */ 1847 1848 #define SIUL2_GPDO5_PDO_n_MASK (0x1U) 1849 #define SIUL2_GPDO5_PDO_n_SHIFT (0U) 1850 #define SIUL2_GPDO5_PDO_n_WIDTH (1U) 1851 #define SIUL2_GPDO5_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO5_PDO_n_SHIFT)) & SIUL2_GPDO5_PDO_n_MASK) 1852 /*! @} */ 1853 1854 /*! @name GPDO4 - SIUL2 GPIO Pad Data Output Register */ 1855 /*! @{ */ 1856 1857 #define SIUL2_GPDO4_PDO_n_MASK (0x1U) 1858 #define SIUL2_GPDO4_PDO_n_SHIFT (0U) 1859 #define SIUL2_GPDO4_PDO_n_WIDTH (1U) 1860 #define SIUL2_GPDO4_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO4_PDO_n_SHIFT)) & SIUL2_GPDO4_PDO_n_MASK) 1861 /*! @} */ 1862 1863 /*! @name GPDO11 - SIUL2 GPIO Pad Data Output Register */ 1864 /*! @{ */ 1865 1866 #define SIUL2_GPDO11_PDO_n_MASK (0x1U) 1867 #define SIUL2_GPDO11_PDO_n_SHIFT (0U) 1868 #define SIUL2_GPDO11_PDO_n_WIDTH (1U) 1869 #define SIUL2_GPDO11_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO11_PDO_n_SHIFT)) & SIUL2_GPDO11_PDO_n_MASK) 1870 /*! @} */ 1871 1872 /*! @name GPDO10 - SIUL2 GPIO Pad Data Output Register */ 1873 /*! @{ */ 1874 1875 #define SIUL2_GPDO10_PDO_n_MASK (0x1U) 1876 #define SIUL2_GPDO10_PDO_n_SHIFT (0U) 1877 #define SIUL2_GPDO10_PDO_n_WIDTH (1U) 1878 #define SIUL2_GPDO10_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO10_PDO_n_SHIFT)) & SIUL2_GPDO10_PDO_n_MASK) 1879 /*! @} */ 1880 1881 /*! @name GPDO9 - SIUL2 GPIO Pad Data Output Register */ 1882 /*! @{ */ 1883 1884 #define SIUL2_GPDO9_PDO_n_MASK (0x1U) 1885 #define SIUL2_GPDO9_PDO_n_SHIFT (0U) 1886 #define SIUL2_GPDO9_PDO_n_WIDTH (1U) 1887 #define SIUL2_GPDO9_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO9_PDO_n_SHIFT)) & SIUL2_GPDO9_PDO_n_MASK) 1888 /*! @} */ 1889 1890 /*! @name GPDO8 - SIUL2 GPIO Pad Data Output Register */ 1891 /*! @{ */ 1892 1893 #define SIUL2_GPDO8_PDO_n_MASK (0x1U) 1894 #define SIUL2_GPDO8_PDO_n_SHIFT (0U) 1895 #define SIUL2_GPDO8_PDO_n_WIDTH (1U) 1896 #define SIUL2_GPDO8_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO8_PDO_n_SHIFT)) & SIUL2_GPDO8_PDO_n_MASK) 1897 /*! @} */ 1898 1899 /*! @name GPDO15 - SIUL2 GPIO Pad Data Output Register */ 1900 /*! @{ */ 1901 1902 #define SIUL2_GPDO15_PDO_n_MASK (0x1U) 1903 #define SIUL2_GPDO15_PDO_n_SHIFT (0U) 1904 #define SIUL2_GPDO15_PDO_n_WIDTH (1U) 1905 #define SIUL2_GPDO15_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO15_PDO_n_SHIFT)) & SIUL2_GPDO15_PDO_n_MASK) 1906 /*! @} */ 1907 1908 /*! @name GPDO14 - SIUL2 GPIO Pad Data Output Register */ 1909 /*! @{ */ 1910 1911 #define SIUL2_GPDO14_PDO_n_MASK (0x1U) 1912 #define SIUL2_GPDO14_PDO_n_SHIFT (0U) 1913 #define SIUL2_GPDO14_PDO_n_WIDTH (1U) 1914 #define SIUL2_GPDO14_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO14_PDO_n_SHIFT)) & SIUL2_GPDO14_PDO_n_MASK) 1915 /*! @} */ 1916 1917 /*! @name GPDO13 - SIUL2 GPIO Pad Data Output Register */ 1918 /*! @{ */ 1919 1920 #define SIUL2_GPDO13_PDO_n_MASK (0x1U) 1921 #define SIUL2_GPDO13_PDO_n_SHIFT (0U) 1922 #define SIUL2_GPDO13_PDO_n_WIDTH (1U) 1923 #define SIUL2_GPDO13_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO13_PDO_n_SHIFT)) & SIUL2_GPDO13_PDO_n_MASK) 1924 /*! @} */ 1925 1926 /*! @name GPDO12 - SIUL2 GPIO Pad Data Output Register */ 1927 /*! @{ */ 1928 1929 #define SIUL2_GPDO12_PDO_n_MASK (0x1U) 1930 #define SIUL2_GPDO12_PDO_n_SHIFT (0U) 1931 #define SIUL2_GPDO12_PDO_n_WIDTH (1U) 1932 #define SIUL2_GPDO12_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO12_PDO_n_SHIFT)) & SIUL2_GPDO12_PDO_n_MASK) 1933 /*! @} */ 1934 1935 /*! @name GPDO19 - SIUL2 GPIO Pad Data Output Register */ 1936 /*! @{ */ 1937 1938 #define SIUL2_GPDO19_PDO_n_MASK (0x1U) 1939 #define SIUL2_GPDO19_PDO_n_SHIFT (0U) 1940 #define SIUL2_GPDO19_PDO_n_WIDTH (1U) 1941 #define SIUL2_GPDO19_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO19_PDO_n_SHIFT)) & SIUL2_GPDO19_PDO_n_MASK) 1942 /*! @} */ 1943 1944 /*! @name GPDO18 - SIUL2 GPIO Pad Data Output Register */ 1945 /*! @{ */ 1946 1947 #define SIUL2_GPDO18_PDO_n_MASK (0x1U) 1948 #define SIUL2_GPDO18_PDO_n_SHIFT (0U) 1949 #define SIUL2_GPDO18_PDO_n_WIDTH (1U) 1950 #define SIUL2_GPDO18_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO18_PDO_n_SHIFT)) & SIUL2_GPDO18_PDO_n_MASK) 1951 /*! @} */ 1952 1953 /*! @name GPDO17 - SIUL2 GPIO Pad Data Output Register */ 1954 /*! @{ */ 1955 1956 #define SIUL2_GPDO17_PDO_n_MASK (0x1U) 1957 #define SIUL2_GPDO17_PDO_n_SHIFT (0U) 1958 #define SIUL2_GPDO17_PDO_n_WIDTH (1U) 1959 #define SIUL2_GPDO17_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO17_PDO_n_SHIFT)) & SIUL2_GPDO17_PDO_n_MASK) 1960 /*! @} */ 1961 1962 /*! @name GPDO16 - SIUL2 GPIO Pad Data Output Register */ 1963 /*! @{ */ 1964 1965 #define SIUL2_GPDO16_PDO_n_MASK (0x1U) 1966 #define SIUL2_GPDO16_PDO_n_SHIFT (0U) 1967 #define SIUL2_GPDO16_PDO_n_WIDTH (1U) 1968 #define SIUL2_GPDO16_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO16_PDO_n_SHIFT)) & SIUL2_GPDO16_PDO_n_MASK) 1969 /*! @} */ 1970 1971 /*! @name GPDO23 - SIUL2 GPIO Pad Data Output Register */ 1972 /*! @{ */ 1973 1974 #define SIUL2_GPDO23_PDO_n_MASK (0x1U) 1975 #define SIUL2_GPDO23_PDO_n_SHIFT (0U) 1976 #define SIUL2_GPDO23_PDO_n_WIDTH (1U) 1977 #define SIUL2_GPDO23_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO23_PDO_n_SHIFT)) & SIUL2_GPDO23_PDO_n_MASK) 1978 /*! @} */ 1979 1980 /*! @name GPDO22 - SIUL2 GPIO Pad Data Output Register */ 1981 /*! @{ */ 1982 1983 #define SIUL2_GPDO22_PDO_n_MASK (0x1U) 1984 #define SIUL2_GPDO22_PDO_n_SHIFT (0U) 1985 #define SIUL2_GPDO22_PDO_n_WIDTH (1U) 1986 #define SIUL2_GPDO22_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO22_PDO_n_SHIFT)) & SIUL2_GPDO22_PDO_n_MASK) 1987 /*! @} */ 1988 1989 /*! @name GPDO21 - SIUL2 GPIO Pad Data Output Register */ 1990 /*! @{ */ 1991 1992 #define SIUL2_GPDO21_PDO_n_MASK (0x1U) 1993 #define SIUL2_GPDO21_PDO_n_SHIFT (0U) 1994 #define SIUL2_GPDO21_PDO_n_WIDTH (1U) 1995 #define SIUL2_GPDO21_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO21_PDO_n_SHIFT)) & SIUL2_GPDO21_PDO_n_MASK) 1996 /*! @} */ 1997 1998 /*! @name GPDO20 - SIUL2 GPIO Pad Data Output Register */ 1999 /*! @{ */ 2000 2001 #define SIUL2_GPDO20_PDO_n_MASK (0x1U) 2002 #define SIUL2_GPDO20_PDO_n_SHIFT (0U) 2003 #define SIUL2_GPDO20_PDO_n_WIDTH (1U) 2004 #define SIUL2_GPDO20_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO20_PDO_n_SHIFT)) & SIUL2_GPDO20_PDO_n_MASK) 2005 /*! @} */ 2006 2007 /*! @name GPDO27 - SIUL2 GPIO Pad Data Output Register */ 2008 /*! @{ */ 2009 2010 #define SIUL2_GPDO27_PDO_n_MASK (0x1U) 2011 #define SIUL2_GPDO27_PDO_n_SHIFT (0U) 2012 #define SIUL2_GPDO27_PDO_n_WIDTH (1U) 2013 #define SIUL2_GPDO27_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO27_PDO_n_SHIFT)) & SIUL2_GPDO27_PDO_n_MASK) 2014 /*! @} */ 2015 2016 /*! @name GPDO26 - SIUL2 GPIO Pad Data Output Register */ 2017 /*! @{ */ 2018 2019 #define SIUL2_GPDO26_PDO_n_MASK (0x1U) 2020 #define SIUL2_GPDO26_PDO_n_SHIFT (0U) 2021 #define SIUL2_GPDO26_PDO_n_WIDTH (1U) 2022 #define SIUL2_GPDO26_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO26_PDO_n_SHIFT)) & SIUL2_GPDO26_PDO_n_MASK) 2023 /*! @} */ 2024 2025 /*! @name GPDO25 - SIUL2 GPIO Pad Data Output Register */ 2026 /*! @{ */ 2027 2028 #define SIUL2_GPDO25_PDO_n_MASK (0x1U) 2029 #define SIUL2_GPDO25_PDO_n_SHIFT (0U) 2030 #define SIUL2_GPDO25_PDO_n_WIDTH (1U) 2031 #define SIUL2_GPDO25_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO25_PDO_n_SHIFT)) & SIUL2_GPDO25_PDO_n_MASK) 2032 /*! @} */ 2033 2034 /*! @name GPDO24 - SIUL2 GPIO Pad Data Output Register */ 2035 /*! @{ */ 2036 2037 #define SIUL2_GPDO24_PDO_n_MASK (0x1U) 2038 #define SIUL2_GPDO24_PDO_n_SHIFT (0U) 2039 #define SIUL2_GPDO24_PDO_n_WIDTH (1U) 2040 #define SIUL2_GPDO24_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO24_PDO_n_SHIFT)) & SIUL2_GPDO24_PDO_n_MASK) 2041 /*! @} */ 2042 2043 /*! @name GPDO31 - SIUL2 GPIO Pad Data Output Register */ 2044 /*! @{ */ 2045 2046 #define SIUL2_GPDO31_PDO_n_MASK (0x1U) 2047 #define SIUL2_GPDO31_PDO_n_SHIFT (0U) 2048 #define SIUL2_GPDO31_PDO_n_WIDTH (1U) 2049 #define SIUL2_GPDO31_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO31_PDO_n_SHIFT)) & SIUL2_GPDO31_PDO_n_MASK) 2050 /*! @} */ 2051 2052 /*! @name GPDO30 - SIUL2 GPIO Pad Data Output Register */ 2053 /*! @{ */ 2054 2055 #define SIUL2_GPDO30_PDO_n_MASK (0x1U) 2056 #define SIUL2_GPDO30_PDO_n_SHIFT (0U) 2057 #define SIUL2_GPDO30_PDO_n_WIDTH (1U) 2058 #define SIUL2_GPDO30_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO30_PDO_n_SHIFT)) & SIUL2_GPDO30_PDO_n_MASK) 2059 /*! @} */ 2060 2061 /*! @name GPDO29 - SIUL2 GPIO Pad Data Output Register */ 2062 /*! @{ */ 2063 2064 #define SIUL2_GPDO29_PDO_n_MASK (0x1U) 2065 #define SIUL2_GPDO29_PDO_n_SHIFT (0U) 2066 #define SIUL2_GPDO29_PDO_n_WIDTH (1U) 2067 #define SIUL2_GPDO29_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO29_PDO_n_SHIFT)) & SIUL2_GPDO29_PDO_n_MASK) 2068 /*! @} */ 2069 2070 /*! @name GPDO28 - SIUL2 GPIO Pad Data Output Register */ 2071 /*! @{ */ 2072 2073 #define SIUL2_GPDO28_PDO_n_MASK (0x1U) 2074 #define SIUL2_GPDO28_PDO_n_SHIFT (0U) 2075 #define SIUL2_GPDO28_PDO_n_WIDTH (1U) 2076 #define SIUL2_GPDO28_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO28_PDO_n_SHIFT)) & SIUL2_GPDO28_PDO_n_MASK) 2077 /*! @} */ 2078 2079 /*! @name GPDO35 - SIUL2 GPIO Pad Data Output Register */ 2080 /*! @{ */ 2081 2082 #define SIUL2_GPDO35_PDO_n_MASK (0x1U) 2083 #define SIUL2_GPDO35_PDO_n_SHIFT (0U) 2084 #define SIUL2_GPDO35_PDO_n_WIDTH (1U) 2085 #define SIUL2_GPDO35_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO35_PDO_n_SHIFT)) & SIUL2_GPDO35_PDO_n_MASK) 2086 /*! @} */ 2087 2088 /*! @name GPDO34 - SIUL2 GPIO Pad Data Output Register */ 2089 /*! @{ */ 2090 2091 #define SIUL2_GPDO34_PDO_n_MASK (0x1U) 2092 #define SIUL2_GPDO34_PDO_n_SHIFT (0U) 2093 #define SIUL2_GPDO34_PDO_n_WIDTH (1U) 2094 #define SIUL2_GPDO34_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO34_PDO_n_SHIFT)) & SIUL2_GPDO34_PDO_n_MASK) 2095 /*! @} */ 2096 2097 /*! @name GPDO33 - SIUL2 GPIO Pad Data Output Register */ 2098 /*! @{ */ 2099 2100 #define SIUL2_GPDO33_PDO_n_MASK (0x1U) 2101 #define SIUL2_GPDO33_PDO_n_SHIFT (0U) 2102 #define SIUL2_GPDO33_PDO_n_WIDTH (1U) 2103 #define SIUL2_GPDO33_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO33_PDO_n_SHIFT)) & SIUL2_GPDO33_PDO_n_MASK) 2104 /*! @} */ 2105 2106 /*! @name GPDO32 - SIUL2 GPIO Pad Data Output Register */ 2107 /*! @{ */ 2108 2109 #define SIUL2_GPDO32_PDO_n_MASK (0x1U) 2110 #define SIUL2_GPDO32_PDO_n_SHIFT (0U) 2111 #define SIUL2_GPDO32_PDO_n_WIDTH (1U) 2112 #define SIUL2_GPDO32_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO32_PDO_n_SHIFT)) & SIUL2_GPDO32_PDO_n_MASK) 2113 /*! @} */ 2114 2115 /*! @name GPDO37 - SIUL2 GPIO Pad Data Output Register */ 2116 /*! @{ */ 2117 2118 #define SIUL2_GPDO37_PDO_n_MASK (0x1U) 2119 #define SIUL2_GPDO37_PDO_n_SHIFT (0U) 2120 #define SIUL2_GPDO37_PDO_n_WIDTH (1U) 2121 #define SIUL2_GPDO37_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO37_PDO_n_SHIFT)) & SIUL2_GPDO37_PDO_n_MASK) 2122 /*! @} */ 2123 2124 /*! @name GPDO36 - SIUL2 GPIO Pad Data Output Register */ 2125 /*! @{ */ 2126 2127 #define SIUL2_GPDO36_PDO_n_MASK (0x1U) 2128 #define SIUL2_GPDO36_PDO_n_SHIFT (0U) 2129 #define SIUL2_GPDO36_PDO_n_WIDTH (1U) 2130 #define SIUL2_GPDO36_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO36_PDO_n_SHIFT)) & SIUL2_GPDO36_PDO_n_MASK) 2131 /*! @} */ 2132 2133 /*! @name GPDO43 - SIUL2 GPIO Pad Data Output Register */ 2134 /*! @{ */ 2135 2136 #define SIUL2_GPDO43_PDO_n_MASK (0x1U) 2137 #define SIUL2_GPDO43_PDO_n_SHIFT (0U) 2138 #define SIUL2_GPDO43_PDO_n_WIDTH (1U) 2139 #define SIUL2_GPDO43_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO43_PDO_n_SHIFT)) & SIUL2_GPDO43_PDO_n_MASK) 2140 /*! @} */ 2141 2142 /*! @name GPDO42 - SIUL2 GPIO Pad Data Output Register */ 2143 /*! @{ */ 2144 2145 #define SIUL2_GPDO42_PDO_n_MASK (0x1U) 2146 #define SIUL2_GPDO42_PDO_n_SHIFT (0U) 2147 #define SIUL2_GPDO42_PDO_n_WIDTH (1U) 2148 #define SIUL2_GPDO42_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO42_PDO_n_SHIFT)) & SIUL2_GPDO42_PDO_n_MASK) 2149 /*! @} */ 2150 2151 /*! @name GPDO41 - SIUL2 GPIO Pad Data Output Register */ 2152 /*! @{ */ 2153 2154 #define SIUL2_GPDO41_PDO_n_MASK (0x1U) 2155 #define SIUL2_GPDO41_PDO_n_SHIFT (0U) 2156 #define SIUL2_GPDO41_PDO_n_WIDTH (1U) 2157 #define SIUL2_GPDO41_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO41_PDO_n_SHIFT)) & SIUL2_GPDO41_PDO_n_MASK) 2158 /*! @} */ 2159 2160 /*! @name GPDO40 - SIUL2 GPIO Pad Data Output Register */ 2161 /*! @{ */ 2162 2163 #define SIUL2_GPDO40_PDO_n_MASK (0x1U) 2164 #define SIUL2_GPDO40_PDO_n_SHIFT (0U) 2165 #define SIUL2_GPDO40_PDO_n_WIDTH (1U) 2166 #define SIUL2_GPDO40_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO40_PDO_n_SHIFT)) & SIUL2_GPDO40_PDO_n_MASK) 2167 /*! @} */ 2168 2169 /*! @name GPDO47 - SIUL2 GPIO Pad Data Output Register */ 2170 /*! @{ */ 2171 2172 #define SIUL2_GPDO47_PDO_n_MASK (0x1U) 2173 #define SIUL2_GPDO47_PDO_n_SHIFT (0U) 2174 #define SIUL2_GPDO47_PDO_n_WIDTH (1U) 2175 #define SIUL2_GPDO47_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO47_PDO_n_SHIFT)) & SIUL2_GPDO47_PDO_n_MASK) 2176 /*! @} */ 2177 2178 /*! @name GPDO46 - SIUL2 GPIO Pad Data Output Register */ 2179 /*! @{ */ 2180 2181 #define SIUL2_GPDO46_PDO_n_MASK (0x1U) 2182 #define SIUL2_GPDO46_PDO_n_SHIFT (0U) 2183 #define SIUL2_GPDO46_PDO_n_WIDTH (1U) 2184 #define SIUL2_GPDO46_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO46_PDO_n_SHIFT)) & SIUL2_GPDO46_PDO_n_MASK) 2185 /*! @} */ 2186 2187 /*! @name GPDO45 - SIUL2 GPIO Pad Data Output Register */ 2188 /*! @{ */ 2189 2190 #define SIUL2_GPDO45_PDO_n_MASK (0x1U) 2191 #define SIUL2_GPDO45_PDO_n_SHIFT (0U) 2192 #define SIUL2_GPDO45_PDO_n_WIDTH (1U) 2193 #define SIUL2_GPDO45_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO45_PDO_n_SHIFT)) & SIUL2_GPDO45_PDO_n_MASK) 2194 /*! @} */ 2195 2196 /*! @name GPDO44 - SIUL2 GPIO Pad Data Output Register */ 2197 /*! @{ */ 2198 2199 #define SIUL2_GPDO44_PDO_n_MASK (0x1U) 2200 #define SIUL2_GPDO44_PDO_n_SHIFT (0U) 2201 #define SIUL2_GPDO44_PDO_n_WIDTH (1U) 2202 #define SIUL2_GPDO44_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO44_PDO_n_SHIFT)) & SIUL2_GPDO44_PDO_n_MASK) 2203 /*! @} */ 2204 2205 /*! @name GPDO51 - SIUL2 GPIO Pad Data Output Register */ 2206 /*! @{ */ 2207 2208 #define SIUL2_GPDO51_PDO_n_MASK (0x1U) 2209 #define SIUL2_GPDO51_PDO_n_SHIFT (0U) 2210 #define SIUL2_GPDO51_PDO_n_WIDTH (1U) 2211 #define SIUL2_GPDO51_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO51_PDO_n_SHIFT)) & SIUL2_GPDO51_PDO_n_MASK) 2212 /*! @} */ 2213 2214 /*! @name GPDO50 - SIUL2 GPIO Pad Data Output Register */ 2215 /*! @{ */ 2216 2217 #define SIUL2_GPDO50_PDO_n_MASK (0x1U) 2218 #define SIUL2_GPDO50_PDO_n_SHIFT (0U) 2219 #define SIUL2_GPDO50_PDO_n_WIDTH (1U) 2220 #define SIUL2_GPDO50_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO50_PDO_n_SHIFT)) & SIUL2_GPDO50_PDO_n_MASK) 2221 /*! @} */ 2222 2223 /*! @name GPDO49 - SIUL2 GPIO Pad Data Output Register */ 2224 /*! @{ */ 2225 2226 #define SIUL2_GPDO49_PDO_n_MASK (0x1U) 2227 #define SIUL2_GPDO49_PDO_n_SHIFT (0U) 2228 #define SIUL2_GPDO49_PDO_n_WIDTH (1U) 2229 #define SIUL2_GPDO49_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO49_PDO_n_SHIFT)) & SIUL2_GPDO49_PDO_n_MASK) 2230 /*! @} */ 2231 2232 /*! @name GPDO48 - SIUL2 GPIO Pad Data Output Register */ 2233 /*! @{ */ 2234 2235 #define SIUL2_GPDO48_PDO_n_MASK (0x1U) 2236 #define SIUL2_GPDO48_PDO_n_SHIFT (0U) 2237 #define SIUL2_GPDO48_PDO_n_WIDTH (1U) 2238 #define SIUL2_GPDO48_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO48_PDO_n_SHIFT)) & SIUL2_GPDO48_PDO_n_MASK) 2239 /*! @} */ 2240 2241 /*! @name GPDO55 - SIUL2 GPIO Pad Data Output Register */ 2242 /*! @{ */ 2243 2244 #define SIUL2_GPDO55_PDO_n_MASK (0x1U) 2245 #define SIUL2_GPDO55_PDO_n_SHIFT (0U) 2246 #define SIUL2_GPDO55_PDO_n_WIDTH (1U) 2247 #define SIUL2_GPDO55_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO55_PDO_n_SHIFT)) & SIUL2_GPDO55_PDO_n_MASK) 2248 /*! @} */ 2249 2250 /*! @name GPDO54 - SIUL2 GPIO Pad Data Output Register */ 2251 /*! @{ */ 2252 2253 #define SIUL2_GPDO54_PDO_n_MASK (0x1U) 2254 #define SIUL2_GPDO54_PDO_n_SHIFT (0U) 2255 #define SIUL2_GPDO54_PDO_n_WIDTH (1U) 2256 #define SIUL2_GPDO54_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO54_PDO_n_SHIFT)) & SIUL2_GPDO54_PDO_n_MASK) 2257 /*! @} */ 2258 2259 /*! @name GPDO53 - SIUL2 GPIO Pad Data Output Register */ 2260 /*! @{ */ 2261 2262 #define SIUL2_GPDO53_PDO_n_MASK (0x1U) 2263 #define SIUL2_GPDO53_PDO_n_SHIFT (0U) 2264 #define SIUL2_GPDO53_PDO_n_WIDTH (1U) 2265 #define SIUL2_GPDO53_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO53_PDO_n_SHIFT)) & SIUL2_GPDO53_PDO_n_MASK) 2266 /*! @} */ 2267 2268 /*! @name GPDO52 - SIUL2 GPIO Pad Data Output Register */ 2269 /*! @{ */ 2270 2271 #define SIUL2_GPDO52_PDO_n_MASK (0x1U) 2272 #define SIUL2_GPDO52_PDO_n_SHIFT (0U) 2273 #define SIUL2_GPDO52_PDO_n_WIDTH (1U) 2274 #define SIUL2_GPDO52_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO52_PDO_n_SHIFT)) & SIUL2_GPDO52_PDO_n_MASK) 2275 /*! @} */ 2276 2277 /*! @name GPDO59 - SIUL2 GPIO Pad Data Output Register */ 2278 /*! @{ */ 2279 2280 #define SIUL2_GPDO59_PDO_n_MASK (0x1U) 2281 #define SIUL2_GPDO59_PDO_n_SHIFT (0U) 2282 #define SIUL2_GPDO59_PDO_n_WIDTH (1U) 2283 #define SIUL2_GPDO59_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO59_PDO_n_SHIFT)) & SIUL2_GPDO59_PDO_n_MASK) 2284 /*! @} */ 2285 2286 /*! @name GPDO58 - SIUL2 GPIO Pad Data Output Register */ 2287 /*! @{ */ 2288 2289 #define SIUL2_GPDO58_PDO_n_MASK (0x1U) 2290 #define SIUL2_GPDO58_PDO_n_SHIFT (0U) 2291 #define SIUL2_GPDO58_PDO_n_WIDTH (1U) 2292 #define SIUL2_GPDO58_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO58_PDO_n_SHIFT)) & SIUL2_GPDO58_PDO_n_MASK) 2293 /*! @} */ 2294 2295 /*! @name GPDO57 - SIUL2 GPIO Pad Data Output Register */ 2296 /*! @{ */ 2297 2298 #define SIUL2_GPDO57_PDO_n_MASK (0x1U) 2299 #define SIUL2_GPDO57_PDO_n_SHIFT (0U) 2300 #define SIUL2_GPDO57_PDO_n_WIDTH (1U) 2301 #define SIUL2_GPDO57_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO57_PDO_n_SHIFT)) & SIUL2_GPDO57_PDO_n_MASK) 2302 /*! @} */ 2303 2304 /*! @name GPDO56 - SIUL2 GPIO Pad Data Output Register */ 2305 /*! @{ */ 2306 2307 #define SIUL2_GPDO56_PDO_n_MASK (0x1U) 2308 #define SIUL2_GPDO56_PDO_n_SHIFT (0U) 2309 #define SIUL2_GPDO56_PDO_n_WIDTH (1U) 2310 #define SIUL2_GPDO56_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO56_PDO_n_SHIFT)) & SIUL2_GPDO56_PDO_n_MASK) 2311 /*! @} */ 2312 2313 /*! @name GPDO63 - SIUL2 GPIO Pad Data Output Register */ 2314 /*! @{ */ 2315 2316 #define SIUL2_GPDO63_PDO_n_MASK (0x1U) 2317 #define SIUL2_GPDO63_PDO_n_SHIFT (0U) 2318 #define SIUL2_GPDO63_PDO_n_WIDTH (1U) 2319 #define SIUL2_GPDO63_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO63_PDO_n_SHIFT)) & SIUL2_GPDO63_PDO_n_MASK) 2320 /*! @} */ 2321 2322 /*! @name GPDO62 - SIUL2 GPIO Pad Data Output Register */ 2323 /*! @{ */ 2324 2325 #define SIUL2_GPDO62_PDO_n_MASK (0x1U) 2326 #define SIUL2_GPDO62_PDO_n_SHIFT (0U) 2327 #define SIUL2_GPDO62_PDO_n_WIDTH (1U) 2328 #define SIUL2_GPDO62_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO62_PDO_n_SHIFT)) & SIUL2_GPDO62_PDO_n_MASK) 2329 /*! @} */ 2330 2331 /*! @name GPDO61 - SIUL2 GPIO Pad Data Output Register */ 2332 /*! @{ */ 2333 2334 #define SIUL2_GPDO61_PDO_n_MASK (0x1U) 2335 #define SIUL2_GPDO61_PDO_n_SHIFT (0U) 2336 #define SIUL2_GPDO61_PDO_n_WIDTH (1U) 2337 #define SIUL2_GPDO61_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO61_PDO_n_SHIFT)) & SIUL2_GPDO61_PDO_n_MASK) 2338 /*! @} */ 2339 2340 /*! @name GPDO60 - SIUL2 GPIO Pad Data Output Register */ 2341 /*! @{ */ 2342 2343 #define SIUL2_GPDO60_PDO_n_MASK (0x1U) 2344 #define SIUL2_GPDO60_PDO_n_SHIFT (0U) 2345 #define SIUL2_GPDO60_PDO_n_WIDTH (1U) 2346 #define SIUL2_GPDO60_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO60_PDO_n_SHIFT)) & SIUL2_GPDO60_PDO_n_MASK) 2347 /*! @} */ 2348 2349 /*! @name GPDO67 - SIUL2 GPIO Pad Data Output Register */ 2350 /*! @{ */ 2351 2352 #define SIUL2_GPDO67_PDO_n_MASK (0x1U) 2353 #define SIUL2_GPDO67_PDO_n_SHIFT (0U) 2354 #define SIUL2_GPDO67_PDO_n_WIDTH (1U) 2355 #define SIUL2_GPDO67_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO67_PDO_n_SHIFT)) & SIUL2_GPDO67_PDO_n_MASK) 2356 /*! @} */ 2357 2358 /*! @name GPDO66 - SIUL2 GPIO Pad Data Output Register */ 2359 /*! @{ */ 2360 2361 #define SIUL2_GPDO66_PDO_n_MASK (0x1U) 2362 #define SIUL2_GPDO66_PDO_n_SHIFT (0U) 2363 #define SIUL2_GPDO66_PDO_n_WIDTH (1U) 2364 #define SIUL2_GPDO66_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO66_PDO_n_SHIFT)) & SIUL2_GPDO66_PDO_n_MASK) 2365 /*! @} */ 2366 2367 /*! @name GPDO65 - SIUL2 GPIO Pad Data Output Register */ 2368 /*! @{ */ 2369 2370 #define SIUL2_GPDO65_PDO_n_MASK (0x1U) 2371 #define SIUL2_GPDO65_PDO_n_SHIFT (0U) 2372 #define SIUL2_GPDO65_PDO_n_WIDTH (1U) 2373 #define SIUL2_GPDO65_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO65_PDO_n_SHIFT)) & SIUL2_GPDO65_PDO_n_MASK) 2374 /*! @} */ 2375 2376 /*! @name GPDO64 - SIUL2 GPIO Pad Data Output Register */ 2377 /*! @{ */ 2378 2379 #define SIUL2_GPDO64_PDO_n_MASK (0x1U) 2380 #define SIUL2_GPDO64_PDO_n_SHIFT (0U) 2381 #define SIUL2_GPDO64_PDO_n_WIDTH (1U) 2382 #define SIUL2_GPDO64_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO64_PDO_n_SHIFT)) & SIUL2_GPDO64_PDO_n_MASK) 2383 /*! @} */ 2384 2385 /*! @name GPDO71 - SIUL2 GPIO Pad Data Output Register */ 2386 /*! @{ */ 2387 2388 #define SIUL2_GPDO71_PDO_n_MASK (0x1U) 2389 #define SIUL2_GPDO71_PDO_n_SHIFT (0U) 2390 #define SIUL2_GPDO71_PDO_n_WIDTH (1U) 2391 #define SIUL2_GPDO71_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO71_PDO_n_SHIFT)) & SIUL2_GPDO71_PDO_n_MASK) 2392 /*! @} */ 2393 2394 /*! @name GPDO70 - SIUL2 GPIO Pad Data Output Register */ 2395 /*! @{ */ 2396 2397 #define SIUL2_GPDO70_PDO_n_MASK (0x1U) 2398 #define SIUL2_GPDO70_PDO_n_SHIFT (0U) 2399 #define SIUL2_GPDO70_PDO_n_WIDTH (1U) 2400 #define SIUL2_GPDO70_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO70_PDO_n_SHIFT)) & SIUL2_GPDO70_PDO_n_MASK) 2401 /*! @} */ 2402 2403 /*! @name GPDO69 - SIUL2 GPIO Pad Data Output Register */ 2404 /*! @{ */ 2405 2406 #define SIUL2_GPDO69_PDO_n_MASK (0x1U) 2407 #define SIUL2_GPDO69_PDO_n_SHIFT (0U) 2408 #define SIUL2_GPDO69_PDO_n_WIDTH (1U) 2409 #define SIUL2_GPDO69_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO69_PDO_n_SHIFT)) & SIUL2_GPDO69_PDO_n_MASK) 2410 /*! @} */ 2411 2412 /*! @name GPDO68 - SIUL2 GPIO Pad Data Output Register */ 2413 /*! @{ */ 2414 2415 #define SIUL2_GPDO68_PDO_n_MASK (0x1U) 2416 #define SIUL2_GPDO68_PDO_n_SHIFT (0U) 2417 #define SIUL2_GPDO68_PDO_n_WIDTH (1U) 2418 #define SIUL2_GPDO68_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO68_PDO_n_SHIFT)) & SIUL2_GPDO68_PDO_n_MASK) 2419 /*! @} */ 2420 2421 /*! @name GPDO75 - SIUL2 GPIO Pad Data Output Register */ 2422 /*! @{ */ 2423 2424 #define SIUL2_GPDO75_PDO_n_MASK (0x1U) 2425 #define SIUL2_GPDO75_PDO_n_SHIFT (0U) 2426 #define SIUL2_GPDO75_PDO_n_WIDTH (1U) 2427 #define SIUL2_GPDO75_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO75_PDO_n_SHIFT)) & SIUL2_GPDO75_PDO_n_MASK) 2428 /*! @} */ 2429 2430 /*! @name GPDO74 - SIUL2 GPIO Pad Data Output Register */ 2431 /*! @{ */ 2432 2433 #define SIUL2_GPDO74_PDO_n_MASK (0x1U) 2434 #define SIUL2_GPDO74_PDO_n_SHIFT (0U) 2435 #define SIUL2_GPDO74_PDO_n_WIDTH (1U) 2436 #define SIUL2_GPDO74_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO74_PDO_n_SHIFT)) & SIUL2_GPDO74_PDO_n_MASK) 2437 /*! @} */ 2438 2439 /*! @name GPDO73 - SIUL2 GPIO Pad Data Output Register */ 2440 /*! @{ */ 2441 2442 #define SIUL2_GPDO73_PDO_n_MASK (0x1U) 2443 #define SIUL2_GPDO73_PDO_n_SHIFT (0U) 2444 #define SIUL2_GPDO73_PDO_n_WIDTH (1U) 2445 #define SIUL2_GPDO73_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO73_PDO_n_SHIFT)) & SIUL2_GPDO73_PDO_n_MASK) 2446 /*! @} */ 2447 2448 /*! @name GPDO72 - SIUL2 GPIO Pad Data Output Register */ 2449 /*! @{ */ 2450 2451 #define SIUL2_GPDO72_PDO_n_MASK (0x1U) 2452 #define SIUL2_GPDO72_PDO_n_SHIFT (0U) 2453 #define SIUL2_GPDO72_PDO_n_WIDTH (1U) 2454 #define SIUL2_GPDO72_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO72_PDO_n_SHIFT)) & SIUL2_GPDO72_PDO_n_MASK) 2455 /*! @} */ 2456 2457 /*! @name GPDO79 - SIUL2 GPIO Pad Data Output Register */ 2458 /*! @{ */ 2459 2460 #define SIUL2_GPDO79_PDO_n_MASK (0x1U) 2461 #define SIUL2_GPDO79_PDO_n_SHIFT (0U) 2462 #define SIUL2_GPDO79_PDO_n_WIDTH (1U) 2463 #define SIUL2_GPDO79_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO79_PDO_n_SHIFT)) & SIUL2_GPDO79_PDO_n_MASK) 2464 /*! @} */ 2465 2466 /*! @name GPDO78 - SIUL2 GPIO Pad Data Output Register */ 2467 /*! @{ */ 2468 2469 #define SIUL2_GPDO78_PDO_n_MASK (0x1U) 2470 #define SIUL2_GPDO78_PDO_n_SHIFT (0U) 2471 #define SIUL2_GPDO78_PDO_n_WIDTH (1U) 2472 #define SIUL2_GPDO78_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO78_PDO_n_SHIFT)) & SIUL2_GPDO78_PDO_n_MASK) 2473 /*! @} */ 2474 2475 /*! @name GPDO77 - SIUL2 GPIO Pad Data Output Register */ 2476 /*! @{ */ 2477 2478 #define SIUL2_GPDO77_PDO_n_MASK (0x1U) 2479 #define SIUL2_GPDO77_PDO_n_SHIFT (0U) 2480 #define SIUL2_GPDO77_PDO_n_WIDTH (1U) 2481 #define SIUL2_GPDO77_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO77_PDO_n_SHIFT)) & SIUL2_GPDO77_PDO_n_MASK) 2482 /*! @} */ 2483 2484 /*! @name GPDO76 - SIUL2 GPIO Pad Data Output Register */ 2485 /*! @{ */ 2486 2487 #define SIUL2_GPDO76_PDO_n_MASK (0x1U) 2488 #define SIUL2_GPDO76_PDO_n_SHIFT (0U) 2489 #define SIUL2_GPDO76_PDO_n_WIDTH (1U) 2490 #define SIUL2_GPDO76_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO76_PDO_n_SHIFT)) & SIUL2_GPDO76_PDO_n_MASK) 2491 /*! @} */ 2492 2493 /*! @name GPDO83 - SIUL2 GPIO Pad Data Output Register */ 2494 /*! @{ */ 2495 2496 #define SIUL2_GPDO83_PDO_n_MASK (0x1U) 2497 #define SIUL2_GPDO83_PDO_n_SHIFT (0U) 2498 #define SIUL2_GPDO83_PDO_n_WIDTH (1U) 2499 #define SIUL2_GPDO83_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO83_PDO_n_SHIFT)) & SIUL2_GPDO83_PDO_n_MASK) 2500 /*! @} */ 2501 2502 /*! @name GPDO82 - SIUL2 GPIO Pad Data Output Register */ 2503 /*! @{ */ 2504 2505 #define SIUL2_GPDO82_PDO_n_MASK (0x1U) 2506 #define SIUL2_GPDO82_PDO_n_SHIFT (0U) 2507 #define SIUL2_GPDO82_PDO_n_WIDTH (1U) 2508 #define SIUL2_GPDO82_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO82_PDO_n_SHIFT)) & SIUL2_GPDO82_PDO_n_MASK) 2509 /*! @} */ 2510 2511 /*! @name GPDO81 - SIUL2 GPIO Pad Data Output Register */ 2512 /*! @{ */ 2513 2514 #define SIUL2_GPDO81_PDO_n_MASK (0x1U) 2515 #define SIUL2_GPDO81_PDO_n_SHIFT (0U) 2516 #define SIUL2_GPDO81_PDO_n_WIDTH (1U) 2517 #define SIUL2_GPDO81_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO81_PDO_n_SHIFT)) & SIUL2_GPDO81_PDO_n_MASK) 2518 /*! @} */ 2519 2520 /*! @name GPDO80 - SIUL2 GPIO Pad Data Output Register */ 2521 /*! @{ */ 2522 2523 #define SIUL2_GPDO80_PDO_n_MASK (0x1U) 2524 #define SIUL2_GPDO80_PDO_n_SHIFT (0U) 2525 #define SIUL2_GPDO80_PDO_n_WIDTH (1U) 2526 #define SIUL2_GPDO80_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO80_PDO_n_SHIFT)) & SIUL2_GPDO80_PDO_n_MASK) 2527 /*! @} */ 2528 2529 /*! @name GPDO87 - SIUL2 GPIO Pad Data Output Register */ 2530 /*! @{ */ 2531 2532 #define SIUL2_GPDO87_PDO_n_MASK (0x1U) 2533 #define SIUL2_GPDO87_PDO_n_SHIFT (0U) 2534 #define SIUL2_GPDO87_PDO_n_WIDTH (1U) 2535 #define SIUL2_GPDO87_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO87_PDO_n_SHIFT)) & SIUL2_GPDO87_PDO_n_MASK) 2536 /*! @} */ 2537 2538 /*! @name GPDO86 - SIUL2 GPIO Pad Data Output Register */ 2539 /*! @{ */ 2540 2541 #define SIUL2_GPDO86_PDO_n_MASK (0x1U) 2542 #define SIUL2_GPDO86_PDO_n_SHIFT (0U) 2543 #define SIUL2_GPDO86_PDO_n_WIDTH (1U) 2544 #define SIUL2_GPDO86_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO86_PDO_n_SHIFT)) & SIUL2_GPDO86_PDO_n_MASK) 2545 /*! @} */ 2546 2547 /*! @name GPDO85 - SIUL2 GPIO Pad Data Output Register */ 2548 /*! @{ */ 2549 2550 #define SIUL2_GPDO85_PDO_n_MASK (0x1U) 2551 #define SIUL2_GPDO85_PDO_n_SHIFT (0U) 2552 #define SIUL2_GPDO85_PDO_n_WIDTH (1U) 2553 #define SIUL2_GPDO85_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO85_PDO_n_SHIFT)) & SIUL2_GPDO85_PDO_n_MASK) 2554 /*! @} */ 2555 2556 /*! @name GPDO84 - SIUL2 GPIO Pad Data Output Register */ 2557 /*! @{ */ 2558 2559 #define SIUL2_GPDO84_PDO_n_MASK (0x1U) 2560 #define SIUL2_GPDO84_PDO_n_SHIFT (0U) 2561 #define SIUL2_GPDO84_PDO_n_WIDTH (1U) 2562 #define SIUL2_GPDO84_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO84_PDO_n_SHIFT)) & SIUL2_GPDO84_PDO_n_MASK) 2563 /*! @} */ 2564 2565 /*! @name GPDO91 - SIUL2 GPIO Pad Data Output Register */ 2566 /*! @{ */ 2567 2568 #define SIUL2_GPDO91_PDO_n_MASK (0x1U) 2569 #define SIUL2_GPDO91_PDO_n_SHIFT (0U) 2570 #define SIUL2_GPDO91_PDO_n_WIDTH (1U) 2571 #define SIUL2_GPDO91_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO91_PDO_n_SHIFT)) & SIUL2_GPDO91_PDO_n_MASK) 2572 /*! @} */ 2573 2574 /*! @name GPDO90 - SIUL2 GPIO Pad Data Output Register */ 2575 /*! @{ */ 2576 2577 #define SIUL2_GPDO90_PDO_n_MASK (0x1U) 2578 #define SIUL2_GPDO90_PDO_n_SHIFT (0U) 2579 #define SIUL2_GPDO90_PDO_n_WIDTH (1U) 2580 #define SIUL2_GPDO90_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO90_PDO_n_SHIFT)) & SIUL2_GPDO90_PDO_n_MASK) 2581 /*! @} */ 2582 2583 /*! @name GPDO89 - SIUL2 GPIO Pad Data Output Register */ 2584 /*! @{ */ 2585 2586 #define SIUL2_GPDO89_PDO_n_MASK (0x1U) 2587 #define SIUL2_GPDO89_PDO_n_SHIFT (0U) 2588 #define SIUL2_GPDO89_PDO_n_WIDTH (1U) 2589 #define SIUL2_GPDO89_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO89_PDO_n_SHIFT)) & SIUL2_GPDO89_PDO_n_MASK) 2590 /*! @} */ 2591 2592 /*! @name GPDO88 - SIUL2 GPIO Pad Data Output Register */ 2593 /*! @{ */ 2594 2595 #define SIUL2_GPDO88_PDO_n_MASK (0x1U) 2596 #define SIUL2_GPDO88_PDO_n_SHIFT (0U) 2597 #define SIUL2_GPDO88_PDO_n_WIDTH (1U) 2598 #define SIUL2_GPDO88_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO88_PDO_n_SHIFT)) & SIUL2_GPDO88_PDO_n_MASK) 2599 /*! @} */ 2600 2601 /*! @name GPDO95 - SIUL2 GPIO Pad Data Output Register */ 2602 /*! @{ */ 2603 2604 #define SIUL2_GPDO95_PDO_n_MASK (0x1U) 2605 #define SIUL2_GPDO95_PDO_n_SHIFT (0U) 2606 #define SIUL2_GPDO95_PDO_n_WIDTH (1U) 2607 #define SIUL2_GPDO95_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO95_PDO_n_SHIFT)) & SIUL2_GPDO95_PDO_n_MASK) 2608 /*! @} */ 2609 2610 /*! @name GPDO94 - SIUL2 GPIO Pad Data Output Register */ 2611 /*! @{ */ 2612 2613 #define SIUL2_GPDO94_PDO_n_MASK (0x1U) 2614 #define SIUL2_GPDO94_PDO_n_SHIFT (0U) 2615 #define SIUL2_GPDO94_PDO_n_WIDTH (1U) 2616 #define SIUL2_GPDO94_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO94_PDO_n_SHIFT)) & SIUL2_GPDO94_PDO_n_MASK) 2617 /*! @} */ 2618 2619 /*! @name GPDO93 - SIUL2 GPIO Pad Data Output Register */ 2620 /*! @{ */ 2621 2622 #define SIUL2_GPDO93_PDO_n_MASK (0x1U) 2623 #define SIUL2_GPDO93_PDO_n_SHIFT (0U) 2624 #define SIUL2_GPDO93_PDO_n_WIDTH (1U) 2625 #define SIUL2_GPDO93_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO93_PDO_n_SHIFT)) & SIUL2_GPDO93_PDO_n_MASK) 2626 /*! @} */ 2627 2628 /*! @name GPDO92 - SIUL2 GPIO Pad Data Output Register */ 2629 /*! @{ */ 2630 2631 #define SIUL2_GPDO92_PDO_n_MASK (0x1U) 2632 #define SIUL2_GPDO92_PDO_n_SHIFT (0U) 2633 #define SIUL2_GPDO92_PDO_n_WIDTH (1U) 2634 #define SIUL2_GPDO92_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO92_PDO_n_SHIFT)) & SIUL2_GPDO92_PDO_n_MASK) 2635 /*! @} */ 2636 2637 /*! @name GPDO99 - SIUL2 GPIO Pad Data Output Register */ 2638 /*! @{ */ 2639 2640 #define SIUL2_GPDO99_PDO_n_MASK (0x1U) 2641 #define SIUL2_GPDO99_PDO_n_SHIFT (0U) 2642 #define SIUL2_GPDO99_PDO_n_WIDTH (1U) 2643 #define SIUL2_GPDO99_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO99_PDO_n_SHIFT)) & SIUL2_GPDO99_PDO_n_MASK) 2644 /*! @} */ 2645 2646 /*! @name GPDO98 - SIUL2 GPIO Pad Data Output Register */ 2647 /*! @{ */ 2648 2649 #define SIUL2_GPDO98_PDO_n_MASK (0x1U) 2650 #define SIUL2_GPDO98_PDO_n_SHIFT (0U) 2651 #define SIUL2_GPDO98_PDO_n_WIDTH (1U) 2652 #define SIUL2_GPDO98_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO98_PDO_n_SHIFT)) & SIUL2_GPDO98_PDO_n_MASK) 2653 /*! @} */ 2654 2655 /*! @name GPDO97 - SIUL2 GPIO Pad Data Output Register */ 2656 /*! @{ */ 2657 2658 #define SIUL2_GPDO97_PDO_n_MASK (0x1U) 2659 #define SIUL2_GPDO97_PDO_n_SHIFT (0U) 2660 #define SIUL2_GPDO97_PDO_n_WIDTH (1U) 2661 #define SIUL2_GPDO97_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO97_PDO_n_SHIFT)) & SIUL2_GPDO97_PDO_n_MASK) 2662 /*! @} */ 2663 2664 /*! @name GPDO96 - SIUL2 GPIO Pad Data Output Register */ 2665 /*! @{ */ 2666 2667 #define SIUL2_GPDO96_PDO_n_MASK (0x1U) 2668 #define SIUL2_GPDO96_PDO_n_SHIFT (0U) 2669 #define SIUL2_GPDO96_PDO_n_WIDTH (1U) 2670 #define SIUL2_GPDO96_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO96_PDO_n_SHIFT)) & SIUL2_GPDO96_PDO_n_MASK) 2671 /*! @} */ 2672 2673 /*! @name GPDO103 - SIUL2 GPIO Pad Data Output Register */ 2674 /*! @{ */ 2675 2676 #define SIUL2_GPDO103_PDO_n_MASK (0x1U) 2677 #define SIUL2_GPDO103_PDO_n_SHIFT (0U) 2678 #define SIUL2_GPDO103_PDO_n_WIDTH (1U) 2679 #define SIUL2_GPDO103_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO103_PDO_n_SHIFT)) & SIUL2_GPDO103_PDO_n_MASK) 2680 /*! @} */ 2681 2682 /*! @name GPDO102 - SIUL2 GPIO Pad Data Output Register */ 2683 /*! @{ */ 2684 2685 #define SIUL2_GPDO102_PDO_n_MASK (0x1U) 2686 #define SIUL2_GPDO102_PDO_n_SHIFT (0U) 2687 #define SIUL2_GPDO102_PDO_n_WIDTH (1U) 2688 #define SIUL2_GPDO102_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO102_PDO_n_SHIFT)) & SIUL2_GPDO102_PDO_n_MASK) 2689 /*! @} */ 2690 2691 /*! @name GPDO101 - SIUL2 GPIO Pad Data Output Register */ 2692 /*! @{ */ 2693 2694 #define SIUL2_GPDO101_PDO_n_MASK (0x1U) 2695 #define SIUL2_GPDO101_PDO_n_SHIFT (0U) 2696 #define SIUL2_GPDO101_PDO_n_WIDTH (1U) 2697 #define SIUL2_GPDO101_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO101_PDO_n_SHIFT)) & SIUL2_GPDO101_PDO_n_MASK) 2698 /*! @} */ 2699 2700 /*! @name GPDO100 - SIUL2 GPIO Pad Data Output Register */ 2701 /*! @{ */ 2702 2703 #define SIUL2_GPDO100_PDO_n_MASK (0x1U) 2704 #define SIUL2_GPDO100_PDO_n_SHIFT (0U) 2705 #define SIUL2_GPDO100_PDO_n_WIDTH (1U) 2706 #define SIUL2_GPDO100_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO100_PDO_n_SHIFT)) & SIUL2_GPDO100_PDO_n_MASK) 2707 /*! @} */ 2708 2709 /*! @name GPDO107 - SIUL2 GPIO Pad Data Output Register */ 2710 /*! @{ */ 2711 2712 #define SIUL2_GPDO107_PDO_n_MASK (0x1U) 2713 #define SIUL2_GPDO107_PDO_n_SHIFT (0U) 2714 #define SIUL2_GPDO107_PDO_n_WIDTH (1U) 2715 #define SIUL2_GPDO107_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO107_PDO_n_SHIFT)) & SIUL2_GPDO107_PDO_n_MASK) 2716 /*! @} */ 2717 2718 /*! @name GPDO106 - SIUL2 GPIO Pad Data Output Register */ 2719 /*! @{ */ 2720 2721 #define SIUL2_GPDO106_PDO_n_MASK (0x1U) 2722 #define SIUL2_GPDO106_PDO_n_SHIFT (0U) 2723 #define SIUL2_GPDO106_PDO_n_WIDTH (1U) 2724 #define SIUL2_GPDO106_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO106_PDO_n_SHIFT)) & SIUL2_GPDO106_PDO_n_MASK) 2725 /*! @} */ 2726 2727 /*! @name GPDO105 - SIUL2 GPIO Pad Data Output Register */ 2728 /*! @{ */ 2729 2730 #define SIUL2_GPDO105_PDO_n_MASK (0x1U) 2731 #define SIUL2_GPDO105_PDO_n_SHIFT (0U) 2732 #define SIUL2_GPDO105_PDO_n_WIDTH (1U) 2733 #define SIUL2_GPDO105_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO105_PDO_n_SHIFT)) & SIUL2_GPDO105_PDO_n_MASK) 2734 /*! @} */ 2735 2736 /*! @name GPDO104 - SIUL2 GPIO Pad Data Output Register */ 2737 /*! @{ */ 2738 2739 #define SIUL2_GPDO104_PDO_n_MASK (0x1U) 2740 #define SIUL2_GPDO104_PDO_n_SHIFT (0U) 2741 #define SIUL2_GPDO104_PDO_n_WIDTH (1U) 2742 #define SIUL2_GPDO104_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO104_PDO_n_SHIFT)) & SIUL2_GPDO104_PDO_n_MASK) 2743 /*! @} */ 2744 2745 /*! @name GPDO111 - SIUL2 GPIO Pad Data Output Register */ 2746 /*! @{ */ 2747 2748 #define SIUL2_GPDO111_PDO_n_MASK (0x1U) 2749 #define SIUL2_GPDO111_PDO_n_SHIFT (0U) 2750 #define SIUL2_GPDO111_PDO_n_WIDTH (1U) 2751 #define SIUL2_GPDO111_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO111_PDO_n_SHIFT)) & SIUL2_GPDO111_PDO_n_MASK) 2752 /*! @} */ 2753 2754 /*! @name GPDO110 - SIUL2 GPIO Pad Data Output Register */ 2755 /*! @{ */ 2756 2757 #define SIUL2_GPDO110_PDO_n_MASK (0x1U) 2758 #define SIUL2_GPDO110_PDO_n_SHIFT (0U) 2759 #define SIUL2_GPDO110_PDO_n_WIDTH (1U) 2760 #define SIUL2_GPDO110_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO110_PDO_n_SHIFT)) & SIUL2_GPDO110_PDO_n_MASK) 2761 /*! @} */ 2762 2763 /*! @name GPDO109 - SIUL2 GPIO Pad Data Output Register */ 2764 /*! @{ */ 2765 2766 #define SIUL2_GPDO109_PDO_n_MASK (0x1U) 2767 #define SIUL2_GPDO109_PDO_n_SHIFT (0U) 2768 #define SIUL2_GPDO109_PDO_n_WIDTH (1U) 2769 #define SIUL2_GPDO109_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO109_PDO_n_SHIFT)) & SIUL2_GPDO109_PDO_n_MASK) 2770 /*! @} */ 2771 2772 /*! @name GPDO108 - SIUL2 GPIO Pad Data Output Register */ 2773 /*! @{ */ 2774 2775 #define SIUL2_GPDO108_PDO_n_MASK (0x1U) 2776 #define SIUL2_GPDO108_PDO_n_SHIFT (0U) 2777 #define SIUL2_GPDO108_PDO_n_WIDTH (1U) 2778 #define SIUL2_GPDO108_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO108_PDO_n_SHIFT)) & SIUL2_GPDO108_PDO_n_MASK) 2779 /*! @} */ 2780 2781 /*! @name GPDO115 - SIUL2 GPIO Pad Data Output Register */ 2782 /*! @{ */ 2783 2784 #define SIUL2_GPDO115_PDO_n_MASK (0x1U) 2785 #define SIUL2_GPDO115_PDO_n_SHIFT (0U) 2786 #define SIUL2_GPDO115_PDO_n_WIDTH (1U) 2787 #define SIUL2_GPDO115_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO115_PDO_n_SHIFT)) & SIUL2_GPDO115_PDO_n_MASK) 2788 /*! @} */ 2789 2790 /*! @name GPDO114 - SIUL2 GPIO Pad Data Output Register */ 2791 /*! @{ */ 2792 2793 #define SIUL2_GPDO114_PDO_n_MASK (0x1U) 2794 #define SIUL2_GPDO114_PDO_n_SHIFT (0U) 2795 #define SIUL2_GPDO114_PDO_n_WIDTH (1U) 2796 #define SIUL2_GPDO114_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO114_PDO_n_SHIFT)) & SIUL2_GPDO114_PDO_n_MASK) 2797 /*! @} */ 2798 2799 /*! @name GPDO113 - SIUL2 GPIO Pad Data Output Register */ 2800 /*! @{ */ 2801 2802 #define SIUL2_GPDO113_PDO_n_MASK (0x1U) 2803 #define SIUL2_GPDO113_PDO_n_SHIFT (0U) 2804 #define SIUL2_GPDO113_PDO_n_WIDTH (1U) 2805 #define SIUL2_GPDO113_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO113_PDO_n_SHIFT)) & SIUL2_GPDO113_PDO_n_MASK) 2806 /*! @} */ 2807 2808 /*! @name GPDO112 - SIUL2 GPIO Pad Data Output Register */ 2809 /*! @{ */ 2810 2811 #define SIUL2_GPDO112_PDO_n_MASK (0x1U) 2812 #define SIUL2_GPDO112_PDO_n_SHIFT (0U) 2813 #define SIUL2_GPDO112_PDO_n_WIDTH (1U) 2814 #define SIUL2_GPDO112_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO112_PDO_n_SHIFT)) & SIUL2_GPDO112_PDO_n_MASK) 2815 /*! @} */ 2816 2817 /*! @name GPDO119 - SIUL2 GPIO Pad Data Output Register */ 2818 /*! @{ */ 2819 2820 #define SIUL2_GPDO119_PDO_n_MASK (0x1U) 2821 #define SIUL2_GPDO119_PDO_n_SHIFT (0U) 2822 #define SIUL2_GPDO119_PDO_n_WIDTH (1U) 2823 #define SIUL2_GPDO119_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO119_PDO_n_SHIFT)) & SIUL2_GPDO119_PDO_n_MASK) 2824 /*! @} */ 2825 2826 /*! @name GPDO118 - SIUL2 GPIO Pad Data Output Register */ 2827 /*! @{ */ 2828 2829 #define SIUL2_GPDO118_PDO_n_MASK (0x1U) 2830 #define SIUL2_GPDO118_PDO_n_SHIFT (0U) 2831 #define SIUL2_GPDO118_PDO_n_WIDTH (1U) 2832 #define SIUL2_GPDO118_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO118_PDO_n_SHIFT)) & SIUL2_GPDO118_PDO_n_MASK) 2833 /*! @} */ 2834 2835 /*! @name GPDO117 - SIUL2 GPIO Pad Data Output Register */ 2836 /*! @{ */ 2837 2838 #define SIUL2_GPDO117_PDO_n_MASK (0x1U) 2839 #define SIUL2_GPDO117_PDO_n_SHIFT (0U) 2840 #define SIUL2_GPDO117_PDO_n_WIDTH (1U) 2841 #define SIUL2_GPDO117_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO117_PDO_n_SHIFT)) & SIUL2_GPDO117_PDO_n_MASK) 2842 /*! @} */ 2843 2844 /*! @name GPDO116 - SIUL2 GPIO Pad Data Output Register */ 2845 /*! @{ */ 2846 2847 #define SIUL2_GPDO116_PDO_n_MASK (0x1U) 2848 #define SIUL2_GPDO116_PDO_n_SHIFT (0U) 2849 #define SIUL2_GPDO116_PDO_n_WIDTH (1U) 2850 #define SIUL2_GPDO116_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO116_PDO_n_SHIFT)) & SIUL2_GPDO116_PDO_n_MASK) 2851 /*! @} */ 2852 2853 /*! @name GPDO123 - SIUL2 GPIO Pad Data Output Register */ 2854 /*! @{ */ 2855 2856 #define SIUL2_GPDO123_PDO_n_MASK (0x1U) 2857 #define SIUL2_GPDO123_PDO_n_SHIFT (0U) 2858 #define SIUL2_GPDO123_PDO_n_WIDTH (1U) 2859 #define SIUL2_GPDO123_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO123_PDO_n_SHIFT)) & SIUL2_GPDO123_PDO_n_MASK) 2860 /*! @} */ 2861 2862 /*! @name GPDO122 - SIUL2 GPIO Pad Data Output Register */ 2863 /*! @{ */ 2864 2865 #define SIUL2_GPDO122_PDO_n_MASK (0x1U) 2866 #define SIUL2_GPDO122_PDO_n_SHIFT (0U) 2867 #define SIUL2_GPDO122_PDO_n_WIDTH (1U) 2868 #define SIUL2_GPDO122_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO122_PDO_n_SHIFT)) & SIUL2_GPDO122_PDO_n_MASK) 2869 /*! @} */ 2870 2871 /*! @name GPDO121 - SIUL2 GPIO Pad Data Output Register */ 2872 /*! @{ */ 2873 2874 #define SIUL2_GPDO121_PDO_n_MASK (0x1U) 2875 #define SIUL2_GPDO121_PDO_n_SHIFT (0U) 2876 #define SIUL2_GPDO121_PDO_n_WIDTH (1U) 2877 #define SIUL2_GPDO121_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO121_PDO_n_SHIFT)) & SIUL2_GPDO121_PDO_n_MASK) 2878 /*! @} */ 2879 2880 /*! @name GPDO120 - SIUL2 GPIO Pad Data Output Register */ 2881 /*! @{ */ 2882 2883 #define SIUL2_GPDO120_PDO_n_MASK (0x1U) 2884 #define SIUL2_GPDO120_PDO_n_SHIFT (0U) 2885 #define SIUL2_GPDO120_PDO_n_WIDTH (1U) 2886 #define SIUL2_GPDO120_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO120_PDO_n_SHIFT)) & SIUL2_GPDO120_PDO_n_MASK) 2887 /*! @} */ 2888 2889 /*! @name GPDO127 - SIUL2 GPIO Pad Data Output Register */ 2890 /*! @{ */ 2891 2892 #define SIUL2_GPDO127_PDO_n_MASK (0x1U) 2893 #define SIUL2_GPDO127_PDO_n_SHIFT (0U) 2894 #define SIUL2_GPDO127_PDO_n_WIDTH (1U) 2895 #define SIUL2_GPDO127_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO127_PDO_n_SHIFT)) & SIUL2_GPDO127_PDO_n_MASK) 2896 /*! @} */ 2897 2898 /*! @name GPDO126 - SIUL2 GPIO Pad Data Output Register */ 2899 /*! @{ */ 2900 2901 #define SIUL2_GPDO126_PDO_n_MASK (0x1U) 2902 #define SIUL2_GPDO126_PDO_n_SHIFT (0U) 2903 #define SIUL2_GPDO126_PDO_n_WIDTH (1U) 2904 #define SIUL2_GPDO126_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO126_PDO_n_SHIFT)) & SIUL2_GPDO126_PDO_n_MASK) 2905 /*! @} */ 2906 2907 /*! @name GPDO125 - SIUL2 GPIO Pad Data Output Register */ 2908 /*! @{ */ 2909 2910 #define SIUL2_GPDO125_PDO_n_MASK (0x1U) 2911 #define SIUL2_GPDO125_PDO_n_SHIFT (0U) 2912 #define SIUL2_GPDO125_PDO_n_WIDTH (1U) 2913 #define SIUL2_GPDO125_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO125_PDO_n_SHIFT)) & SIUL2_GPDO125_PDO_n_MASK) 2914 /*! @} */ 2915 2916 /*! @name GPDO124 - SIUL2 GPIO Pad Data Output Register */ 2917 /*! @{ */ 2918 2919 #define SIUL2_GPDO124_PDO_n_MASK (0x1U) 2920 #define SIUL2_GPDO124_PDO_n_SHIFT (0U) 2921 #define SIUL2_GPDO124_PDO_n_WIDTH (1U) 2922 #define SIUL2_GPDO124_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO124_PDO_n_SHIFT)) & SIUL2_GPDO124_PDO_n_MASK) 2923 /*! @} */ 2924 2925 /*! @name GPDO131 - SIUL2 GPIO Pad Data Output Register */ 2926 /*! @{ */ 2927 2928 #define SIUL2_GPDO131_PDO_n_MASK (0x1U) 2929 #define SIUL2_GPDO131_PDO_n_SHIFT (0U) 2930 #define SIUL2_GPDO131_PDO_n_WIDTH (1U) 2931 #define SIUL2_GPDO131_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO131_PDO_n_SHIFT)) & SIUL2_GPDO131_PDO_n_MASK) 2932 /*! @} */ 2933 2934 /*! @name GPDO130 - SIUL2 GPIO Pad Data Output Register */ 2935 /*! @{ */ 2936 2937 #define SIUL2_GPDO130_PDO_n_MASK (0x1U) 2938 #define SIUL2_GPDO130_PDO_n_SHIFT (0U) 2939 #define SIUL2_GPDO130_PDO_n_WIDTH (1U) 2940 #define SIUL2_GPDO130_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO130_PDO_n_SHIFT)) & SIUL2_GPDO130_PDO_n_MASK) 2941 /*! @} */ 2942 2943 /*! @name GPDO129 - SIUL2 GPIO Pad Data Output Register */ 2944 /*! @{ */ 2945 2946 #define SIUL2_GPDO129_PDO_n_MASK (0x1U) 2947 #define SIUL2_GPDO129_PDO_n_SHIFT (0U) 2948 #define SIUL2_GPDO129_PDO_n_WIDTH (1U) 2949 #define SIUL2_GPDO129_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO129_PDO_n_SHIFT)) & SIUL2_GPDO129_PDO_n_MASK) 2950 /*! @} */ 2951 2952 /*! @name GPDO128 - SIUL2 GPIO Pad Data Output Register */ 2953 /*! @{ */ 2954 2955 #define SIUL2_GPDO128_PDO_n_MASK (0x1U) 2956 #define SIUL2_GPDO128_PDO_n_SHIFT (0U) 2957 #define SIUL2_GPDO128_PDO_n_WIDTH (1U) 2958 #define SIUL2_GPDO128_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO128_PDO_n_SHIFT)) & SIUL2_GPDO128_PDO_n_MASK) 2959 /*! @} */ 2960 2961 /*! @name GPDO135 - SIUL2 GPIO Pad Data Output Register */ 2962 /*! @{ */ 2963 2964 #define SIUL2_GPDO135_PDO_n_MASK (0x1U) 2965 #define SIUL2_GPDO135_PDO_n_SHIFT (0U) 2966 #define SIUL2_GPDO135_PDO_n_WIDTH (1U) 2967 #define SIUL2_GPDO135_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO135_PDO_n_SHIFT)) & SIUL2_GPDO135_PDO_n_MASK) 2968 /*! @} */ 2969 2970 /*! @name GPDO134 - SIUL2 GPIO Pad Data Output Register */ 2971 /*! @{ */ 2972 2973 #define SIUL2_GPDO134_PDO_n_MASK (0x1U) 2974 #define SIUL2_GPDO134_PDO_n_SHIFT (0U) 2975 #define SIUL2_GPDO134_PDO_n_WIDTH (1U) 2976 #define SIUL2_GPDO134_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO134_PDO_n_SHIFT)) & SIUL2_GPDO134_PDO_n_MASK) 2977 /*! @} */ 2978 2979 /*! @name GPDO133 - SIUL2 GPIO Pad Data Output Register */ 2980 /*! @{ */ 2981 2982 #define SIUL2_GPDO133_PDO_n_MASK (0x1U) 2983 #define SIUL2_GPDO133_PDO_n_SHIFT (0U) 2984 #define SIUL2_GPDO133_PDO_n_WIDTH (1U) 2985 #define SIUL2_GPDO133_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO133_PDO_n_SHIFT)) & SIUL2_GPDO133_PDO_n_MASK) 2986 /*! @} */ 2987 2988 /*! @name GPDO132 - SIUL2 GPIO Pad Data Output Register */ 2989 /*! @{ */ 2990 2991 #define SIUL2_GPDO132_PDO_n_MASK (0x1U) 2992 #define SIUL2_GPDO132_PDO_n_SHIFT (0U) 2993 #define SIUL2_GPDO132_PDO_n_WIDTH (1U) 2994 #define SIUL2_GPDO132_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO132_PDO_n_SHIFT)) & SIUL2_GPDO132_PDO_n_MASK) 2995 /*! @} */ 2996 2997 /*! @name GPDO139 - SIUL2 GPIO Pad Data Output Register */ 2998 /*! @{ */ 2999 3000 #define SIUL2_GPDO139_PDO_n_MASK (0x1U) 3001 #define SIUL2_GPDO139_PDO_n_SHIFT (0U) 3002 #define SIUL2_GPDO139_PDO_n_WIDTH (1U) 3003 #define SIUL2_GPDO139_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO139_PDO_n_SHIFT)) & SIUL2_GPDO139_PDO_n_MASK) 3004 /*! @} */ 3005 3006 /*! @name GPDO138 - SIUL2 GPIO Pad Data Output Register */ 3007 /*! @{ */ 3008 3009 #define SIUL2_GPDO138_PDO_n_MASK (0x1U) 3010 #define SIUL2_GPDO138_PDO_n_SHIFT (0U) 3011 #define SIUL2_GPDO138_PDO_n_WIDTH (1U) 3012 #define SIUL2_GPDO138_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO138_PDO_n_SHIFT)) & SIUL2_GPDO138_PDO_n_MASK) 3013 /*! @} */ 3014 3015 /*! @name GPDO137 - SIUL2 GPIO Pad Data Output Register */ 3016 /*! @{ */ 3017 3018 #define SIUL2_GPDO137_PDO_n_MASK (0x1U) 3019 #define SIUL2_GPDO137_PDO_n_SHIFT (0U) 3020 #define SIUL2_GPDO137_PDO_n_WIDTH (1U) 3021 #define SIUL2_GPDO137_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO137_PDO_n_SHIFT)) & SIUL2_GPDO137_PDO_n_MASK) 3022 /*! @} */ 3023 3024 /*! @name GPDO136 - SIUL2 GPIO Pad Data Output Register */ 3025 /*! @{ */ 3026 3027 #define SIUL2_GPDO136_PDO_n_MASK (0x1U) 3028 #define SIUL2_GPDO136_PDO_n_SHIFT (0U) 3029 #define SIUL2_GPDO136_PDO_n_WIDTH (1U) 3030 #define SIUL2_GPDO136_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO136_PDO_n_SHIFT)) & SIUL2_GPDO136_PDO_n_MASK) 3031 /*! @} */ 3032 3033 /*! @name GPDO143 - SIUL2 GPIO Pad Data Output Register */ 3034 /*! @{ */ 3035 3036 #define SIUL2_GPDO143_PDO_n_MASK (0x1U) 3037 #define SIUL2_GPDO143_PDO_n_SHIFT (0U) 3038 #define SIUL2_GPDO143_PDO_n_WIDTH (1U) 3039 #define SIUL2_GPDO143_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO143_PDO_n_SHIFT)) & SIUL2_GPDO143_PDO_n_MASK) 3040 /*! @} */ 3041 3042 /*! @name GPDO142 - SIUL2 GPIO Pad Data Output Register */ 3043 /*! @{ */ 3044 3045 #define SIUL2_GPDO142_PDO_n_MASK (0x1U) 3046 #define SIUL2_GPDO142_PDO_n_SHIFT (0U) 3047 #define SIUL2_GPDO142_PDO_n_WIDTH (1U) 3048 #define SIUL2_GPDO142_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO142_PDO_n_SHIFT)) & SIUL2_GPDO142_PDO_n_MASK) 3049 /*! @} */ 3050 3051 /*! @name GPDO141 - SIUL2 GPIO Pad Data Output Register */ 3052 /*! @{ */ 3053 3054 #define SIUL2_GPDO141_PDO_n_MASK (0x1U) 3055 #define SIUL2_GPDO141_PDO_n_SHIFT (0U) 3056 #define SIUL2_GPDO141_PDO_n_WIDTH (1U) 3057 #define SIUL2_GPDO141_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO141_PDO_n_SHIFT)) & SIUL2_GPDO141_PDO_n_MASK) 3058 /*! @} */ 3059 3060 /*! @name GPDO140 - SIUL2 GPIO Pad Data Output Register */ 3061 /*! @{ */ 3062 3063 #define SIUL2_GPDO140_PDO_n_MASK (0x1U) 3064 #define SIUL2_GPDO140_PDO_n_SHIFT (0U) 3065 #define SIUL2_GPDO140_PDO_n_WIDTH (1U) 3066 #define SIUL2_GPDO140_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO140_PDO_n_SHIFT)) & SIUL2_GPDO140_PDO_n_MASK) 3067 /*! @} */ 3068 3069 /*! @name GPDO147 - SIUL2 GPIO Pad Data Output Register */ 3070 /*! @{ */ 3071 3072 #define SIUL2_GPDO147_PDO_n_MASK (0x1U) 3073 #define SIUL2_GPDO147_PDO_n_SHIFT (0U) 3074 #define SIUL2_GPDO147_PDO_n_WIDTH (1U) 3075 #define SIUL2_GPDO147_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO147_PDO_n_SHIFT)) & SIUL2_GPDO147_PDO_n_MASK) 3076 /*! @} */ 3077 3078 /*! @name GPDO146 - SIUL2 GPIO Pad Data Output Register */ 3079 /*! @{ */ 3080 3081 #define SIUL2_GPDO146_PDO_n_MASK (0x1U) 3082 #define SIUL2_GPDO146_PDO_n_SHIFT (0U) 3083 #define SIUL2_GPDO146_PDO_n_WIDTH (1U) 3084 #define SIUL2_GPDO146_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO146_PDO_n_SHIFT)) & SIUL2_GPDO146_PDO_n_MASK) 3085 /*! @} */ 3086 3087 /*! @name GPDO145 - SIUL2 GPIO Pad Data Output Register */ 3088 /*! @{ */ 3089 3090 #define SIUL2_GPDO145_PDO_n_MASK (0x1U) 3091 #define SIUL2_GPDO145_PDO_n_SHIFT (0U) 3092 #define SIUL2_GPDO145_PDO_n_WIDTH (1U) 3093 #define SIUL2_GPDO145_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO145_PDO_n_SHIFT)) & SIUL2_GPDO145_PDO_n_MASK) 3094 /*! @} */ 3095 3096 /*! @name GPDO144 - SIUL2 GPIO Pad Data Output Register */ 3097 /*! @{ */ 3098 3099 #define SIUL2_GPDO144_PDO_n_MASK (0x1U) 3100 #define SIUL2_GPDO144_PDO_n_SHIFT (0U) 3101 #define SIUL2_GPDO144_PDO_n_WIDTH (1U) 3102 #define SIUL2_GPDO144_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO144_PDO_n_SHIFT)) & SIUL2_GPDO144_PDO_n_MASK) 3103 /*! @} */ 3104 3105 /*! @name GPDO151 - SIUL2 GPIO Pad Data Output Register */ 3106 /*! @{ */ 3107 3108 #define SIUL2_GPDO151_PDO_n_MASK (0x1U) 3109 #define SIUL2_GPDO151_PDO_n_SHIFT (0U) 3110 #define SIUL2_GPDO151_PDO_n_WIDTH (1U) 3111 #define SIUL2_GPDO151_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO151_PDO_n_SHIFT)) & SIUL2_GPDO151_PDO_n_MASK) 3112 /*! @} */ 3113 3114 /*! @name GPDO150 - SIUL2 GPIO Pad Data Output Register */ 3115 /*! @{ */ 3116 3117 #define SIUL2_GPDO150_PDO_n_MASK (0x1U) 3118 #define SIUL2_GPDO150_PDO_n_SHIFT (0U) 3119 #define SIUL2_GPDO150_PDO_n_WIDTH (1U) 3120 #define SIUL2_GPDO150_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO150_PDO_n_SHIFT)) & SIUL2_GPDO150_PDO_n_MASK) 3121 /*! @} */ 3122 3123 /*! @name GPDO149 - SIUL2 GPIO Pad Data Output Register */ 3124 /*! @{ */ 3125 3126 #define SIUL2_GPDO149_PDO_n_MASK (0x1U) 3127 #define SIUL2_GPDO149_PDO_n_SHIFT (0U) 3128 #define SIUL2_GPDO149_PDO_n_WIDTH (1U) 3129 #define SIUL2_GPDO149_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO149_PDO_n_SHIFT)) & SIUL2_GPDO149_PDO_n_MASK) 3130 /*! @} */ 3131 3132 /*! @name GPDO148 - SIUL2 GPIO Pad Data Output Register */ 3133 /*! @{ */ 3134 3135 #define SIUL2_GPDO148_PDO_n_MASK (0x1U) 3136 #define SIUL2_GPDO148_PDO_n_SHIFT (0U) 3137 #define SIUL2_GPDO148_PDO_n_WIDTH (1U) 3138 #define SIUL2_GPDO148_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO148_PDO_n_SHIFT)) & SIUL2_GPDO148_PDO_n_MASK) 3139 /*! @} */ 3140 3141 /*! @name GPDO155 - SIUL2 GPIO Pad Data Output Register */ 3142 /*! @{ */ 3143 3144 #define SIUL2_GPDO155_PDO_n_MASK (0x1U) 3145 #define SIUL2_GPDO155_PDO_n_SHIFT (0U) 3146 #define SIUL2_GPDO155_PDO_n_WIDTH (1U) 3147 #define SIUL2_GPDO155_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO155_PDO_n_SHIFT)) & SIUL2_GPDO155_PDO_n_MASK) 3148 /*! @} */ 3149 3150 /*! @name GPDO154 - SIUL2 GPIO Pad Data Output Register */ 3151 /*! @{ */ 3152 3153 #define SIUL2_GPDO154_PDO_n_MASK (0x1U) 3154 #define SIUL2_GPDO154_PDO_n_SHIFT (0U) 3155 #define SIUL2_GPDO154_PDO_n_WIDTH (1U) 3156 #define SIUL2_GPDO154_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO154_PDO_n_SHIFT)) & SIUL2_GPDO154_PDO_n_MASK) 3157 /*! @} */ 3158 3159 /*! @name GPDO153 - SIUL2 GPIO Pad Data Output Register */ 3160 /*! @{ */ 3161 3162 #define SIUL2_GPDO153_PDO_n_MASK (0x1U) 3163 #define SIUL2_GPDO153_PDO_n_SHIFT (0U) 3164 #define SIUL2_GPDO153_PDO_n_WIDTH (1U) 3165 #define SIUL2_GPDO153_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO153_PDO_n_SHIFT)) & SIUL2_GPDO153_PDO_n_MASK) 3166 /*! @} */ 3167 3168 /*! @name GPDO152 - SIUL2 GPIO Pad Data Output Register */ 3169 /*! @{ */ 3170 3171 #define SIUL2_GPDO152_PDO_n_MASK (0x1U) 3172 #define SIUL2_GPDO152_PDO_n_SHIFT (0U) 3173 #define SIUL2_GPDO152_PDO_n_WIDTH (1U) 3174 #define SIUL2_GPDO152_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO152_PDO_n_SHIFT)) & SIUL2_GPDO152_PDO_n_MASK) 3175 /*! @} */ 3176 3177 /*! @name GPDO159 - SIUL2 GPIO Pad Data Output Register */ 3178 /*! @{ */ 3179 3180 #define SIUL2_GPDO159_PDO_n_MASK (0x1U) 3181 #define SIUL2_GPDO159_PDO_n_SHIFT (0U) 3182 #define SIUL2_GPDO159_PDO_n_WIDTH (1U) 3183 #define SIUL2_GPDO159_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO159_PDO_n_SHIFT)) & SIUL2_GPDO159_PDO_n_MASK) 3184 /*! @} */ 3185 3186 /*! @name GPDO158 - SIUL2 GPIO Pad Data Output Register */ 3187 /*! @{ */ 3188 3189 #define SIUL2_GPDO158_PDO_n_MASK (0x1U) 3190 #define SIUL2_GPDO158_PDO_n_SHIFT (0U) 3191 #define SIUL2_GPDO158_PDO_n_WIDTH (1U) 3192 #define SIUL2_GPDO158_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO158_PDO_n_SHIFT)) & SIUL2_GPDO158_PDO_n_MASK) 3193 /*! @} */ 3194 3195 /*! @name GPDO157 - SIUL2 GPIO Pad Data Output Register */ 3196 /*! @{ */ 3197 3198 #define SIUL2_GPDO157_PDO_n_MASK (0x1U) 3199 #define SIUL2_GPDO157_PDO_n_SHIFT (0U) 3200 #define SIUL2_GPDO157_PDO_n_WIDTH (1U) 3201 #define SIUL2_GPDO157_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO157_PDO_n_SHIFT)) & SIUL2_GPDO157_PDO_n_MASK) 3202 /*! @} */ 3203 3204 /*! @name GPDO156 - SIUL2 GPIO Pad Data Output Register */ 3205 /*! @{ */ 3206 3207 #define SIUL2_GPDO156_PDO_n_MASK (0x1U) 3208 #define SIUL2_GPDO156_PDO_n_SHIFT (0U) 3209 #define SIUL2_GPDO156_PDO_n_WIDTH (1U) 3210 #define SIUL2_GPDO156_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO156_PDO_n_SHIFT)) & SIUL2_GPDO156_PDO_n_MASK) 3211 /*! @} */ 3212 3213 /*! @name GPDO163 - SIUL2 GPIO Pad Data Output Register */ 3214 /*! @{ */ 3215 3216 #define SIUL2_GPDO163_PDO_n_MASK (0x1U) 3217 #define SIUL2_GPDO163_PDO_n_SHIFT (0U) 3218 #define SIUL2_GPDO163_PDO_n_WIDTH (1U) 3219 #define SIUL2_GPDO163_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO163_PDO_n_SHIFT)) & SIUL2_GPDO163_PDO_n_MASK) 3220 /*! @} */ 3221 3222 /*! @name GPDO162 - SIUL2 GPIO Pad Data Output Register */ 3223 /*! @{ */ 3224 3225 #define SIUL2_GPDO162_PDO_n_MASK (0x1U) 3226 #define SIUL2_GPDO162_PDO_n_SHIFT (0U) 3227 #define SIUL2_GPDO162_PDO_n_WIDTH (1U) 3228 #define SIUL2_GPDO162_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO162_PDO_n_SHIFT)) & SIUL2_GPDO162_PDO_n_MASK) 3229 /*! @} */ 3230 3231 /*! @name GPDO161 - SIUL2 GPIO Pad Data Output Register */ 3232 /*! @{ */ 3233 3234 #define SIUL2_GPDO161_PDO_n_MASK (0x1U) 3235 #define SIUL2_GPDO161_PDO_n_SHIFT (0U) 3236 #define SIUL2_GPDO161_PDO_n_WIDTH (1U) 3237 #define SIUL2_GPDO161_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO161_PDO_n_SHIFT)) & SIUL2_GPDO161_PDO_n_MASK) 3238 /*! @} */ 3239 3240 /*! @name GPDO160 - SIUL2 GPIO Pad Data Output Register */ 3241 /*! @{ */ 3242 3243 #define SIUL2_GPDO160_PDO_n_MASK (0x1U) 3244 #define SIUL2_GPDO160_PDO_n_SHIFT (0U) 3245 #define SIUL2_GPDO160_PDO_n_WIDTH (1U) 3246 #define SIUL2_GPDO160_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO160_PDO_n_SHIFT)) & SIUL2_GPDO160_PDO_n_MASK) 3247 /*! @} */ 3248 3249 /*! @name GPDO167 - SIUL2 GPIO Pad Data Output Register */ 3250 /*! @{ */ 3251 3252 #define SIUL2_GPDO167_PDO_n_MASK (0x1U) 3253 #define SIUL2_GPDO167_PDO_n_SHIFT (0U) 3254 #define SIUL2_GPDO167_PDO_n_WIDTH (1U) 3255 #define SIUL2_GPDO167_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO167_PDO_n_SHIFT)) & SIUL2_GPDO167_PDO_n_MASK) 3256 /*! @} */ 3257 3258 /*! @name GPDO166 - SIUL2 GPIO Pad Data Output Register */ 3259 /*! @{ */ 3260 3261 #define SIUL2_GPDO166_PDO_n_MASK (0x1U) 3262 #define SIUL2_GPDO166_PDO_n_SHIFT (0U) 3263 #define SIUL2_GPDO166_PDO_n_WIDTH (1U) 3264 #define SIUL2_GPDO166_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO166_PDO_n_SHIFT)) & SIUL2_GPDO166_PDO_n_MASK) 3265 /*! @} */ 3266 3267 /*! @name GPDO165 - SIUL2 GPIO Pad Data Output Register */ 3268 /*! @{ */ 3269 3270 #define SIUL2_GPDO165_PDO_n_MASK (0x1U) 3271 #define SIUL2_GPDO165_PDO_n_SHIFT (0U) 3272 #define SIUL2_GPDO165_PDO_n_WIDTH (1U) 3273 #define SIUL2_GPDO165_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO165_PDO_n_SHIFT)) & SIUL2_GPDO165_PDO_n_MASK) 3274 /*! @} */ 3275 3276 /*! @name GPDO164 - SIUL2 GPIO Pad Data Output Register */ 3277 /*! @{ */ 3278 3279 #define SIUL2_GPDO164_PDO_n_MASK (0x1U) 3280 #define SIUL2_GPDO164_PDO_n_SHIFT (0U) 3281 #define SIUL2_GPDO164_PDO_n_WIDTH (1U) 3282 #define SIUL2_GPDO164_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO164_PDO_n_SHIFT)) & SIUL2_GPDO164_PDO_n_MASK) 3283 /*! @} */ 3284 3285 /*! @name GPDO171 - SIUL2 GPIO Pad Data Output Register */ 3286 /*! @{ */ 3287 3288 #define SIUL2_GPDO171_PDO_n_MASK (0x1U) 3289 #define SIUL2_GPDO171_PDO_n_SHIFT (0U) 3290 #define SIUL2_GPDO171_PDO_n_WIDTH (1U) 3291 #define SIUL2_GPDO171_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO171_PDO_n_SHIFT)) & SIUL2_GPDO171_PDO_n_MASK) 3292 /*! @} */ 3293 3294 /*! @name GPDO170 - SIUL2 GPIO Pad Data Output Register */ 3295 /*! @{ */ 3296 3297 #define SIUL2_GPDO170_PDO_n_MASK (0x1U) 3298 #define SIUL2_GPDO170_PDO_n_SHIFT (0U) 3299 #define SIUL2_GPDO170_PDO_n_WIDTH (1U) 3300 #define SIUL2_GPDO170_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO170_PDO_n_SHIFT)) & SIUL2_GPDO170_PDO_n_MASK) 3301 /*! @} */ 3302 3303 /*! @name GPDO169 - SIUL2 GPIO Pad Data Output Register */ 3304 /*! @{ */ 3305 3306 #define SIUL2_GPDO169_PDO_n_MASK (0x1U) 3307 #define SIUL2_GPDO169_PDO_n_SHIFT (0U) 3308 #define SIUL2_GPDO169_PDO_n_WIDTH (1U) 3309 #define SIUL2_GPDO169_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO169_PDO_n_SHIFT)) & SIUL2_GPDO169_PDO_n_MASK) 3310 /*! @} */ 3311 3312 /*! @name GPDO168 - SIUL2 GPIO Pad Data Output Register */ 3313 /*! @{ */ 3314 3315 #define SIUL2_GPDO168_PDO_n_MASK (0x1U) 3316 #define SIUL2_GPDO168_PDO_n_SHIFT (0U) 3317 #define SIUL2_GPDO168_PDO_n_WIDTH (1U) 3318 #define SIUL2_GPDO168_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO168_PDO_n_SHIFT)) & SIUL2_GPDO168_PDO_n_MASK) 3319 /*! @} */ 3320 3321 /*! @name GPDO175 - SIUL2 GPIO Pad Data Output Register */ 3322 /*! @{ */ 3323 3324 #define SIUL2_GPDO175_PDO_n_MASK (0x1U) 3325 #define SIUL2_GPDO175_PDO_n_SHIFT (0U) 3326 #define SIUL2_GPDO175_PDO_n_WIDTH (1U) 3327 #define SIUL2_GPDO175_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO175_PDO_n_SHIFT)) & SIUL2_GPDO175_PDO_n_MASK) 3328 /*! @} */ 3329 3330 /*! @name GPDO174 - SIUL2 GPIO Pad Data Output Register */ 3331 /*! @{ */ 3332 3333 #define SIUL2_GPDO174_PDO_n_MASK (0x1U) 3334 #define SIUL2_GPDO174_PDO_n_SHIFT (0U) 3335 #define SIUL2_GPDO174_PDO_n_WIDTH (1U) 3336 #define SIUL2_GPDO174_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO174_PDO_n_SHIFT)) & SIUL2_GPDO174_PDO_n_MASK) 3337 /*! @} */ 3338 3339 /*! @name GPDO173 - SIUL2 GPIO Pad Data Output Register */ 3340 /*! @{ */ 3341 3342 #define SIUL2_GPDO173_PDO_n_MASK (0x1U) 3343 #define SIUL2_GPDO173_PDO_n_SHIFT (0U) 3344 #define SIUL2_GPDO173_PDO_n_WIDTH (1U) 3345 #define SIUL2_GPDO173_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO173_PDO_n_SHIFT)) & SIUL2_GPDO173_PDO_n_MASK) 3346 /*! @} */ 3347 3348 /*! @name GPDO172 - SIUL2 GPIO Pad Data Output Register */ 3349 /*! @{ */ 3350 3351 #define SIUL2_GPDO172_PDO_n_MASK (0x1U) 3352 #define SIUL2_GPDO172_PDO_n_SHIFT (0U) 3353 #define SIUL2_GPDO172_PDO_n_WIDTH (1U) 3354 #define SIUL2_GPDO172_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO172_PDO_n_SHIFT)) & SIUL2_GPDO172_PDO_n_MASK) 3355 /*! @} */ 3356 3357 /*! @name GPDO179 - SIUL2 GPIO Pad Data Output Register */ 3358 /*! @{ */ 3359 3360 #define SIUL2_GPDO179_PDO_n_MASK (0x1U) 3361 #define SIUL2_GPDO179_PDO_n_SHIFT (0U) 3362 #define SIUL2_GPDO179_PDO_n_WIDTH (1U) 3363 #define SIUL2_GPDO179_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO179_PDO_n_SHIFT)) & SIUL2_GPDO179_PDO_n_MASK) 3364 /*! @} */ 3365 3366 /*! @name GPDO178 - SIUL2 GPIO Pad Data Output Register */ 3367 /*! @{ */ 3368 3369 #define SIUL2_GPDO178_PDO_n_MASK (0x1U) 3370 #define SIUL2_GPDO178_PDO_n_SHIFT (0U) 3371 #define SIUL2_GPDO178_PDO_n_WIDTH (1U) 3372 #define SIUL2_GPDO178_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO178_PDO_n_SHIFT)) & SIUL2_GPDO178_PDO_n_MASK) 3373 /*! @} */ 3374 3375 /*! @name GPDO177 - SIUL2 GPIO Pad Data Output Register */ 3376 /*! @{ */ 3377 3378 #define SIUL2_GPDO177_PDO_n_MASK (0x1U) 3379 #define SIUL2_GPDO177_PDO_n_SHIFT (0U) 3380 #define SIUL2_GPDO177_PDO_n_WIDTH (1U) 3381 #define SIUL2_GPDO177_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO177_PDO_n_SHIFT)) & SIUL2_GPDO177_PDO_n_MASK) 3382 /*! @} */ 3383 3384 /*! @name GPDO176 - SIUL2 GPIO Pad Data Output Register */ 3385 /*! @{ */ 3386 3387 #define SIUL2_GPDO176_PDO_n_MASK (0x1U) 3388 #define SIUL2_GPDO176_PDO_n_SHIFT (0U) 3389 #define SIUL2_GPDO176_PDO_n_WIDTH (1U) 3390 #define SIUL2_GPDO176_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO176_PDO_n_SHIFT)) & SIUL2_GPDO176_PDO_n_MASK) 3391 /*! @} */ 3392 3393 /*! @name GPDO183 - SIUL2 GPIO Pad Data Output Register */ 3394 /*! @{ */ 3395 3396 #define SIUL2_GPDO183_PDO_n_MASK (0x1U) 3397 #define SIUL2_GPDO183_PDO_n_SHIFT (0U) 3398 #define SIUL2_GPDO183_PDO_n_WIDTH (1U) 3399 #define SIUL2_GPDO183_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO183_PDO_n_SHIFT)) & SIUL2_GPDO183_PDO_n_MASK) 3400 /*! @} */ 3401 3402 /*! @name GPDO182 - SIUL2 GPIO Pad Data Output Register */ 3403 /*! @{ */ 3404 3405 #define SIUL2_GPDO182_PDO_n_MASK (0x1U) 3406 #define SIUL2_GPDO182_PDO_n_SHIFT (0U) 3407 #define SIUL2_GPDO182_PDO_n_WIDTH (1U) 3408 #define SIUL2_GPDO182_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO182_PDO_n_SHIFT)) & SIUL2_GPDO182_PDO_n_MASK) 3409 /*! @} */ 3410 3411 /*! @name GPDO181 - SIUL2 GPIO Pad Data Output Register */ 3412 /*! @{ */ 3413 3414 #define SIUL2_GPDO181_PDO_n_MASK (0x1U) 3415 #define SIUL2_GPDO181_PDO_n_SHIFT (0U) 3416 #define SIUL2_GPDO181_PDO_n_WIDTH (1U) 3417 #define SIUL2_GPDO181_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO181_PDO_n_SHIFT)) & SIUL2_GPDO181_PDO_n_MASK) 3418 /*! @} */ 3419 3420 /*! @name GPDO180 - SIUL2 GPIO Pad Data Output Register */ 3421 /*! @{ */ 3422 3423 #define SIUL2_GPDO180_PDO_n_MASK (0x1U) 3424 #define SIUL2_GPDO180_PDO_n_SHIFT (0U) 3425 #define SIUL2_GPDO180_PDO_n_WIDTH (1U) 3426 #define SIUL2_GPDO180_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO180_PDO_n_SHIFT)) & SIUL2_GPDO180_PDO_n_MASK) 3427 /*! @} */ 3428 3429 /*! @name GPDO187 - SIUL2 GPIO Pad Data Output Register */ 3430 /*! @{ */ 3431 3432 #define SIUL2_GPDO187_PDO_n_MASK (0x1U) 3433 #define SIUL2_GPDO187_PDO_n_SHIFT (0U) 3434 #define SIUL2_GPDO187_PDO_n_WIDTH (1U) 3435 #define SIUL2_GPDO187_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO187_PDO_n_SHIFT)) & SIUL2_GPDO187_PDO_n_MASK) 3436 /*! @} */ 3437 3438 /*! @name GPDO186 - SIUL2 GPIO Pad Data Output Register */ 3439 /*! @{ */ 3440 3441 #define SIUL2_GPDO186_PDO_n_MASK (0x1U) 3442 #define SIUL2_GPDO186_PDO_n_SHIFT (0U) 3443 #define SIUL2_GPDO186_PDO_n_WIDTH (1U) 3444 #define SIUL2_GPDO186_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO186_PDO_n_SHIFT)) & SIUL2_GPDO186_PDO_n_MASK) 3445 /*! @} */ 3446 3447 /*! @name GPDO185 - SIUL2 GPIO Pad Data Output Register */ 3448 /*! @{ */ 3449 3450 #define SIUL2_GPDO185_PDO_n_MASK (0x1U) 3451 #define SIUL2_GPDO185_PDO_n_SHIFT (0U) 3452 #define SIUL2_GPDO185_PDO_n_WIDTH (1U) 3453 #define SIUL2_GPDO185_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO185_PDO_n_SHIFT)) & SIUL2_GPDO185_PDO_n_MASK) 3454 /*! @} */ 3455 3456 /*! @name GPDO184 - SIUL2 GPIO Pad Data Output Register */ 3457 /*! @{ */ 3458 3459 #define SIUL2_GPDO184_PDO_n_MASK (0x1U) 3460 #define SIUL2_GPDO184_PDO_n_SHIFT (0U) 3461 #define SIUL2_GPDO184_PDO_n_WIDTH (1U) 3462 #define SIUL2_GPDO184_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO184_PDO_n_SHIFT)) & SIUL2_GPDO184_PDO_n_MASK) 3463 /*! @} */ 3464 3465 /*! @name GPDO191 - SIUL2 GPIO Pad Data Output Register */ 3466 /*! @{ */ 3467 3468 #define SIUL2_GPDO191_PDO_n_MASK (0x1U) 3469 #define SIUL2_GPDO191_PDO_n_SHIFT (0U) 3470 #define SIUL2_GPDO191_PDO_n_WIDTH (1U) 3471 #define SIUL2_GPDO191_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO191_PDO_n_SHIFT)) & SIUL2_GPDO191_PDO_n_MASK) 3472 /*! @} */ 3473 3474 /*! @name GPDO190 - SIUL2 GPIO Pad Data Output Register */ 3475 /*! @{ */ 3476 3477 #define SIUL2_GPDO190_PDO_n_MASK (0x1U) 3478 #define SIUL2_GPDO190_PDO_n_SHIFT (0U) 3479 #define SIUL2_GPDO190_PDO_n_WIDTH (1U) 3480 #define SIUL2_GPDO190_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO190_PDO_n_SHIFT)) & SIUL2_GPDO190_PDO_n_MASK) 3481 /*! @} */ 3482 3483 /*! @name GPDO189 - SIUL2 GPIO Pad Data Output Register */ 3484 /*! @{ */ 3485 3486 #define SIUL2_GPDO189_PDO_n_MASK (0x1U) 3487 #define SIUL2_GPDO189_PDO_n_SHIFT (0U) 3488 #define SIUL2_GPDO189_PDO_n_WIDTH (1U) 3489 #define SIUL2_GPDO189_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO189_PDO_n_SHIFT)) & SIUL2_GPDO189_PDO_n_MASK) 3490 /*! @} */ 3491 3492 /*! @name GPDO188 - SIUL2 GPIO Pad Data Output Register */ 3493 /*! @{ */ 3494 3495 #define SIUL2_GPDO188_PDO_n_MASK (0x1U) 3496 #define SIUL2_GPDO188_PDO_n_SHIFT (0U) 3497 #define SIUL2_GPDO188_PDO_n_WIDTH (1U) 3498 #define SIUL2_GPDO188_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO188_PDO_n_SHIFT)) & SIUL2_GPDO188_PDO_n_MASK) 3499 /*! @} */ 3500 3501 /*! @name GPDO195 - SIUL2 GPIO Pad Data Output Register */ 3502 /*! @{ */ 3503 3504 #define SIUL2_GPDO195_PDO_n_MASK (0x1U) 3505 #define SIUL2_GPDO195_PDO_n_SHIFT (0U) 3506 #define SIUL2_GPDO195_PDO_n_WIDTH (1U) 3507 #define SIUL2_GPDO195_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO195_PDO_n_SHIFT)) & SIUL2_GPDO195_PDO_n_MASK) 3508 /*! @} */ 3509 3510 /*! @name GPDO194 - SIUL2 GPIO Pad Data Output Register */ 3511 /*! @{ */ 3512 3513 #define SIUL2_GPDO194_PDO_n_MASK (0x1U) 3514 #define SIUL2_GPDO194_PDO_n_SHIFT (0U) 3515 #define SIUL2_GPDO194_PDO_n_WIDTH (1U) 3516 #define SIUL2_GPDO194_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO194_PDO_n_SHIFT)) & SIUL2_GPDO194_PDO_n_MASK) 3517 /*! @} */ 3518 3519 /*! @name GPDO193 - SIUL2 GPIO Pad Data Output Register */ 3520 /*! @{ */ 3521 3522 #define SIUL2_GPDO193_PDO_n_MASK (0x1U) 3523 #define SIUL2_GPDO193_PDO_n_SHIFT (0U) 3524 #define SIUL2_GPDO193_PDO_n_WIDTH (1U) 3525 #define SIUL2_GPDO193_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO193_PDO_n_SHIFT)) & SIUL2_GPDO193_PDO_n_MASK) 3526 /*! @} */ 3527 3528 /*! @name GPDO192 - SIUL2 GPIO Pad Data Output Register */ 3529 /*! @{ */ 3530 3531 #define SIUL2_GPDO192_PDO_n_MASK (0x1U) 3532 #define SIUL2_GPDO192_PDO_n_SHIFT (0U) 3533 #define SIUL2_GPDO192_PDO_n_WIDTH (1U) 3534 #define SIUL2_GPDO192_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO192_PDO_n_SHIFT)) & SIUL2_GPDO192_PDO_n_MASK) 3535 /*! @} */ 3536 3537 /*! @name GPDO199 - SIUL2 GPIO Pad Data Output Register */ 3538 /*! @{ */ 3539 3540 #define SIUL2_GPDO199_PDO_n_MASK (0x1U) 3541 #define SIUL2_GPDO199_PDO_n_SHIFT (0U) 3542 #define SIUL2_GPDO199_PDO_n_WIDTH (1U) 3543 #define SIUL2_GPDO199_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO199_PDO_n_SHIFT)) & SIUL2_GPDO199_PDO_n_MASK) 3544 /*! @} */ 3545 3546 /*! @name GPDO198 - SIUL2 GPIO Pad Data Output Register */ 3547 /*! @{ */ 3548 3549 #define SIUL2_GPDO198_PDO_n_MASK (0x1U) 3550 #define SIUL2_GPDO198_PDO_n_SHIFT (0U) 3551 #define SIUL2_GPDO198_PDO_n_WIDTH (1U) 3552 #define SIUL2_GPDO198_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO198_PDO_n_SHIFT)) & SIUL2_GPDO198_PDO_n_MASK) 3553 /*! @} */ 3554 3555 /*! @name GPDO197 - SIUL2 GPIO Pad Data Output Register */ 3556 /*! @{ */ 3557 3558 #define SIUL2_GPDO197_PDO_n_MASK (0x1U) 3559 #define SIUL2_GPDO197_PDO_n_SHIFT (0U) 3560 #define SIUL2_GPDO197_PDO_n_WIDTH (1U) 3561 #define SIUL2_GPDO197_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO197_PDO_n_SHIFT)) & SIUL2_GPDO197_PDO_n_MASK) 3562 /*! @} */ 3563 3564 /*! @name GPDO196 - SIUL2 GPIO Pad Data Output Register */ 3565 /*! @{ */ 3566 3567 #define SIUL2_GPDO196_PDO_n_MASK (0x1U) 3568 #define SIUL2_GPDO196_PDO_n_SHIFT (0U) 3569 #define SIUL2_GPDO196_PDO_n_WIDTH (1U) 3570 #define SIUL2_GPDO196_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO196_PDO_n_SHIFT)) & SIUL2_GPDO196_PDO_n_MASK) 3571 /*! @} */ 3572 3573 /*! @name GPDO203 - SIUL2 GPIO Pad Data Output Register */ 3574 /*! @{ */ 3575 3576 #define SIUL2_GPDO203_PDO_n_MASK (0x1U) 3577 #define SIUL2_GPDO203_PDO_n_SHIFT (0U) 3578 #define SIUL2_GPDO203_PDO_n_WIDTH (1U) 3579 #define SIUL2_GPDO203_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO203_PDO_n_SHIFT)) & SIUL2_GPDO203_PDO_n_MASK) 3580 /*! @} */ 3581 3582 /*! @name GPDO202 - SIUL2 GPIO Pad Data Output Register */ 3583 /*! @{ */ 3584 3585 #define SIUL2_GPDO202_PDO_n_MASK (0x1U) 3586 #define SIUL2_GPDO202_PDO_n_SHIFT (0U) 3587 #define SIUL2_GPDO202_PDO_n_WIDTH (1U) 3588 #define SIUL2_GPDO202_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO202_PDO_n_SHIFT)) & SIUL2_GPDO202_PDO_n_MASK) 3589 /*! @} */ 3590 3591 /*! @name GPDO201 - SIUL2 GPIO Pad Data Output Register */ 3592 /*! @{ */ 3593 3594 #define SIUL2_GPDO201_PDO_n_MASK (0x1U) 3595 #define SIUL2_GPDO201_PDO_n_SHIFT (0U) 3596 #define SIUL2_GPDO201_PDO_n_WIDTH (1U) 3597 #define SIUL2_GPDO201_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO201_PDO_n_SHIFT)) & SIUL2_GPDO201_PDO_n_MASK) 3598 /*! @} */ 3599 3600 /*! @name GPDO200 - SIUL2 GPIO Pad Data Output Register */ 3601 /*! @{ */ 3602 3603 #define SIUL2_GPDO200_PDO_n_MASK (0x1U) 3604 #define SIUL2_GPDO200_PDO_n_SHIFT (0U) 3605 #define SIUL2_GPDO200_PDO_n_WIDTH (1U) 3606 #define SIUL2_GPDO200_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO200_PDO_n_SHIFT)) & SIUL2_GPDO200_PDO_n_MASK) 3607 /*! @} */ 3608 3609 /*! @name GPDO207 - SIUL2 GPIO Pad Data Output Register */ 3610 /*! @{ */ 3611 3612 #define SIUL2_GPDO207_PDO_n_MASK (0x1U) 3613 #define SIUL2_GPDO207_PDO_n_SHIFT (0U) 3614 #define SIUL2_GPDO207_PDO_n_WIDTH (1U) 3615 #define SIUL2_GPDO207_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO207_PDO_n_SHIFT)) & SIUL2_GPDO207_PDO_n_MASK) 3616 /*! @} */ 3617 3618 /*! @name GPDO206 - SIUL2 GPIO Pad Data Output Register */ 3619 /*! @{ */ 3620 3621 #define SIUL2_GPDO206_PDO_n_MASK (0x1U) 3622 #define SIUL2_GPDO206_PDO_n_SHIFT (0U) 3623 #define SIUL2_GPDO206_PDO_n_WIDTH (1U) 3624 #define SIUL2_GPDO206_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO206_PDO_n_SHIFT)) & SIUL2_GPDO206_PDO_n_MASK) 3625 /*! @} */ 3626 3627 /*! @name GPDO205 - SIUL2 GPIO Pad Data Output Register */ 3628 /*! @{ */ 3629 3630 #define SIUL2_GPDO205_PDO_n_MASK (0x1U) 3631 #define SIUL2_GPDO205_PDO_n_SHIFT (0U) 3632 #define SIUL2_GPDO205_PDO_n_WIDTH (1U) 3633 #define SIUL2_GPDO205_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO205_PDO_n_SHIFT)) & SIUL2_GPDO205_PDO_n_MASK) 3634 /*! @} */ 3635 3636 /*! @name GPDO204 - SIUL2 GPIO Pad Data Output Register */ 3637 /*! @{ */ 3638 3639 #define SIUL2_GPDO204_PDO_n_MASK (0x1U) 3640 #define SIUL2_GPDO204_PDO_n_SHIFT (0U) 3641 #define SIUL2_GPDO204_PDO_n_WIDTH (1U) 3642 #define SIUL2_GPDO204_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO204_PDO_n_SHIFT)) & SIUL2_GPDO204_PDO_n_MASK) 3643 /*! @} */ 3644 3645 /*! @name GPDO211 - SIUL2 GPIO Pad Data Output Register */ 3646 /*! @{ */ 3647 3648 #define SIUL2_GPDO211_PDO_n_MASK (0x1U) 3649 #define SIUL2_GPDO211_PDO_n_SHIFT (0U) 3650 #define SIUL2_GPDO211_PDO_n_WIDTH (1U) 3651 #define SIUL2_GPDO211_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO211_PDO_n_SHIFT)) & SIUL2_GPDO211_PDO_n_MASK) 3652 /*! @} */ 3653 3654 /*! @name GPDO210 - SIUL2 GPIO Pad Data Output Register */ 3655 /*! @{ */ 3656 3657 #define SIUL2_GPDO210_PDO_n_MASK (0x1U) 3658 #define SIUL2_GPDO210_PDO_n_SHIFT (0U) 3659 #define SIUL2_GPDO210_PDO_n_WIDTH (1U) 3660 #define SIUL2_GPDO210_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO210_PDO_n_SHIFT)) & SIUL2_GPDO210_PDO_n_MASK) 3661 /*! @} */ 3662 3663 /*! @name GPDO209 - SIUL2 GPIO Pad Data Output Register */ 3664 /*! @{ */ 3665 3666 #define SIUL2_GPDO209_PDO_n_MASK (0x1U) 3667 #define SIUL2_GPDO209_PDO_n_SHIFT (0U) 3668 #define SIUL2_GPDO209_PDO_n_WIDTH (1U) 3669 #define SIUL2_GPDO209_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO209_PDO_n_SHIFT)) & SIUL2_GPDO209_PDO_n_MASK) 3670 /*! @} */ 3671 3672 /*! @name GPDO208 - SIUL2 GPIO Pad Data Output Register */ 3673 /*! @{ */ 3674 3675 #define SIUL2_GPDO208_PDO_n_MASK (0x1U) 3676 #define SIUL2_GPDO208_PDO_n_SHIFT (0U) 3677 #define SIUL2_GPDO208_PDO_n_WIDTH (1U) 3678 #define SIUL2_GPDO208_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO208_PDO_n_SHIFT)) & SIUL2_GPDO208_PDO_n_MASK) 3679 /*! @} */ 3680 3681 /*! @name GPDO215 - SIUL2 GPIO Pad Data Output Register */ 3682 /*! @{ */ 3683 3684 #define SIUL2_GPDO215_PDO_n_MASK (0x1U) 3685 #define SIUL2_GPDO215_PDO_n_SHIFT (0U) 3686 #define SIUL2_GPDO215_PDO_n_WIDTH (1U) 3687 #define SIUL2_GPDO215_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO215_PDO_n_SHIFT)) & SIUL2_GPDO215_PDO_n_MASK) 3688 /*! @} */ 3689 3690 /*! @name GPDO214 - SIUL2 GPIO Pad Data Output Register */ 3691 /*! @{ */ 3692 3693 #define SIUL2_GPDO214_PDO_n_MASK (0x1U) 3694 #define SIUL2_GPDO214_PDO_n_SHIFT (0U) 3695 #define SIUL2_GPDO214_PDO_n_WIDTH (1U) 3696 #define SIUL2_GPDO214_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO214_PDO_n_SHIFT)) & SIUL2_GPDO214_PDO_n_MASK) 3697 /*! @} */ 3698 3699 /*! @name GPDO213 - SIUL2 GPIO Pad Data Output Register */ 3700 /*! @{ */ 3701 3702 #define SIUL2_GPDO213_PDO_n_MASK (0x1U) 3703 #define SIUL2_GPDO213_PDO_n_SHIFT (0U) 3704 #define SIUL2_GPDO213_PDO_n_WIDTH (1U) 3705 #define SIUL2_GPDO213_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO213_PDO_n_SHIFT)) & SIUL2_GPDO213_PDO_n_MASK) 3706 /*! @} */ 3707 3708 /*! @name GPDO212 - SIUL2 GPIO Pad Data Output Register */ 3709 /*! @{ */ 3710 3711 #define SIUL2_GPDO212_PDO_n_MASK (0x1U) 3712 #define SIUL2_GPDO212_PDO_n_SHIFT (0U) 3713 #define SIUL2_GPDO212_PDO_n_WIDTH (1U) 3714 #define SIUL2_GPDO212_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO212_PDO_n_SHIFT)) & SIUL2_GPDO212_PDO_n_MASK) 3715 /*! @} */ 3716 3717 /*! @name GPDO219 - SIUL2 GPIO Pad Data Output Register */ 3718 /*! @{ */ 3719 3720 #define SIUL2_GPDO219_PDO_n_MASK (0x1U) 3721 #define SIUL2_GPDO219_PDO_n_SHIFT (0U) 3722 #define SIUL2_GPDO219_PDO_n_WIDTH (1U) 3723 #define SIUL2_GPDO219_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO219_PDO_n_SHIFT)) & SIUL2_GPDO219_PDO_n_MASK) 3724 /*! @} */ 3725 3726 /*! @name GPDO218 - SIUL2 GPIO Pad Data Output Register */ 3727 /*! @{ */ 3728 3729 #define SIUL2_GPDO218_PDO_n_MASK (0x1U) 3730 #define SIUL2_GPDO218_PDO_n_SHIFT (0U) 3731 #define SIUL2_GPDO218_PDO_n_WIDTH (1U) 3732 #define SIUL2_GPDO218_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO218_PDO_n_SHIFT)) & SIUL2_GPDO218_PDO_n_MASK) 3733 /*! @} */ 3734 3735 /*! @name GPDO217 - SIUL2 GPIO Pad Data Output Register */ 3736 /*! @{ */ 3737 3738 #define SIUL2_GPDO217_PDO_n_MASK (0x1U) 3739 #define SIUL2_GPDO217_PDO_n_SHIFT (0U) 3740 #define SIUL2_GPDO217_PDO_n_WIDTH (1U) 3741 #define SIUL2_GPDO217_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO217_PDO_n_SHIFT)) & SIUL2_GPDO217_PDO_n_MASK) 3742 /*! @} */ 3743 3744 /*! @name GPDO216 - SIUL2 GPIO Pad Data Output Register */ 3745 /*! @{ */ 3746 3747 #define SIUL2_GPDO216_PDO_n_MASK (0x1U) 3748 #define SIUL2_GPDO216_PDO_n_SHIFT (0U) 3749 #define SIUL2_GPDO216_PDO_n_WIDTH (1U) 3750 #define SIUL2_GPDO216_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO216_PDO_n_SHIFT)) & SIUL2_GPDO216_PDO_n_MASK) 3751 /*! @} */ 3752 3753 /*! @name GPDI3 - SIUL2 GPIO Pad Data Input Register */ 3754 /*! @{ */ 3755 3756 #define SIUL2_GPDI3_PDI_n_MASK (0x1U) 3757 #define SIUL2_GPDI3_PDI_n_SHIFT (0U) 3758 #define SIUL2_GPDI3_PDI_n_WIDTH (1U) 3759 #define SIUL2_GPDI3_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI3_PDI_n_SHIFT)) & SIUL2_GPDI3_PDI_n_MASK) 3760 /*! @} */ 3761 3762 /*! @name GPDI2 - SIUL2 GPIO Pad Data Input Register */ 3763 /*! @{ */ 3764 3765 #define SIUL2_GPDI2_PDI_n_MASK (0x1U) 3766 #define SIUL2_GPDI2_PDI_n_SHIFT (0U) 3767 #define SIUL2_GPDI2_PDI_n_WIDTH (1U) 3768 #define SIUL2_GPDI2_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI2_PDI_n_SHIFT)) & SIUL2_GPDI2_PDI_n_MASK) 3769 /*! @} */ 3770 3771 /*! @name GPDI1 - SIUL2 GPIO Pad Data Input Register */ 3772 /*! @{ */ 3773 3774 #define SIUL2_GPDI1_PDI_n_MASK (0x1U) 3775 #define SIUL2_GPDI1_PDI_n_SHIFT (0U) 3776 #define SIUL2_GPDI1_PDI_n_WIDTH (1U) 3777 #define SIUL2_GPDI1_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI1_PDI_n_SHIFT)) & SIUL2_GPDI1_PDI_n_MASK) 3778 /*! @} */ 3779 3780 /*! @name GPDI0 - SIUL2 GPIO Pad Data Input Register */ 3781 /*! @{ */ 3782 3783 #define SIUL2_GPDI0_PDI_n_MASK (0x1U) 3784 #define SIUL2_GPDI0_PDI_n_SHIFT (0U) 3785 #define SIUL2_GPDI0_PDI_n_WIDTH (1U) 3786 #define SIUL2_GPDI0_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI0_PDI_n_SHIFT)) & SIUL2_GPDI0_PDI_n_MASK) 3787 /*! @} */ 3788 3789 /*! @name GPDI7 - SIUL2 GPIO Pad Data Input Register */ 3790 /*! @{ */ 3791 3792 #define SIUL2_GPDI7_PDI_n_MASK (0x1U) 3793 #define SIUL2_GPDI7_PDI_n_SHIFT (0U) 3794 #define SIUL2_GPDI7_PDI_n_WIDTH (1U) 3795 #define SIUL2_GPDI7_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI7_PDI_n_SHIFT)) & SIUL2_GPDI7_PDI_n_MASK) 3796 /*! @} */ 3797 3798 /*! @name GPDI6 - SIUL2 GPIO Pad Data Input Register */ 3799 /*! @{ */ 3800 3801 #define SIUL2_GPDI6_PDI_n_MASK (0x1U) 3802 #define SIUL2_GPDI6_PDI_n_SHIFT (0U) 3803 #define SIUL2_GPDI6_PDI_n_WIDTH (1U) 3804 #define SIUL2_GPDI6_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI6_PDI_n_SHIFT)) & SIUL2_GPDI6_PDI_n_MASK) 3805 /*! @} */ 3806 3807 /*! @name GPDI5 - SIUL2 GPIO Pad Data Input Register */ 3808 /*! @{ */ 3809 3810 #define SIUL2_GPDI5_PDI_n_MASK (0x1U) 3811 #define SIUL2_GPDI5_PDI_n_SHIFT (0U) 3812 #define SIUL2_GPDI5_PDI_n_WIDTH (1U) 3813 #define SIUL2_GPDI5_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI5_PDI_n_SHIFT)) & SIUL2_GPDI5_PDI_n_MASK) 3814 /*! @} */ 3815 3816 /*! @name GPDI4 - SIUL2 GPIO Pad Data Input Register */ 3817 /*! @{ */ 3818 3819 #define SIUL2_GPDI4_PDI_n_MASK (0x1U) 3820 #define SIUL2_GPDI4_PDI_n_SHIFT (0U) 3821 #define SIUL2_GPDI4_PDI_n_WIDTH (1U) 3822 #define SIUL2_GPDI4_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI4_PDI_n_SHIFT)) & SIUL2_GPDI4_PDI_n_MASK) 3823 /*! @} */ 3824 3825 /*! @name GPDI11 - SIUL2 GPIO Pad Data Input Register */ 3826 /*! @{ */ 3827 3828 #define SIUL2_GPDI11_PDI_n_MASK (0x1U) 3829 #define SIUL2_GPDI11_PDI_n_SHIFT (0U) 3830 #define SIUL2_GPDI11_PDI_n_WIDTH (1U) 3831 #define SIUL2_GPDI11_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI11_PDI_n_SHIFT)) & SIUL2_GPDI11_PDI_n_MASK) 3832 /*! @} */ 3833 3834 /*! @name GPDI10 - SIUL2 GPIO Pad Data Input Register */ 3835 /*! @{ */ 3836 3837 #define SIUL2_GPDI10_PDI_n_MASK (0x1U) 3838 #define SIUL2_GPDI10_PDI_n_SHIFT (0U) 3839 #define SIUL2_GPDI10_PDI_n_WIDTH (1U) 3840 #define SIUL2_GPDI10_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI10_PDI_n_SHIFT)) & SIUL2_GPDI10_PDI_n_MASK) 3841 /*! @} */ 3842 3843 /*! @name GPDI9 - SIUL2 GPIO Pad Data Input Register */ 3844 /*! @{ */ 3845 3846 #define SIUL2_GPDI9_PDI_n_MASK (0x1U) 3847 #define SIUL2_GPDI9_PDI_n_SHIFT (0U) 3848 #define SIUL2_GPDI9_PDI_n_WIDTH (1U) 3849 #define SIUL2_GPDI9_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI9_PDI_n_SHIFT)) & SIUL2_GPDI9_PDI_n_MASK) 3850 /*! @} */ 3851 3852 /*! @name GPDI8 - SIUL2 GPIO Pad Data Input Register */ 3853 /*! @{ */ 3854 3855 #define SIUL2_GPDI8_PDI_n_MASK (0x1U) 3856 #define SIUL2_GPDI8_PDI_n_SHIFT (0U) 3857 #define SIUL2_GPDI8_PDI_n_WIDTH (1U) 3858 #define SIUL2_GPDI8_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI8_PDI_n_SHIFT)) & SIUL2_GPDI8_PDI_n_MASK) 3859 /*! @} */ 3860 3861 /*! @name GPDI15 - SIUL2 GPIO Pad Data Input Register */ 3862 /*! @{ */ 3863 3864 #define SIUL2_GPDI15_PDI_n_MASK (0x1U) 3865 #define SIUL2_GPDI15_PDI_n_SHIFT (0U) 3866 #define SIUL2_GPDI15_PDI_n_WIDTH (1U) 3867 #define SIUL2_GPDI15_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI15_PDI_n_SHIFT)) & SIUL2_GPDI15_PDI_n_MASK) 3868 /*! @} */ 3869 3870 /*! @name GPDI14 - SIUL2 GPIO Pad Data Input Register */ 3871 /*! @{ */ 3872 3873 #define SIUL2_GPDI14_PDI_n_MASK (0x1U) 3874 #define SIUL2_GPDI14_PDI_n_SHIFT (0U) 3875 #define SIUL2_GPDI14_PDI_n_WIDTH (1U) 3876 #define SIUL2_GPDI14_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI14_PDI_n_SHIFT)) & SIUL2_GPDI14_PDI_n_MASK) 3877 /*! @} */ 3878 3879 /*! @name GPDI13 - SIUL2 GPIO Pad Data Input Register */ 3880 /*! @{ */ 3881 3882 #define SIUL2_GPDI13_PDI_n_MASK (0x1U) 3883 #define SIUL2_GPDI13_PDI_n_SHIFT (0U) 3884 #define SIUL2_GPDI13_PDI_n_WIDTH (1U) 3885 #define SIUL2_GPDI13_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI13_PDI_n_SHIFT)) & SIUL2_GPDI13_PDI_n_MASK) 3886 /*! @} */ 3887 3888 /*! @name GPDI12 - SIUL2 GPIO Pad Data Input Register */ 3889 /*! @{ */ 3890 3891 #define SIUL2_GPDI12_PDI_n_MASK (0x1U) 3892 #define SIUL2_GPDI12_PDI_n_SHIFT (0U) 3893 #define SIUL2_GPDI12_PDI_n_WIDTH (1U) 3894 #define SIUL2_GPDI12_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI12_PDI_n_SHIFT)) & SIUL2_GPDI12_PDI_n_MASK) 3895 /*! @} */ 3896 3897 /*! @name GPDI19 - SIUL2 GPIO Pad Data Input Register */ 3898 /*! @{ */ 3899 3900 #define SIUL2_GPDI19_PDI_n_MASK (0x1U) 3901 #define SIUL2_GPDI19_PDI_n_SHIFT (0U) 3902 #define SIUL2_GPDI19_PDI_n_WIDTH (1U) 3903 #define SIUL2_GPDI19_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI19_PDI_n_SHIFT)) & SIUL2_GPDI19_PDI_n_MASK) 3904 /*! @} */ 3905 3906 /*! @name GPDI18 - SIUL2 GPIO Pad Data Input Register */ 3907 /*! @{ */ 3908 3909 #define SIUL2_GPDI18_PDI_n_MASK (0x1U) 3910 #define SIUL2_GPDI18_PDI_n_SHIFT (0U) 3911 #define SIUL2_GPDI18_PDI_n_WIDTH (1U) 3912 #define SIUL2_GPDI18_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI18_PDI_n_SHIFT)) & SIUL2_GPDI18_PDI_n_MASK) 3913 /*! @} */ 3914 3915 /*! @name GPDI17 - SIUL2 GPIO Pad Data Input Register */ 3916 /*! @{ */ 3917 3918 #define SIUL2_GPDI17_PDI_n_MASK (0x1U) 3919 #define SIUL2_GPDI17_PDI_n_SHIFT (0U) 3920 #define SIUL2_GPDI17_PDI_n_WIDTH (1U) 3921 #define SIUL2_GPDI17_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI17_PDI_n_SHIFT)) & SIUL2_GPDI17_PDI_n_MASK) 3922 /*! @} */ 3923 3924 /*! @name GPDI16 - SIUL2 GPIO Pad Data Input Register */ 3925 /*! @{ */ 3926 3927 #define SIUL2_GPDI16_PDI_n_MASK (0x1U) 3928 #define SIUL2_GPDI16_PDI_n_SHIFT (0U) 3929 #define SIUL2_GPDI16_PDI_n_WIDTH (1U) 3930 #define SIUL2_GPDI16_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI16_PDI_n_SHIFT)) & SIUL2_GPDI16_PDI_n_MASK) 3931 /*! @} */ 3932 3933 /*! @name GPDI23 - SIUL2 GPIO Pad Data Input Register */ 3934 /*! @{ */ 3935 3936 #define SIUL2_GPDI23_PDI_n_MASK (0x1U) 3937 #define SIUL2_GPDI23_PDI_n_SHIFT (0U) 3938 #define SIUL2_GPDI23_PDI_n_WIDTH (1U) 3939 #define SIUL2_GPDI23_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI23_PDI_n_SHIFT)) & SIUL2_GPDI23_PDI_n_MASK) 3940 /*! @} */ 3941 3942 /*! @name GPDI22 - SIUL2 GPIO Pad Data Input Register */ 3943 /*! @{ */ 3944 3945 #define SIUL2_GPDI22_PDI_n_MASK (0x1U) 3946 #define SIUL2_GPDI22_PDI_n_SHIFT (0U) 3947 #define SIUL2_GPDI22_PDI_n_WIDTH (1U) 3948 #define SIUL2_GPDI22_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI22_PDI_n_SHIFT)) & SIUL2_GPDI22_PDI_n_MASK) 3949 /*! @} */ 3950 3951 /*! @name GPDI21 - SIUL2 GPIO Pad Data Input Register */ 3952 /*! @{ */ 3953 3954 #define SIUL2_GPDI21_PDI_n_MASK (0x1U) 3955 #define SIUL2_GPDI21_PDI_n_SHIFT (0U) 3956 #define SIUL2_GPDI21_PDI_n_WIDTH (1U) 3957 #define SIUL2_GPDI21_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI21_PDI_n_SHIFT)) & SIUL2_GPDI21_PDI_n_MASK) 3958 /*! @} */ 3959 3960 /*! @name GPDI20 - SIUL2 GPIO Pad Data Input Register */ 3961 /*! @{ */ 3962 3963 #define SIUL2_GPDI20_PDI_n_MASK (0x1U) 3964 #define SIUL2_GPDI20_PDI_n_SHIFT (0U) 3965 #define SIUL2_GPDI20_PDI_n_WIDTH (1U) 3966 #define SIUL2_GPDI20_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI20_PDI_n_SHIFT)) & SIUL2_GPDI20_PDI_n_MASK) 3967 /*! @} */ 3968 3969 /*! @name GPDI27 - SIUL2 GPIO Pad Data Input Register */ 3970 /*! @{ */ 3971 3972 #define SIUL2_GPDI27_PDI_n_MASK (0x1U) 3973 #define SIUL2_GPDI27_PDI_n_SHIFT (0U) 3974 #define SIUL2_GPDI27_PDI_n_WIDTH (1U) 3975 #define SIUL2_GPDI27_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI27_PDI_n_SHIFT)) & SIUL2_GPDI27_PDI_n_MASK) 3976 /*! @} */ 3977 3978 /*! @name GPDI26 - SIUL2 GPIO Pad Data Input Register */ 3979 /*! @{ */ 3980 3981 #define SIUL2_GPDI26_PDI_n_MASK (0x1U) 3982 #define SIUL2_GPDI26_PDI_n_SHIFT (0U) 3983 #define SIUL2_GPDI26_PDI_n_WIDTH (1U) 3984 #define SIUL2_GPDI26_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI26_PDI_n_SHIFT)) & SIUL2_GPDI26_PDI_n_MASK) 3985 /*! @} */ 3986 3987 /*! @name GPDI25 - SIUL2 GPIO Pad Data Input Register */ 3988 /*! @{ */ 3989 3990 #define SIUL2_GPDI25_PDI_n_MASK (0x1U) 3991 #define SIUL2_GPDI25_PDI_n_SHIFT (0U) 3992 #define SIUL2_GPDI25_PDI_n_WIDTH (1U) 3993 #define SIUL2_GPDI25_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI25_PDI_n_SHIFT)) & SIUL2_GPDI25_PDI_n_MASK) 3994 /*! @} */ 3995 3996 /*! @name GPDI24 - SIUL2 GPIO Pad Data Input Register */ 3997 /*! @{ */ 3998 3999 #define SIUL2_GPDI24_PDI_n_MASK (0x1U) 4000 #define SIUL2_GPDI24_PDI_n_SHIFT (0U) 4001 #define SIUL2_GPDI24_PDI_n_WIDTH (1U) 4002 #define SIUL2_GPDI24_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI24_PDI_n_SHIFT)) & SIUL2_GPDI24_PDI_n_MASK) 4003 /*! @} */ 4004 4005 /*! @name GPDI31 - SIUL2 GPIO Pad Data Input Register */ 4006 /*! @{ */ 4007 4008 #define SIUL2_GPDI31_PDI_n_MASK (0x1U) 4009 #define SIUL2_GPDI31_PDI_n_SHIFT (0U) 4010 #define SIUL2_GPDI31_PDI_n_WIDTH (1U) 4011 #define SIUL2_GPDI31_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI31_PDI_n_SHIFT)) & SIUL2_GPDI31_PDI_n_MASK) 4012 /*! @} */ 4013 4014 /*! @name GPDI30 - SIUL2 GPIO Pad Data Input Register */ 4015 /*! @{ */ 4016 4017 #define SIUL2_GPDI30_PDI_n_MASK (0x1U) 4018 #define SIUL2_GPDI30_PDI_n_SHIFT (0U) 4019 #define SIUL2_GPDI30_PDI_n_WIDTH (1U) 4020 #define SIUL2_GPDI30_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI30_PDI_n_SHIFT)) & SIUL2_GPDI30_PDI_n_MASK) 4021 /*! @} */ 4022 4023 /*! @name GPDI29 - SIUL2 GPIO Pad Data Input Register */ 4024 /*! @{ */ 4025 4026 #define SIUL2_GPDI29_PDI_n_MASK (0x1U) 4027 #define SIUL2_GPDI29_PDI_n_SHIFT (0U) 4028 #define SIUL2_GPDI29_PDI_n_WIDTH (1U) 4029 #define SIUL2_GPDI29_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI29_PDI_n_SHIFT)) & SIUL2_GPDI29_PDI_n_MASK) 4030 /*! @} */ 4031 4032 /*! @name GPDI28 - SIUL2 GPIO Pad Data Input Register */ 4033 /*! @{ */ 4034 4035 #define SIUL2_GPDI28_PDI_n_MASK (0x1U) 4036 #define SIUL2_GPDI28_PDI_n_SHIFT (0U) 4037 #define SIUL2_GPDI28_PDI_n_WIDTH (1U) 4038 #define SIUL2_GPDI28_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI28_PDI_n_SHIFT)) & SIUL2_GPDI28_PDI_n_MASK) 4039 /*! @} */ 4040 4041 /*! @name GPDI35 - SIUL2 GPIO Pad Data Input Register */ 4042 /*! @{ */ 4043 4044 #define SIUL2_GPDI35_PDI_n_MASK (0x1U) 4045 #define SIUL2_GPDI35_PDI_n_SHIFT (0U) 4046 #define SIUL2_GPDI35_PDI_n_WIDTH (1U) 4047 #define SIUL2_GPDI35_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI35_PDI_n_SHIFT)) & SIUL2_GPDI35_PDI_n_MASK) 4048 /*! @} */ 4049 4050 /*! @name GPDI34 - SIUL2 GPIO Pad Data Input Register */ 4051 /*! @{ */ 4052 4053 #define SIUL2_GPDI34_PDI_n_MASK (0x1U) 4054 #define SIUL2_GPDI34_PDI_n_SHIFT (0U) 4055 #define SIUL2_GPDI34_PDI_n_WIDTH (1U) 4056 #define SIUL2_GPDI34_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI34_PDI_n_SHIFT)) & SIUL2_GPDI34_PDI_n_MASK) 4057 /*! @} */ 4058 4059 /*! @name GPDI33 - SIUL2 GPIO Pad Data Input Register */ 4060 /*! @{ */ 4061 4062 #define SIUL2_GPDI33_PDI_n_MASK (0x1U) 4063 #define SIUL2_GPDI33_PDI_n_SHIFT (0U) 4064 #define SIUL2_GPDI33_PDI_n_WIDTH (1U) 4065 #define SIUL2_GPDI33_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI33_PDI_n_SHIFT)) & SIUL2_GPDI33_PDI_n_MASK) 4066 /*! @} */ 4067 4068 /*! @name GPDI32 - SIUL2 GPIO Pad Data Input Register */ 4069 /*! @{ */ 4070 4071 #define SIUL2_GPDI32_PDI_n_MASK (0x1U) 4072 #define SIUL2_GPDI32_PDI_n_SHIFT (0U) 4073 #define SIUL2_GPDI32_PDI_n_WIDTH (1U) 4074 #define SIUL2_GPDI32_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI32_PDI_n_SHIFT)) & SIUL2_GPDI32_PDI_n_MASK) 4075 /*! @} */ 4076 4077 /*! @name GPDI37 - SIUL2 GPIO Pad Data Input Register */ 4078 /*! @{ */ 4079 4080 #define SIUL2_GPDI37_PDI_n_MASK (0x1U) 4081 #define SIUL2_GPDI37_PDI_n_SHIFT (0U) 4082 #define SIUL2_GPDI37_PDI_n_WIDTH (1U) 4083 #define SIUL2_GPDI37_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI37_PDI_n_SHIFT)) & SIUL2_GPDI37_PDI_n_MASK) 4084 /*! @} */ 4085 4086 /*! @name GPDI36 - SIUL2 GPIO Pad Data Input Register */ 4087 /*! @{ */ 4088 4089 #define SIUL2_GPDI36_PDI_n_MASK (0x1U) 4090 #define SIUL2_GPDI36_PDI_n_SHIFT (0U) 4091 #define SIUL2_GPDI36_PDI_n_WIDTH (1U) 4092 #define SIUL2_GPDI36_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI36_PDI_n_SHIFT)) & SIUL2_GPDI36_PDI_n_MASK) 4093 /*! @} */ 4094 4095 /*! @name GPDI43 - SIUL2 GPIO Pad Data Input Register */ 4096 /*! @{ */ 4097 4098 #define SIUL2_GPDI43_PDI_n_MASK (0x1U) 4099 #define SIUL2_GPDI43_PDI_n_SHIFT (0U) 4100 #define SIUL2_GPDI43_PDI_n_WIDTH (1U) 4101 #define SIUL2_GPDI43_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI43_PDI_n_SHIFT)) & SIUL2_GPDI43_PDI_n_MASK) 4102 /*! @} */ 4103 4104 /*! @name GPDI42 - SIUL2 GPIO Pad Data Input Register */ 4105 /*! @{ */ 4106 4107 #define SIUL2_GPDI42_PDI_n_MASK (0x1U) 4108 #define SIUL2_GPDI42_PDI_n_SHIFT (0U) 4109 #define SIUL2_GPDI42_PDI_n_WIDTH (1U) 4110 #define SIUL2_GPDI42_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI42_PDI_n_SHIFT)) & SIUL2_GPDI42_PDI_n_MASK) 4111 /*! @} */ 4112 4113 /*! @name GPDI41 - SIUL2 GPIO Pad Data Input Register */ 4114 /*! @{ */ 4115 4116 #define SIUL2_GPDI41_PDI_n_MASK (0x1U) 4117 #define SIUL2_GPDI41_PDI_n_SHIFT (0U) 4118 #define SIUL2_GPDI41_PDI_n_WIDTH (1U) 4119 #define SIUL2_GPDI41_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI41_PDI_n_SHIFT)) & SIUL2_GPDI41_PDI_n_MASK) 4120 /*! @} */ 4121 4122 /*! @name GPDI40 - SIUL2 GPIO Pad Data Input Register */ 4123 /*! @{ */ 4124 4125 #define SIUL2_GPDI40_PDI_n_MASK (0x1U) 4126 #define SIUL2_GPDI40_PDI_n_SHIFT (0U) 4127 #define SIUL2_GPDI40_PDI_n_WIDTH (1U) 4128 #define SIUL2_GPDI40_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI40_PDI_n_SHIFT)) & SIUL2_GPDI40_PDI_n_MASK) 4129 /*! @} */ 4130 4131 /*! @name GPDI47 - SIUL2 GPIO Pad Data Input Register */ 4132 /*! @{ */ 4133 4134 #define SIUL2_GPDI47_PDI_n_MASK (0x1U) 4135 #define SIUL2_GPDI47_PDI_n_SHIFT (0U) 4136 #define SIUL2_GPDI47_PDI_n_WIDTH (1U) 4137 #define SIUL2_GPDI47_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI47_PDI_n_SHIFT)) & SIUL2_GPDI47_PDI_n_MASK) 4138 /*! @} */ 4139 4140 /*! @name GPDI46 - SIUL2 GPIO Pad Data Input Register */ 4141 /*! @{ */ 4142 4143 #define SIUL2_GPDI46_PDI_n_MASK (0x1U) 4144 #define SIUL2_GPDI46_PDI_n_SHIFT (0U) 4145 #define SIUL2_GPDI46_PDI_n_WIDTH (1U) 4146 #define SIUL2_GPDI46_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI46_PDI_n_SHIFT)) & SIUL2_GPDI46_PDI_n_MASK) 4147 /*! @} */ 4148 4149 /*! @name GPDI45 - SIUL2 GPIO Pad Data Input Register */ 4150 /*! @{ */ 4151 4152 #define SIUL2_GPDI45_PDI_n_MASK (0x1U) 4153 #define SIUL2_GPDI45_PDI_n_SHIFT (0U) 4154 #define SIUL2_GPDI45_PDI_n_WIDTH (1U) 4155 #define SIUL2_GPDI45_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI45_PDI_n_SHIFT)) & SIUL2_GPDI45_PDI_n_MASK) 4156 /*! @} */ 4157 4158 /*! @name GPDI44 - SIUL2 GPIO Pad Data Input Register */ 4159 /*! @{ */ 4160 4161 #define SIUL2_GPDI44_PDI_n_MASK (0x1U) 4162 #define SIUL2_GPDI44_PDI_n_SHIFT (0U) 4163 #define SIUL2_GPDI44_PDI_n_WIDTH (1U) 4164 #define SIUL2_GPDI44_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI44_PDI_n_SHIFT)) & SIUL2_GPDI44_PDI_n_MASK) 4165 /*! @} */ 4166 4167 /*! @name GPDI51 - SIUL2 GPIO Pad Data Input Register */ 4168 /*! @{ */ 4169 4170 #define SIUL2_GPDI51_PDI_n_MASK (0x1U) 4171 #define SIUL2_GPDI51_PDI_n_SHIFT (0U) 4172 #define SIUL2_GPDI51_PDI_n_WIDTH (1U) 4173 #define SIUL2_GPDI51_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI51_PDI_n_SHIFT)) & SIUL2_GPDI51_PDI_n_MASK) 4174 /*! @} */ 4175 4176 /*! @name GPDI50 - SIUL2 GPIO Pad Data Input Register */ 4177 /*! @{ */ 4178 4179 #define SIUL2_GPDI50_PDI_n_MASK (0x1U) 4180 #define SIUL2_GPDI50_PDI_n_SHIFT (0U) 4181 #define SIUL2_GPDI50_PDI_n_WIDTH (1U) 4182 #define SIUL2_GPDI50_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI50_PDI_n_SHIFT)) & SIUL2_GPDI50_PDI_n_MASK) 4183 /*! @} */ 4184 4185 /*! @name GPDI49 - SIUL2 GPIO Pad Data Input Register */ 4186 /*! @{ */ 4187 4188 #define SIUL2_GPDI49_PDI_n_MASK (0x1U) 4189 #define SIUL2_GPDI49_PDI_n_SHIFT (0U) 4190 #define SIUL2_GPDI49_PDI_n_WIDTH (1U) 4191 #define SIUL2_GPDI49_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI49_PDI_n_SHIFT)) & SIUL2_GPDI49_PDI_n_MASK) 4192 /*! @} */ 4193 4194 /*! @name GPDI48 - SIUL2 GPIO Pad Data Input Register */ 4195 /*! @{ */ 4196 4197 #define SIUL2_GPDI48_PDI_n_MASK (0x1U) 4198 #define SIUL2_GPDI48_PDI_n_SHIFT (0U) 4199 #define SIUL2_GPDI48_PDI_n_WIDTH (1U) 4200 #define SIUL2_GPDI48_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI48_PDI_n_SHIFT)) & SIUL2_GPDI48_PDI_n_MASK) 4201 /*! @} */ 4202 4203 /*! @name GPDI55 - SIUL2 GPIO Pad Data Input Register */ 4204 /*! @{ */ 4205 4206 #define SIUL2_GPDI55_PDI_n_MASK (0x1U) 4207 #define SIUL2_GPDI55_PDI_n_SHIFT (0U) 4208 #define SIUL2_GPDI55_PDI_n_WIDTH (1U) 4209 #define SIUL2_GPDI55_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI55_PDI_n_SHIFT)) & SIUL2_GPDI55_PDI_n_MASK) 4210 /*! @} */ 4211 4212 /*! @name GPDI54 - SIUL2 GPIO Pad Data Input Register */ 4213 /*! @{ */ 4214 4215 #define SIUL2_GPDI54_PDI_n_MASK (0x1U) 4216 #define SIUL2_GPDI54_PDI_n_SHIFT (0U) 4217 #define SIUL2_GPDI54_PDI_n_WIDTH (1U) 4218 #define SIUL2_GPDI54_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI54_PDI_n_SHIFT)) & SIUL2_GPDI54_PDI_n_MASK) 4219 /*! @} */ 4220 4221 /*! @name GPDI53 - SIUL2 GPIO Pad Data Input Register */ 4222 /*! @{ */ 4223 4224 #define SIUL2_GPDI53_PDI_n_MASK (0x1U) 4225 #define SIUL2_GPDI53_PDI_n_SHIFT (0U) 4226 #define SIUL2_GPDI53_PDI_n_WIDTH (1U) 4227 #define SIUL2_GPDI53_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI53_PDI_n_SHIFT)) & SIUL2_GPDI53_PDI_n_MASK) 4228 /*! @} */ 4229 4230 /*! @name GPDI52 - SIUL2 GPIO Pad Data Input Register */ 4231 /*! @{ */ 4232 4233 #define SIUL2_GPDI52_PDI_n_MASK (0x1U) 4234 #define SIUL2_GPDI52_PDI_n_SHIFT (0U) 4235 #define SIUL2_GPDI52_PDI_n_WIDTH (1U) 4236 #define SIUL2_GPDI52_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI52_PDI_n_SHIFT)) & SIUL2_GPDI52_PDI_n_MASK) 4237 /*! @} */ 4238 4239 /*! @name GPDI59 - SIUL2 GPIO Pad Data Input Register */ 4240 /*! @{ */ 4241 4242 #define SIUL2_GPDI59_PDI_n_MASK (0x1U) 4243 #define SIUL2_GPDI59_PDI_n_SHIFT (0U) 4244 #define SIUL2_GPDI59_PDI_n_WIDTH (1U) 4245 #define SIUL2_GPDI59_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI59_PDI_n_SHIFT)) & SIUL2_GPDI59_PDI_n_MASK) 4246 /*! @} */ 4247 4248 /*! @name GPDI58 - SIUL2 GPIO Pad Data Input Register */ 4249 /*! @{ */ 4250 4251 #define SIUL2_GPDI58_PDI_n_MASK (0x1U) 4252 #define SIUL2_GPDI58_PDI_n_SHIFT (0U) 4253 #define SIUL2_GPDI58_PDI_n_WIDTH (1U) 4254 #define SIUL2_GPDI58_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI58_PDI_n_SHIFT)) & SIUL2_GPDI58_PDI_n_MASK) 4255 /*! @} */ 4256 4257 /*! @name GPDI57 - SIUL2 GPIO Pad Data Input Register */ 4258 /*! @{ */ 4259 4260 #define SIUL2_GPDI57_PDI_n_MASK (0x1U) 4261 #define SIUL2_GPDI57_PDI_n_SHIFT (0U) 4262 #define SIUL2_GPDI57_PDI_n_WIDTH (1U) 4263 #define SIUL2_GPDI57_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI57_PDI_n_SHIFT)) & SIUL2_GPDI57_PDI_n_MASK) 4264 /*! @} */ 4265 4266 /*! @name GPDI56 - SIUL2 GPIO Pad Data Input Register */ 4267 /*! @{ */ 4268 4269 #define SIUL2_GPDI56_PDI_n_MASK (0x1U) 4270 #define SIUL2_GPDI56_PDI_n_SHIFT (0U) 4271 #define SIUL2_GPDI56_PDI_n_WIDTH (1U) 4272 #define SIUL2_GPDI56_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI56_PDI_n_SHIFT)) & SIUL2_GPDI56_PDI_n_MASK) 4273 /*! @} */ 4274 4275 /*! @name GPDI63 - SIUL2 GPIO Pad Data Input Register */ 4276 /*! @{ */ 4277 4278 #define SIUL2_GPDI63_PDI_n_MASK (0x1U) 4279 #define SIUL2_GPDI63_PDI_n_SHIFT (0U) 4280 #define SIUL2_GPDI63_PDI_n_WIDTH (1U) 4281 #define SIUL2_GPDI63_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI63_PDI_n_SHIFT)) & SIUL2_GPDI63_PDI_n_MASK) 4282 /*! @} */ 4283 4284 /*! @name GPDI62 - SIUL2 GPIO Pad Data Input Register */ 4285 /*! @{ */ 4286 4287 #define SIUL2_GPDI62_PDI_n_MASK (0x1U) 4288 #define SIUL2_GPDI62_PDI_n_SHIFT (0U) 4289 #define SIUL2_GPDI62_PDI_n_WIDTH (1U) 4290 #define SIUL2_GPDI62_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI62_PDI_n_SHIFT)) & SIUL2_GPDI62_PDI_n_MASK) 4291 /*! @} */ 4292 4293 /*! @name GPDI61 - SIUL2 GPIO Pad Data Input Register */ 4294 /*! @{ */ 4295 4296 #define SIUL2_GPDI61_PDI_n_MASK (0x1U) 4297 #define SIUL2_GPDI61_PDI_n_SHIFT (0U) 4298 #define SIUL2_GPDI61_PDI_n_WIDTH (1U) 4299 #define SIUL2_GPDI61_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI61_PDI_n_SHIFT)) & SIUL2_GPDI61_PDI_n_MASK) 4300 /*! @} */ 4301 4302 /*! @name GPDI60 - SIUL2 GPIO Pad Data Input Register */ 4303 /*! @{ */ 4304 4305 #define SIUL2_GPDI60_PDI_n_MASK (0x1U) 4306 #define SIUL2_GPDI60_PDI_n_SHIFT (0U) 4307 #define SIUL2_GPDI60_PDI_n_WIDTH (1U) 4308 #define SIUL2_GPDI60_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI60_PDI_n_SHIFT)) & SIUL2_GPDI60_PDI_n_MASK) 4309 /*! @} */ 4310 4311 /*! @name GPDI67 - SIUL2 GPIO Pad Data Input Register */ 4312 /*! @{ */ 4313 4314 #define SIUL2_GPDI67_PDI_n_MASK (0x1U) 4315 #define SIUL2_GPDI67_PDI_n_SHIFT (0U) 4316 #define SIUL2_GPDI67_PDI_n_WIDTH (1U) 4317 #define SIUL2_GPDI67_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI67_PDI_n_SHIFT)) & SIUL2_GPDI67_PDI_n_MASK) 4318 /*! @} */ 4319 4320 /*! @name GPDI66 - SIUL2 GPIO Pad Data Input Register */ 4321 /*! @{ */ 4322 4323 #define SIUL2_GPDI66_PDI_n_MASK (0x1U) 4324 #define SIUL2_GPDI66_PDI_n_SHIFT (0U) 4325 #define SIUL2_GPDI66_PDI_n_WIDTH (1U) 4326 #define SIUL2_GPDI66_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI66_PDI_n_SHIFT)) & SIUL2_GPDI66_PDI_n_MASK) 4327 /*! @} */ 4328 4329 /*! @name GPDI65 - SIUL2 GPIO Pad Data Input Register */ 4330 /*! @{ */ 4331 4332 #define SIUL2_GPDI65_PDI_n_MASK (0x1U) 4333 #define SIUL2_GPDI65_PDI_n_SHIFT (0U) 4334 #define SIUL2_GPDI65_PDI_n_WIDTH (1U) 4335 #define SIUL2_GPDI65_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI65_PDI_n_SHIFT)) & SIUL2_GPDI65_PDI_n_MASK) 4336 /*! @} */ 4337 4338 /*! @name GPDI64 - SIUL2 GPIO Pad Data Input Register */ 4339 /*! @{ */ 4340 4341 #define SIUL2_GPDI64_PDI_n_MASK (0x1U) 4342 #define SIUL2_GPDI64_PDI_n_SHIFT (0U) 4343 #define SIUL2_GPDI64_PDI_n_WIDTH (1U) 4344 #define SIUL2_GPDI64_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI64_PDI_n_SHIFT)) & SIUL2_GPDI64_PDI_n_MASK) 4345 /*! @} */ 4346 4347 /*! @name GPDI71 - SIUL2 GPIO Pad Data Input Register */ 4348 /*! @{ */ 4349 4350 #define SIUL2_GPDI71_PDI_n_MASK (0x1U) 4351 #define SIUL2_GPDI71_PDI_n_SHIFT (0U) 4352 #define SIUL2_GPDI71_PDI_n_WIDTH (1U) 4353 #define SIUL2_GPDI71_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI71_PDI_n_SHIFT)) & SIUL2_GPDI71_PDI_n_MASK) 4354 /*! @} */ 4355 4356 /*! @name GPDI70 - SIUL2 GPIO Pad Data Input Register */ 4357 /*! @{ */ 4358 4359 #define SIUL2_GPDI70_PDI_n_MASK (0x1U) 4360 #define SIUL2_GPDI70_PDI_n_SHIFT (0U) 4361 #define SIUL2_GPDI70_PDI_n_WIDTH (1U) 4362 #define SIUL2_GPDI70_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI70_PDI_n_SHIFT)) & SIUL2_GPDI70_PDI_n_MASK) 4363 /*! @} */ 4364 4365 /*! @name GPDI69 - SIUL2 GPIO Pad Data Input Register */ 4366 /*! @{ */ 4367 4368 #define SIUL2_GPDI69_PDI_n_MASK (0x1U) 4369 #define SIUL2_GPDI69_PDI_n_SHIFT (0U) 4370 #define SIUL2_GPDI69_PDI_n_WIDTH (1U) 4371 #define SIUL2_GPDI69_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI69_PDI_n_SHIFT)) & SIUL2_GPDI69_PDI_n_MASK) 4372 /*! @} */ 4373 4374 /*! @name GPDI68 - SIUL2 GPIO Pad Data Input Register */ 4375 /*! @{ */ 4376 4377 #define SIUL2_GPDI68_PDI_n_MASK (0x1U) 4378 #define SIUL2_GPDI68_PDI_n_SHIFT (0U) 4379 #define SIUL2_GPDI68_PDI_n_WIDTH (1U) 4380 #define SIUL2_GPDI68_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI68_PDI_n_SHIFT)) & SIUL2_GPDI68_PDI_n_MASK) 4381 /*! @} */ 4382 4383 /*! @name GPDI75 - SIUL2 GPIO Pad Data Input Register */ 4384 /*! @{ */ 4385 4386 #define SIUL2_GPDI75_PDI_n_MASK (0x1U) 4387 #define SIUL2_GPDI75_PDI_n_SHIFT (0U) 4388 #define SIUL2_GPDI75_PDI_n_WIDTH (1U) 4389 #define SIUL2_GPDI75_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI75_PDI_n_SHIFT)) & SIUL2_GPDI75_PDI_n_MASK) 4390 /*! @} */ 4391 4392 /*! @name GPDI74 - SIUL2 GPIO Pad Data Input Register */ 4393 /*! @{ */ 4394 4395 #define SIUL2_GPDI74_PDI_n_MASK (0x1U) 4396 #define SIUL2_GPDI74_PDI_n_SHIFT (0U) 4397 #define SIUL2_GPDI74_PDI_n_WIDTH (1U) 4398 #define SIUL2_GPDI74_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI74_PDI_n_SHIFT)) & SIUL2_GPDI74_PDI_n_MASK) 4399 /*! @} */ 4400 4401 /*! @name GPDI73 - SIUL2 GPIO Pad Data Input Register */ 4402 /*! @{ */ 4403 4404 #define SIUL2_GPDI73_PDI_n_MASK (0x1U) 4405 #define SIUL2_GPDI73_PDI_n_SHIFT (0U) 4406 #define SIUL2_GPDI73_PDI_n_WIDTH (1U) 4407 #define SIUL2_GPDI73_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI73_PDI_n_SHIFT)) & SIUL2_GPDI73_PDI_n_MASK) 4408 /*! @} */ 4409 4410 /*! @name GPDI72 - SIUL2 GPIO Pad Data Input Register */ 4411 /*! @{ */ 4412 4413 #define SIUL2_GPDI72_PDI_n_MASK (0x1U) 4414 #define SIUL2_GPDI72_PDI_n_SHIFT (0U) 4415 #define SIUL2_GPDI72_PDI_n_WIDTH (1U) 4416 #define SIUL2_GPDI72_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI72_PDI_n_SHIFT)) & SIUL2_GPDI72_PDI_n_MASK) 4417 /*! @} */ 4418 4419 /*! @name GPDI79 - SIUL2 GPIO Pad Data Input Register */ 4420 /*! @{ */ 4421 4422 #define SIUL2_GPDI79_PDI_n_MASK (0x1U) 4423 #define SIUL2_GPDI79_PDI_n_SHIFT (0U) 4424 #define SIUL2_GPDI79_PDI_n_WIDTH (1U) 4425 #define SIUL2_GPDI79_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI79_PDI_n_SHIFT)) & SIUL2_GPDI79_PDI_n_MASK) 4426 /*! @} */ 4427 4428 /*! @name GPDI78 - SIUL2 GPIO Pad Data Input Register */ 4429 /*! @{ */ 4430 4431 #define SIUL2_GPDI78_PDI_n_MASK (0x1U) 4432 #define SIUL2_GPDI78_PDI_n_SHIFT (0U) 4433 #define SIUL2_GPDI78_PDI_n_WIDTH (1U) 4434 #define SIUL2_GPDI78_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI78_PDI_n_SHIFT)) & SIUL2_GPDI78_PDI_n_MASK) 4435 /*! @} */ 4436 4437 /*! @name GPDI77 - SIUL2 GPIO Pad Data Input Register */ 4438 /*! @{ */ 4439 4440 #define SIUL2_GPDI77_PDI_n_MASK (0x1U) 4441 #define SIUL2_GPDI77_PDI_n_SHIFT (0U) 4442 #define SIUL2_GPDI77_PDI_n_WIDTH (1U) 4443 #define SIUL2_GPDI77_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI77_PDI_n_SHIFT)) & SIUL2_GPDI77_PDI_n_MASK) 4444 /*! @} */ 4445 4446 /*! @name GPDI76 - SIUL2 GPIO Pad Data Input Register */ 4447 /*! @{ */ 4448 4449 #define SIUL2_GPDI76_PDI_n_MASK (0x1U) 4450 #define SIUL2_GPDI76_PDI_n_SHIFT (0U) 4451 #define SIUL2_GPDI76_PDI_n_WIDTH (1U) 4452 #define SIUL2_GPDI76_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI76_PDI_n_SHIFT)) & SIUL2_GPDI76_PDI_n_MASK) 4453 /*! @} */ 4454 4455 /*! @name GPDI83 - SIUL2 GPIO Pad Data Input Register */ 4456 /*! @{ */ 4457 4458 #define SIUL2_GPDI83_PDI_n_MASK (0x1U) 4459 #define SIUL2_GPDI83_PDI_n_SHIFT (0U) 4460 #define SIUL2_GPDI83_PDI_n_WIDTH (1U) 4461 #define SIUL2_GPDI83_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI83_PDI_n_SHIFT)) & SIUL2_GPDI83_PDI_n_MASK) 4462 /*! @} */ 4463 4464 /*! @name GPDI82 - SIUL2 GPIO Pad Data Input Register */ 4465 /*! @{ */ 4466 4467 #define SIUL2_GPDI82_PDI_n_MASK (0x1U) 4468 #define SIUL2_GPDI82_PDI_n_SHIFT (0U) 4469 #define SIUL2_GPDI82_PDI_n_WIDTH (1U) 4470 #define SIUL2_GPDI82_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI82_PDI_n_SHIFT)) & SIUL2_GPDI82_PDI_n_MASK) 4471 /*! @} */ 4472 4473 /*! @name GPDI81 - SIUL2 GPIO Pad Data Input Register */ 4474 /*! @{ */ 4475 4476 #define SIUL2_GPDI81_PDI_n_MASK (0x1U) 4477 #define SIUL2_GPDI81_PDI_n_SHIFT (0U) 4478 #define SIUL2_GPDI81_PDI_n_WIDTH (1U) 4479 #define SIUL2_GPDI81_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI81_PDI_n_SHIFT)) & SIUL2_GPDI81_PDI_n_MASK) 4480 /*! @} */ 4481 4482 /*! @name GPDI80 - SIUL2 GPIO Pad Data Input Register */ 4483 /*! @{ */ 4484 4485 #define SIUL2_GPDI80_PDI_n_MASK (0x1U) 4486 #define SIUL2_GPDI80_PDI_n_SHIFT (0U) 4487 #define SIUL2_GPDI80_PDI_n_WIDTH (1U) 4488 #define SIUL2_GPDI80_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI80_PDI_n_SHIFT)) & SIUL2_GPDI80_PDI_n_MASK) 4489 /*! @} */ 4490 4491 /*! @name GPDI87 - SIUL2 GPIO Pad Data Input Register */ 4492 /*! @{ */ 4493 4494 #define SIUL2_GPDI87_PDI_n_MASK (0x1U) 4495 #define SIUL2_GPDI87_PDI_n_SHIFT (0U) 4496 #define SIUL2_GPDI87_PDI_n_WIDTH (1U) 4497 #define SIUL2_GPDI87_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI87_PDI_n_SHIFT)) & SIUL2_GPDI87_PDI_n_MASK) 4498 /*! @} */ 4499 4500 /*! @name GPDI86 - SIUL2 GPIO Pad Data Input Register */ 4501 /*! @{ */ 4502 4503 #define SIUL2_GPDI86_PDI_n_MASK (0x1U) 4504 #define SIUL2_GPDI86_PDI_n_SHIFT (0U) 4505 #define SIUL2_GPDI86_PDI_n_WIDTH (1U) 4506 #define SIUL2_GPDI86_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI86_PDI_n_SHIFT)) & SIUL2_GPDI86_PDI_n_MASK) 4507 /*! @} */ 4508 4509 /*! @name GPDI85 - SIUL2 GPIO Pad Data Input Register */ 4510 /*! @{ */ 4511 4512 #define SIUL2_GPDI85_PDI_n_MASK (0x1U) 4513 #define SIUL2_GPDI85_PDI_n_SHIFT (0U) 4514 #define SIUL2_GPDI85_PDI_n_WIDTH (1U) 4515 #define SIUL2_GPDI85_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI85_PDI_n_SHIFT)) & SIUL2_GPDI85_PDI_n_MASK) 4516 /*! @} */ 4517 4518 /*! @name GPDI84 - SIUL2 GPIO Pad Data Input Register */ 4519 /*! @{ */ 4520 4521 #define SIUL2_GPDI84_PDI_n_MASK (0x1U) 4522 #define SIUL2_GPDI84_PDI_n_SHIFT (0U) 4523 #define SIUL2_GPDI84_PDI_n_WIDTH (1U) 4524 #define SIUL2_GPDI84_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI84_PDI_n_SHIFT)) & SIUL2_GPDI84_PDI_n_MASK) 4525 /*! @} */ 4526 4527 /*! @name GPDI91 - SIUL2 GPIO Pad Data Input Register */ 4528 /*! @{ */ 4529 4530 #define SIUL2_GPDI91_PDI_n_MASK (0x1U) 4531 #define SIUL2_GPDI91_PDI_n_SHIFT (0U) 4532 #define SIUL2_GPDI91_PDI_n_WIDTH (1U) 4533 #define SIUL2_GPDI91_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI91_PDI_n_SHIFT)) & SIUL2_GPDI91_PDI_n_MASK) 4534 /*! @} */ 4535 4536 /*! @name GPDI90 - SIUL2 GPIO Pad Data Input Register */ 4537 /*! @{ */ 4538 4539 #define SIUL2_GPDI90_PDI_n_MASK (0x1U) 4540 #define SIUL2_GPDI90_PDI_n_SHIFT (0U) 4541 #define SIUL2_GPDI90_PDI_n_WIDTH (1U) 4542 #define SIUL2_GPDI90_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI90_PDI_n_SHIFT)) & SIUL2_GPDI90_PDI_n_MASK) 4543 /*! @} */ 4544 4545 /*! @name GPDI89 - SIUL2 GPIO Pad Data Input Register */ 4546 /*! @{ */ 4547 4548 #define SIUL2_GPDI89_PDI_n_MASK (0x1U) 4549 #define SIUL2_GPDI89_PDI_n_SHIFT (0U) 4550 #define SIUL2_GPDI89_PDI_n_WIDTH (1U) 4551 #define SIUL2_GPDI89_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI89_PDI_n_SHIFT)) & SIUL2_GPDI89_PDI_n_MASK) 4552 /*! @} */ 4553 4554 /*! @name GPDI88 - SIUL2 GPIO Pad Data Input Register */ 4555 /*! @{ */ 4556 4557 #define SIUL2_GPDI88_PDI_n_MASK (0x1U) 4558 #define SIUL2_GPDI88_PDI_n_SHIFT (0U) 4559 #define SIUL2_GPDI88_PDI_n_WIDTH (1U) 4560 #define SIUL2_GPDI88_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI88_PDI_n_SHIFT)) & SIUL2_GPDI88_PDI_n_MASK) 4561 /*! @} */ 4562 4563 /*! @name GPDI95 - SIUL2 GPIO Pad Data Input Register */ 4564 /*! @{ */ 4565 4566 #define SIUL2_GPDI95_PDI_n_MASK (0x1U) 4567 #define SIUL2_GPDI95_PDI_n_SHIFT (0U) 4568 #define SIUL2_GPDI95_PDI_n_WIDTH (1U) 4569 #define SIUL2_GPDI95_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI95_PDI_n_SHIFT)) & SIUL2_GPDI95_PDI_n_MASK) 4570 /*! @} */ 4571 4572 /*! @name GPDI94 - SIUL2 GPIO Pad Data Input Register */ 4573 /*! @{ */ 4574 4575 #define SIUL2_GPDI94_PDI_n_MASK (0x1U) 4576 #define SIUL2_GPDI94_PDI_n_SHIFT (0U) 4577 #define SIUL2_GPDI94_PDI_n_WIDTH (1U) 4578 #define SIUL2_GPDI94_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI94_PDI_n_SHIFT)) & SIUL2_GPDI94_PDI_n_MASK) 4579 /*! @} */ 4580 4581 /*! @name GPDI93 - SIUL2 GPIO Pad Data Input Register */ 4582 /*! @{ */ 4583 4584 #define SIUL2_GPDI93_PDI_n_MASK (0x1U) 4585 #define SIUL2_GPDI93_PDI_n_SHIFT (0U) 4586 #define SIUL2_GPDI93_PDI_n_WIDTH (1U) 4587 #define SIUL2_GPDI93_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI93_PDI_n_SHIFT)) & SIUL2_GPDI93_PDI_n_MASK) 4588 /*! @} */ 4589 4590 /*! @name GPDI92 - SIUL2 GPIO Pad Data Input Register */ 4591 /*! @{ */ 4592 4593 #define SIUL2_GPDI92_PDI_n_MASK (0x1U) 4594 #define SIUL2_GPDI92_PDI_n_SHIFT (0U) 4595 #define SIUL2_GPDI92_PDI_n_WIDTH (1U) 4596 #define SIUL2_GPDI92_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI92_PDI_n_SHIFT)) & SIUL2_GPDI92_PDI_n_MASK) 4597 /*! @} */ 4598 4599 /*! @name GPDI99 - SIUL2 GPIO Pad Data Input Register */ 4600 /*! @{ */ 4601 4602 #define SIUL2_GPDI99_PDI_n_MASK (0x1U) 4603 #define SIUL2_GPDI99_PDI_n_SHIFT (0U) 4604 #define SIUL2_GPDI99_PDI_n_WIDTH (1U) 4605 #define SIUL2_GPDI99_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI99_PDI_n_SHIFT)) & SIUL2_GPDI99_PDI_n_MASK) 4606 /*! @} */ 4607 4608 /*! @name GPDI98 - SIUL2 GPIO Pad Data Input Register */ 4609 /*! @{ */ 4610 4611 #define SIUL2_GPDI98_PDI_n_MASK (0x1U) 4612 #define SIUL2_GPDI98_PDI_n_SHIFT (0U) 4613 #define SIUL2_GPDI98_PDI_n_WIDTH (1U) 4614 #define SIUL2_GPDI98_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI98_PDI_n_SHIFT)) & SIUL2_GPDI98_PDI_n_MASK) 4615 /*! @} */ 4616 4617 /*! @name GPDI97 - SIUL2 GPIO Pad Data Input Register */ 4618 /*! @{ */ 4619 4620 #define SIUL2_GPDI97_PDI_n_MASK (0x1U) 4621 #define SIUL2_GPDI97_PDI_n_SHIFT (0U) 4622 #define SIUL2_GPDI97_PDI_n_WIDTH (1U) 4623 #define SIUL2_GPDI97_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI97_PDI_n_SHIFT)) & SIUL2_GPDI97_PDI_n_MASK) 4624 /*! @} */ 4625 4626 /*! @name GPDI96 - SIUL2 GPIO Pad Data Input Register */ 4627 /*! @{ */ 4628 4629 #define SIUL2_GPDI96_PDI_n_MASK (0x1U) 4630 #define SIUL2_GPDI96_PDI_n_SHIFT (0U) 4631 #define SIUL2_GPDI96_PDI_n_WIDTH (1U) 4632 #define SIUL2_GPDI96_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI96_PDI_n_SHIFT)) & SIUL2_GPDI96_PDI_n_MASK) 4633 /*! @} */ 4634 4635 /*! @name GPDI103 - SIUL2 GPIO Pad Data Input Register */ 4636 /*! @{ */ 4637 4638 #define SIUL2_GPDI103_PDI_n_MASK (0x1U) 4639 #define SIUL2_GPDI103_PDI_n_SHIFT (0U) 4640 #define SIUL2_GPDI103_PDI_n_WIDTH (1U) 4641 #define SIUL2_GPDI103_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI103_PDI_n_SHIFT)) & SIUL2_GPDI103_PDI_n_MASK) 4642 /*! @} */ 4643 4644 /*! @name GPDI102 - SIUL2 GPIO Pad Data Input Register */ 4645 /*! @{ */ 4646 4647 #define SIUL2_GPDI102_PDI_n_MASK (0x1U) 4648 #define SIUL2_GPDI102_PDI_n_SHIFT (0U) 4649 #define SIUL2_GPDI102_PDI_n_WIDTH (1U) 4650 #define SIUL2_GPDI102_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI102_PDI_n_SHIFT)) & SIUL2_GPDI102_PDI_n_MASK) 4651 /*! @} */ 4652 4653 /*! @name GPDI101 - SIUL2 GPIO Pad Data Input Register */ 4654 /*! @{ */ 4655 4656 #define SIUL2_GPDI101_PDI_n_MASK (0x1U) 4657 #define SIUL2_GPDI101_PDI_n_SHIFT (0U) 4658 #define SIUL2_GPDI101_PDI_n_WIDTH (1U) 4659 #define SIUL2_GPDI101_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI101_PDI_n_SHIFT)) & SIUL2_GPDI101_PDI_n_MASK) 4660 /*! @} */ 4661 4662 /*! @name GPDI100 - SIUL2 GPIO Pad Data Input Register */ 4663 /*! @{ */ 4664 4665 #define SIUL2_GPDI100_PDI_n_MASK (0x1U) 4666 #define SIUL2_GPDI100_PDI_n_SHIFT (0U) 4667 #define SIUL2_GPDI100_PDI_n_WIDTH (1U) 4668 #define SIUL2_GPDI100_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI100_PDI_n_SHIFT)) & SIUL2_GPDI100_PDI_n_MASK) 4669 /*! @} */ 4670 4671 /*! @name GPDI107 - SIUL2 GPIO Pad Data Input Register */ 4672 /*! @{ */ 4673 4674 #define SIUL2_GPDI107_PDI_n_MASK (0x1U) 4675 #define SIUL2_GPDI107_PDI_n_SHIFT (0U) 4676 #define SIUL2_GPDI107_PDI_n_WIDTH (1U) 4677 #define SIUL2_GPDI107_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI107_PDI_n_SHIFT)) & SIUL2_GPDI107_PDI_n_MASK) 4678 /*! @} */ 4679 4680 /*! @name GPDI106 - SIUL2 GPIO Pad Data Input Register */ 4681 /*! @{ */ 4682 4683 #define SIUL2_GPDI106_PDI_n_MASK (0x1U) 4684 #define SIUL2_GPDI106_PDI_n_SHIFT (0U) 4685 #define SIUL2_GPDI106_PDI_n_WIDTH (1U) 4686 #define SIUL2_GPDI106_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI106_PDI_n_SHIFT)) & SIUL2_GPDI106_PDI_n_MASK) 4687 /*! @} */ 4688 4689 /*! @name GPDI105 - SIUL2 GPIO Pad Data Input Register */ 4690 /*! @{ */ 4691 4692 #define SIUL2_GPDI105_PDI_n_MASK (0x1U) 4693 #define SIUL2_GPDI105_PDI_n_SHIFT (0U) 4694 #define SIUL2_GPDI105_PDI_n_WIDTH (1U) 4695 #define SIUL2_GPDI105_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI105_PDI_n_SHIFT)) & SIUL2_GPDI105_PDI_n_MASK) 4696 /*! @} */ 4697 4698 /*! @name GPDI104 - SIUL2 GPIO Pad Data Input Register */ 4699 /*! @{ */ 4700 4701 #define SIUL2_GPDI104_PDI_n_MASK (0x1U) 4702 #define SIUL2_GPDI104_PDI_n_SHIFT (0U) 4703 #define SIUL2_GPDI104_PDI_n_WIDTH (1U) 4704 #define SIUL2_GPDI104_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI104_PDI_n_SHIFT)) & SIUL2_GPDI104_PDI_n_MASK) 4705 /*! @} */ 4706 4707 /*! @name GPDI111 - SIUL2 GPIO Pad Data Input Register */ 4708 /*! @{ */ 4709 4710 #define SIUL2_GPDI111_PDI_n_MASK (0x1U) 4711 #define SIUL2_GPDI111_PDI_n_SHIFT (0U) 4712 #define SIUL2_GPDI111_PDI_n_WIDTH (1U) 4713 #define SIUL2_GPDI111_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI111_PDI_n_SHIFT)) & SIUL2_GPDI111_PDI_n_MASK) 4714 /*! @} */ 4715 4716 /*! @name GPDI110 - SIUL2 GPIO Pad Data Input Register */ 4717 /*! @{ */ 4718 4719 #define SIUL2_GPDI110_PDI_n_MASK (0x1U) 4720 #define SIUL2_GPDI110_PDI_n_SHIFT (0U) 4721 #define SIUL2_GPDI110_PDI_n_WIDTH (1U) 4722 #define SIUL2_GPDI110_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI110_PDI_n_SHIFT)) & SIUL2_GPDI110_PDI_n_MASK) 4723 /*! @} */ 4724 4725 /*! @name GPDI109 - SIUL2 GPIO Pad Data Input Register */ 4726 /*! @{ */ 4727 4728 #define SIUL2_GPDI109_PDI_n_MASK (0x1U) 4729 #define SIUL2_GPDI109_PDI_n_SHIFT (0U) 4730 #define SIUL2_GPDI109_PDI_n_WIDTH (1U) 4731 #define SIUL2_GPDI109_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI109_PDI_n_SHIFT)) & SIUL2_GPDI109_PDI_n_MASK) 4732 /*! @} */ 4733 4734 /*! @name GPDI108 - SIUL2 GPIO Pad Data Input Register */ 4735 /*! @{ */ 4736 4737 #define SIUL2_GPDI108_PDI_n_MASK (0x1U) 4738 #define SIUL2_GPDI108_PDI_n_SHIFT (0U) 4739 #define SIUL2_GPDI108_PDI_n_WIDTH (1U) 4740 #define SIUL2_GPDI108_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI108_PDI_n_SHIFT)) & SIUL2_GPDI108_PDI_n_MASK) 4741 /*! @} */ 4742 4743 /*! @name GPDI115 - SIUL2 GPIO Pad Data Input Register */ 4744 /*! @{ */ 4745 4746 #define SIUL2_GPDI115_PDI_n_MASK (0x1U) 4747 #define SIUL2_GPDI115_PDI_n_SHIFT (0U) 4748 #define SIUL2_GPDI115_PDI_n_WIDTH (1U) 4749 #define SIUL2_GPDI115_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI115_PDI_n_SHIFT)) & SIUL2_GPDI115_PDI_n_MASK) 4750 /*! @} */ 4751 4752 /*! @name GPDI114 - SIUL2 GPIO Pad Data Input Register */ 4753 /*! @{ */ 4754 4755 #define SIUL2_GPDI114_PDI_n_MASK (0x1U) 4756 #define SIUL2_GPDI114_PDI_n_SHIFT (0U) 4757 #define SIUL2_GPDI114_PDI_n_WIDTH (1U) 4758 #define SIUL2_GPDI114_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI114_PDI_n_SHIFT)) & SIUL2_GPDI114_PDI_n_MASK) 4759 /*! @} */ 4760 4761 /*! @name GPDI113 - SIUL2 GPIO Pad Data Input Register */ 4762 /*! @{ */ 4763 4764 #define SIUL2_GPDI113_PDI_n_MASK (0x1U) 4765 #define SIUL2_GPDI113_PDI_n_SHIFT (0U) 4766 #define SIUL2_GPDI113_PDI_n_WIDTH (1U) 4767 #define SIUL2_GPDI113_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI113_PDI_n_SHIFT)) & SIUL2_GPDI113_PDI_n_MASK) 4768 /*! @} */ 4769 4770 /*! @name GPDI112 - SIUL2 GPIO Pad Data Input Register */ 4771 /*! @{ */ 4772 4773 #define SIUL2_GPDI112_PDI_n_MASK (0x1U) 4774 #define SIUL2_GPDI112_PDI_n_SHIFT (0U) 4775 #define SIUL2_GPDI112_PDI_n_WIDTH (1U) 4776 #define SIUL2_GPDI112_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI112_PDI_n_SHIFT)) & SIUL2_GPDI112_PDI_n_MASK) 4777 /*! @} */ 4778 4779 /*! @name GPDI119 - SIUL2 GPIO Pad Data Input Register */ 4780 /*! @{ */ 4781 4782 #define SIUL2_GPDI119_PDI_n_MASK (0x1U) 4783 #define SIUL2_GPDI119_PDI_n_SHIFT (0U) 4784 #define SIUL2_GPDI119_PDI_n_WIDTH (1U) 4785 #define SIUL2_GPDI119_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI119_PDI_n_SHIFT)) & SIUL2_GPDI119_PDI_n_MASK) 4786 /*! @} */ 4787 4788 /*! @name GPDI118 - SIUL2 GPIO Pad Data Input Register */ 4789 /*! @{ */ 4790 4791 #define SIUL2_GPDI118_PDI_n_MASK (0x1U) 4792 #define SIUL2_GPDI118_PDI_n_SHIFT (0U) 4793 #define SIUL2_GPDI118_PDI_n_WIDTH (1U) 4794 #define SIUL2_GPDI118_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI118_PDI_n_SHIFT)) & SIUL2_GPDI118_PDI_n_MASK) 4795 /*! @} */ 4796 4797 /*! @name GPDI117 - SIUL2 GPIO Pad Data Input Register */ 4798 /*! @{ */ 4799 4800 #define SIUL2_GPDI117_PDI_n_MASK (0x1U) 4801 #define SIUL2_GPDI117_PDI_n_SHIFT (0U) 4802 #define SIUL2_GPDI117_PDI_n_WIDTH (1U) 4803 #define SIUL2_GPDI117_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI117_PDI_n_SHIFT)) & SIUL2_GPDI117_PDI_n_MASK) 4804 /*! @} */ 4805 4806 /*! @name GPDI116 - SIUL2 GPIO Pad Data Input Register */ 4807 /*! @{ */ 4808 4809 #define SIUL2_GPDI116_PDI_n_MASK (0x1U) 4810 #define SIUL2_GPDI116_PDI_n_SHIFT (0U) 4811 #define SIUL2_GPDI116_PDI_n_WIDTH (1U) 4812 #define SIUL2_GPDI116_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI116_PDI_n_SHIFT)) & SIUL2_GPDI116_PDI_n_MASK) 4813 /*! @} */ 4814 4815 /*! @name GPDI123 - SIUL2 GPIO Pad Data Input Register */ 4816 /*! @{ */ 4817 4818 #define SIUL2_GPDI123_PDI_n_MASK (0x1U) 4819 #define SIUL2_GPDI123_PDI_n_SHIFT (0U) 4820 #define SIUL2_GPDI123_PDI_n_WIDTH (1U) 4821 #define SIUL2_GPDI123_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI123_PDI_n_SHIFT)) & SIUL2_GPDI123_PDI_n_MASK) 4822 /*! @} */ 4823 4824 /*! @name GPDI122 - SIUL2 GPIO Pad Data Input Register */ 4825 /*! @{ */ 4826 4827 #define SIUL2_GPDI122_PDI_n_MASK (0x1U) 4828 #define SIUL2_GPDI122_PDI_n_SHIFT (0U) 4829 #define SIUL2_GPDI122_PDI_n_WIDTH (1U) 4830 #define SIUL2_GPDI122_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI122_PDI_n_SHIFT)) & SIUL2_GPDI122_PDI_n_MASK) 4831 /*! @} */ 4832 4833 /*! @name GPDI121 - SIUL2 GPIO Pad Data Input Register */ 4834 /*! @{ */ 4835 4836 #define SIUL2_GPDI121_PDI_n_MASK (0x1U) 4837 #define SIUL2_GPDI121_PDI_n_SHIFT (0U) 4838 #define SIUL2_GPDI121_PDI_n_WIDTH (1U) 4839 #define SIUL2_GPDI121_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI121_PDI_n_SHIFT)) & SIUL2_GPDI121_PDI_n_MASK) 4840 /*! @} */ 4841 4842 /*! @name GPDI120 - SIUL2 GPIO Pad Data Input Register */ 4843 /*! @{ */ 4844 4845 #define SIUL2_GPDI120_PDI_n_MASK (0x1U) 4846 #define SIUL2_GPDI120_PDI_n_SHIFT (0U) 4847 #define SIUL2_GPDI120_PDI_n_WIDTH (1U) 4848 #define SIUL2_GPDI120_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI120_PDI_n_SHIFT)) & SIUL2_GPDI120_PDI_n_MASK) 4849 /*! @} */ 4850 4851 /*! @name GPDI127 - SIUL2 GPIO Pad Data Input Register */ 4852 /*! @{ */ 4853 4854 #define SIUL2_GPDI127_PDI_n_MASK (0x1U) 4855 #define SIUL2_GPDI127_PDI_n_SHIFT (0U) 4856 #define SIUL2_GPDI127_PDI_n_WIDTH (1U) 4857 #define SIUL2_GPDI127_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI127_PDI_n_SHIFT)) & SIUL2_GPDI127_PDI_n_MASK) 4858 /*! @} */ 4859 4860 /*! @name GPDI126 - SIUL2 GPIO Pad Data Input Register */ 4861 /*! @{ */ 4862 4863 #define SIUL2_GPDI126_PDI_n_MASK (0x1U) 4864 #define SIUL2_GPDI126_PDI_n_SHIFT (0U) 4865 #define SIUL2_GPDI126_PDI_n_WIDTH (1U) 4866 #define SIUL2_GPDI126_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI126_PDI_n_SHIFT)) & SIUL2_GPDI126_PDI_n_MASK) 4867 /*! @} */ 4868 4869 /*! @name GPDI125 - SIUL2 GPIO Pad Data Input Register */ 4870 /*! @{ */ 4871 4872 #define SIUL2_GPDI125_PDI_n_MASK (0x1U) 4873 #define SIUL2_GPDI125_PDI_n_SHIFT (0U) 4874 #define SIUL2_GPDI125_PDI_n_WIDTH (1U) 4875 #define SIUL2_GPDI125_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI125_PDI_n_SHIFT)) & SIUL2_GPDI125_PDI_n_MASK) 4876 /*! @} */ 4877 4878 /*! @name GPDI124 - SIUL2 GPIO Pad Data Input Register */ 4879 /*! @{ */ 4880 4881 #define SIUL2_GPDI124_PDI_n_MASK (0x1U) 4882 #define SIUL2_GPDI124_PDI_n_SHIFT (0U) 4883 #define SIUL2_GPDI124_PDI_n_WIDTH (1U) 4884 #define SIUL2_GPDI124_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI124_PDI_n_SHIFT)) & SIUL2_GPDI124_PDI_n_MASK) 4885 /*! @} */ 4886 4887 /*! @name GPDI131 - SIUL2 GPIO Pad Data Input Register */ 4888 /*! @{ */ 4889 4890 #define SIUL2_GPDI131_PDI_n_MASK (0x1U) 4891 #define SIUL2_GPDI131_PDI_n_SHIFT (0U) 4892 #define SIUL2_GPDI131_PDI_n_WIDTH (1U) 4893 #define SIUL2_GPDI131_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI131_PDI_n_SHIFT)) & SIUL2_GPDI131_PDI_n_MASK) 4894 /*! @} */ 4895 4896 /*! @name GPDI130 - SIUL2 GPIO Pad Data Input Register */ 4897 /*! @{ */ 4898 4899 #define SIUL2_GPDI130_PDI_n_MASK (0x1U) 4900 #define SIUL2_GPDI130_PDI_n_SHIFT (0U) 4901 #define SIUL2_GPDI130_PDI_n_WIDTH (1U) 4902 #define SIUL2_GPDI130_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI130_PDI_n_SHIFT)) & SIUL2_GPDI130_PDI_n_MASK) 4903 /*! @} */ 4904 4905 /*! @name GPDI129 - SIUL2 GPIO Pad Data Input Register */ 4906 /*! @{ */ 4907 4908 #define SIUL2_GPDI129_PDI_n_MASK (0x1U) 4909 #define SIUL2_GPDI129_PDI_n_SHIFT (0U) 4910 #define SIUL2_GPDI129_PDI_n_WIDTH (1U) 4911 #define SIUL2_GPDI129_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI129_PDI_n_SHIFT)) & SIUL2_GPDI129_PDI_n_MASK) 4912 /*! @} */ 4913 4914 /*! @name GPDI128 - SIUL2 GPIO Pad Data Input Register */ 4915 /*! @{ */ 4916 4917 #define SIUL2_GPDI128_PDI_n_MASK (0x1U) 4918 #define SIUL2_GPDI128_PDI_n_SHIFT (0U) 4919 #define SIUL2_GPDI128_PDI_n_WIDTH (1U) 4920 #define SIUL2_GPDI128_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI128_PDI_n_SHIFT)) & SIUL2_GPDI128_PDI_n_MASK) 4921 /*! @} */ 4922 4923 /*! @name GPDI135 - SIUL2 GPIO Pad Data Input Register */ 4924 /*! @{ */ 4925 4926 #define SIUL2_GPDI135_PDI_n_MASK (0x1U) 4927 #define SIUL2_GPDI135_PDI_n_SHIFT (0U) 4928 #define SIUL2_GPDI135_PDI_n_WIDTH (1U) 4929 #define SIUL2_GPDI135_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI135_PDI_n_SHIFT)) & SIUL2_GPDI135_PDI_n_MASK) 4930 /*! @} */ 4931 4932 /*! @name GPDI134 - SIUL2 GPIO Pad Data Input Register */ 4933 /*! @{ */ 4934 4935 #define SIUL2_GPDI134_PDI_n_MASK (0x1U) 4936 #define SIUL2_GPDI134_PDI_n_SHIFT (0U) 4937 #define SIUL2_GPDI134_PDI_n_WIDTH (1U) 4938 #define SIUL2_GPDI134_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI134_PDI_n_SHIFT)) & SIUL2_GPDI134_PDI_n_MASK) 4939 /*! @} */ 4940 4941 /*! @name GPDI133 - SIUL2 GPIO Pad Data Input Register */ 4942 /*! @{ */ 4943 4944 #define SIUL2_GPDI133_PDI_n_MASK (0x1U) 4945 #define SIUL2_GPDI133_PDI_n_SHIFT (0U) 4946 #define SIUL2_GPDI133_PDI_n_WIDTH (1U) 4947 #define SIUL2_GPDI133_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI133_PDI_n_SHIFT)) & SIUL2_GPDI133_PDI_n_MASK) 4948 /*! @} */ 4949 4950 /*! @name GPDI132 - SIUL2 GPIO Pad Data Input Register */ 4951 /*! @{ */ 4952 4953 #define SIUL2_GPDI132_PDI_n_MASK (0x1U) 4954 #define SIUL2_GPDI132_PDI_n_SHIFT (0U) 4955 #define SIUL2_GPDI132_PDI_n_WIDTH (1U) 4956 #define SIUL2_GPDI132_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI132_PDI_n_SHIFT)) & SIUL2_GPDI132_PDI_n_MASK) 4957 /*! @} */ 4958 4959 /*! @name GPDI139 - SIUL2 GPIO Pad Data Input Register */ 4960 /*! @{ */ 4961 4962 #define SIUL2_GPDI139_PDI_n_MASK (0x1U) 4963 #define SIUL2_GPDI139_PDI_n_SHIFT (0U) 4964 #define SIUL2_GPDI139_PDI_n_WIDTH (1U) 4965 #define SIUL2_GPDI139_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI139_PDI_n_SHIFT)) & SIUL2_GPDI139_PDI_n_MASK) 4966 /*! @} */ 4967 4968 /*! @name GPDI138 - SIUL2 GPIO Pad Data Input Register */ 4969 /*! @{ */ 4970 4971 #define SIUL2_GPDI138_PDI_n_MASK (0x1U) 4972 #define SIUL2_GPDI138_PDI_n_SHIFT (0U) 4973 #define SIUL2_GPDI138_PDI_n_WIDTH (1U) 4974 #define SIUL2_GPDI138_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI138_PDI_n_SHIFT)) & SIUL2_GPDI138_PDI_n_MASK) 4975 /*! @} */ 4976 4977 /*! @name GPDI137 - SIUL2 GPIO Pad Data Input Register */ 4978 /*! @{ */ 4979 4980 #define SIUL2_GPDI137_PDI_n_MASK (0x1U) 4981 #define SIUL2_GPDI137_PDI_n_SHIFT (0U) 4982 #define SIUL2_GPDI137_PDI_n_WIDTH (1U) 4983 #define SIUL2_GPDI137_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI137_PDI_n_SHIFT)) & SIUL2_GPDI137_PDI_n_MASK) 4984 /*! @} */ 4985 4986 /*! @name GPDI136 - SIUL2 GPIO Pad Data Input Register */ 4987 /*! @{ */ 4988 4989 #define SIUL2_GPDI136_PDI_n_MASK (0x1U) 4990 #define SIUL2_GPDI136_PDI_n_SHIFT (0U) 4991 #define SIUL2_GPDI136_PDI_n_WIDTH (1U) 4992 #define SIUL2_GPDI136_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI136_PDI_n_SHIFT)) & SIUL2_GPDI136_PDI_n_MASK) 4993 /*! @} */ 4994 4995 /*! @name GPDI143 - SIUL2 GPIO Pad Data Input Register */ 4996 /*! @{ */ 4997 4998 #define SIUL2_GPDI143_PDI_n_MASK (0x1U) 4999 #define SIUL2_GPDI143_PDI_n_SHIFT (0U) 5000 #define SIUL2_GPDI143_PDI_n_WIDTH (1U) 5001 #define SIUL2_GPDI143_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI143_PDI_n_SHIFT)) & SIUL2_GPDI143_PDI_n_MASK) 5002 /*! @} */ 5003 5004 /*! @name GPDI142 - SIUL2 GPIO Pad Data Input Register */ 5005 /*! @{ */ 5006 5007 #define SIUL2_GPDI142_PDI_n_MASK (0x1U) 5008 #define SIUL2_GPDI142_PDI_n_SHIFT (0U) 5009 #define SIUL2_GPDI142_PDI_n_WIDTH (1U) 5010 #define SIUL2_GPDI142_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI142_PDI_n_SHIFT)) & SIUL2_GPDI142_PDI_n_MASK) 5011 /*! @} */ 5012 5013 /*! @name GPDI141 - SIUL2 GPIO Pad Data Input Register */ 5014 /*! @{ */ 5015 5016 #define SIUL2_GPDI141_PDI_n_MASK (0x1U) 5017 #define SIUL2_GPDI141_PDI_n_SHIFT (0U) 5018 #define SIUL2_GPDI141_PDI_n_WIDTH (1U) 5019 #define SIUL2_GPDI141_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI141_PDI_n_SHIFT)) & SIUL2_GPDI141_PDI_n_MASK) 5020 /*! @} */ 5021 5022 /*! @name GPDI140 - SIUL2 GPIO Pad Data Input Register */ 5023 /*! @{ */ 5024 5025 #define SIUL2_GPDI140_PDI_n_MASK (0x1U) 5026 #define SIUL2_GPDI140_PDI_n_SHIFT (0U) 5027 #define SIUL2_GPDI140_PDI_n_WIDTH (1U) 5028 #define SIUL2_GPDI140_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI140_PDI_n_SHIFT)) & SIUL2_GPDI140_PDI_n_MASK) 5029 /*! @} */ 5030 5031 /*! @name GPDI147 - SIUL2 GPIO Pad Data Input Register */ 5032 /*! @{ */ 5033 5034 #define SIUL2_GPDI147_PDI_n_MASK (0x1U) 5035 #define SIUL2_GPDI147_PDI_n_SHIFT (0U) 5036 #define SIUL2_GPDI147_PDI_n_WIDTH (1U) 5037 #define SIUL2_GPDI147_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI147_PDI_n_SHIFT)) & SIUL2_GPDI147_PDI_n_MASK) 5038 /*! @} */ 5039 5040 /*! @name GPDI146 - SIUL2 GPIO Pad Data Input Register */ 5041 /*! @{ */ 5042 5043 #define SIUL2_GPDI146_PDI_n_MASK (0x1U) 5044 #define SIUL2_GPDI146_PDI_n_SHIFT (0U) 5045 #define SIUL2_GPDI146_PDI_n_WIDTH (1U) 5046 #define SIUL2_GPDI146_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI146_PDI_n_SHIFT)) & SIUL2_GPDI146_PDI_n_MASK) 5047 /*! @} */ 5048 5049 /*! @name GPDI145 - SIUL2 GPIO Pad Data Input Register */ 5050 /*! @{ */ 5051 5052 #define SIUL2_GPDI145_PDI_n_MASK (0x1U) 5053 #define SIUL2_GPDI145_PDI_n_SHIFT (0U) 5054 #define SIUL2_GPDI145_PDI_n_WIDTH (1U) 5055 #define SIUL2_GPDI145_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI145_PDI_n_SHIFT)) & SIUL2_GPDI145_PDI_n_MASK) 5056 /*! @} */ 5057 5058 /*! @name GPDI144 - SIUL2 GPIO Pad Data Input Register */ 5059 /*! @{ */ 5060 5061 #define SIUL2_GPDI144_PDI_n_MASK (0x1U) 5062 #define SIUL2_GPDI144_PDI_n_SHIFT (0U) 5063 #define SIUL2_GPDI144_PDI_n_WIDTH (1U) 5064 #define SIUL2_GPDI144_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI144_PDI_n_SHIFT)) & SIUL2_GPDI144_PDI_n_MASK) 5065 /*! @} */ 5066 5067 /*! @name GPDI151 - SIUL2 GPIO Pad Data Input Register */ 5068 /*! @{ */ 5069 5070 #define SIUL2_GPDI151_PDI_n_MASK (0x1U) 5071 #define SIUL2_GPDI151_PDI_n_SHIFT (0U) 5072 #define SIUL2_GPDI151_PDI_n_WIDTH (1U) 5073 #define SIUL2_GPDI151_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI151_PDI_n_SHIFT)) & SIUL2_GPDI151_PDI_n_MASK) 5074 /*! @} */ 5075 5076 /*! @name GPDI150 - SIUL2 GPIO Pad Data Input Register */ 5077 /*! @{ */ 5078 5079 #define SIUL2_GPDI150_PDI_n_MASK (0x1U) 5080 #define SIUL2_GPDI150_PDI_n_SHIFT (0U) 5081 #define SIUL2_GPDI150_PDI_n_WIDTH (1U) 5082 #define SIUL2_GPDI150_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI150_PDI_n_SHIFT)) & SIUL2_GPDI150_PDI_n_MASK) 5083 /*! @} */ 5084 5085 /*! @name GPDI149 - SIUL2 GPIO Pad Data Input Register */ 5086 /*! @{ */ 5087 5088 #define SIUL2_GPDI149_PDI_n_MASK (0x1U) 5089 #define SIUL2_GPDI149_PDI_n_SHIFT (0U) 5090 #define SIUL2_GPDI149_PDI_n_WIDTH (1U) 5091 #define SIUL2_GPDI149_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI149_PDI_n_SHIFT)) & SIUL2_GPDI149_PDI_n_MASK) 5092 /*! @} */ 5093 5094 /*! @name GPDI148 - SIUL2 GPIO Pad Data Input Register */ 5095 /*! @{ */ 5096 5097 #define SIUL2_GPDI148_PDI_n_MASK (0x1U) 5098 #define SIUL2_GPDI148_PDI_n_SHIFT (0U) 5099 #define SIUL2_GPDI148_PDI_n_WIDTH (1U) 5100 #define SIUL2_GPDI148_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI148_PDI_n_SHIFT)) & SIUL2_GPDI148_PDI_n_MASK) 5101 /*! @} */ 5102 5103 /*! @name GPDI155 - SIUL2 GPIO Pad Data Input Register */ 5104 /*! @{ */ 5105 5106 #define SIUL2_GPDI155_PDI_n_MASK (0x1U) 5107 #define SIUL2_GPDI155_PDI_n_SHIFT (0U) 5108 #define SIUL2_GPDI155_PDI_n_WIDTH (1U) 5109 #define SIUL2_GPDI155_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI155_PDI_n_SHIFT)) & SIUL2_GPDI155_PDI_n_MASK) 5110 /*! @} */ 5111 5112 /*! @name GPDI154 - SIUL2 GPIO Pad Data Input Register */ 5113 /*! @{ */ 5114 5115 #define SIUL2_GPDI154_PDI_n_MASK (0x1U) 5116 #define SIUL2_GPDI154_PDI_n_SHIFT (0U) 5117 #define SIUL2_GPDI154_PDI_n_WIDTH (1U) 5118 #define SIUL2_GPDI154_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI154_PDI_n_SHIFT)) & SIUL2_GPDI154_PDI_n_MASK) 5119 /*! @} */ 5120 5121 /*! @name GPDI153 - SIUL2 GPIO Pad Data Input Register */ 5122 /*! @{ */ 5123 5124 #define SIUL2_GPDI153_PDI_n_MASK (0x1U) 5125 #define SIUL2_GPDI153_PDI_n_SHIFT (0U) 5126 #define SIUL2_GPDI153_PDI_n_WIDTH (1U) 5127 #define SIUL2_GPDI153_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI153_PDI_n_SHIFT)) & SIUL2_GPDI153_PDI_n_MASK) 5128 /*! @} */ 5129 5130 /*! @name GPDI152 - SIUL2 GPIO Pad Data Input Register */ 5131 /*! @{ */ 5132 5133 #define SIUL2_GPDI152_PDI_n_MASK (0x1U) 5134 #define SIUL2_GPDI152_PDI_n_SHIFT (0U) 5135 #define SIUL2_GPDI152_PDI_n_WIDTH (1U) 5136 #define SIUL2_GPDI152_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI152_PDI_n_SHIFT)) & SIUL2_GPDI152_PDI_n_MASK) 5137 /*! @} */ 5138 5139 /*! @name GPDI159 - SIUL2 GPIO Pad Data Input Register */ 5140 /*! @{ */ 5141 5142 #define SIUL2_GPDI159_PDI_n_MASK (0x1U) 5143 #define SIUL2_GPDI159_PDI_n_SHIFT (0U) 5144 #define SIUL2_GPDI159_PDI_n_WIDTH (1U) 5145 #define SIUL2_GPDI159_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI159_PDI_n_SHIFT)) & SIUL2_GPDI159_PDI_n_MASK) 5146 /*! @} */ 5147 5148 /*! @name GPDI158 - SIUL2 GPIO Pad Data Input Register */ 5149 /*! @{ */ 5150 5151 #define SIUL2_GPDI158_PDI_n_MASK (0x1U) 5152 #define SIUL2_GPDI158_PDI_n_SHIFT (0U) 5153 #define SIUL2_GPDI158_PDI_n_WIDTH (1U) 5154 #define SIUL2_GPDI158_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI158_PDI_n_SHIFT)) & SIUL2_GPDI158_PDI_n_MASK) 5155 /*! @} */ 5156 5157 /*! @name GPDI157 - SIUL2 GPIO Pad Data Input Register */ 5158 /*! @{ */ 5159 5160 #define SIUL2_GPDI157_PDI_n_MASK (0x1U) 5161 #define SIUL2_GPDI157_PDI_n_SHIFT (0U) 5162 #define SIUL2_GPDI157_PDI_n_WIDTH (1U) 5163 #define SIUL2_GPDI157_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI157_PDI_n_SHIFT)) & SIUL2_GPDI157_PDI_n_MASK) 5164 /*! @} */ 5165 5166 /*! @name GPDI156 - SIUL2 GPIO Pad Data Input Register */ 5167 /*! @{ */ 5168 5169 #define SIUL2_GPDI156_PDI_n_MASK (0x1U) 5170 #define SIUL2_GPDI156_PDI_n_SHIFT (0U) 5171 #define SIUL2_GPDI156_PDI_n_WIDTH (1U) 5172 #define SIUL2_GPDI156_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI156_PDI_n_SHIFT)) & SIUL2_GPDI156_PDI_n_MASK) 5173 /*! @} */ 5174 5175 /*! @name GPDI163 - SIUL2 GPIO Pad Data Input Register */ 5176 /*! @{ */ 5177 5178 #define SIUL2_GPDI163_PDI_n_MASK (0x1U) 5179 #define SIUL2_GPDI163_PDI_n_SHIFT (0U) 5180 #define SIUL2_GPDI163_PDI_n_WIDTH (1U) 5181 #define SIUL2_GPDI163_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI163_PDI_n_SHIFT)) & SIUL2_GPDI163_PDI_n_MASK) 5182 /*! @} */ 5183 5184 /*! @name GPDI162 - SIUL2 GPIO Pad Data Input Register */ 5185 /*! @{ */ 5186 5187 #define SIUL2_GPDI162_PDI_n_MASK (0x1U) 5188 #define SIUL2_GPDI162_PDI_n_SHIFT (0U) 5189 #define SIUL2_GPDI162_PDI_n_WIDTH (1U) 5190 #define SIUL2_GPDI162_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI162_PDI_n_SHIFT)) & SIUL2_GPDI162_PDI_n_MASK) 5191 /*! @} */ 5192 5193 /*! @name GPDI161 - SIUL2 GPIO Pad Data Input Register */ 5194 /*! @{ */ 5195 5196 #define SIUL2_GPDI161_PDI_n_MASK (0x1U) 5197 #define SIUL2_GPDI161_PDI_n_SHIFT (0U) 5198 #define SIUL2_GPDI161_PDI_n_WIDTH (1U) 5199 #define SIUL2_GPDI161_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI161_PDI_n_SHIFT)) & SIUL2_GPDI161_PDI_n_MASK) 5200 /*! @} */ 5201 5202 /*! @name GPDI160 - SIUL2 GPIO Pad Data Input Register */ 5203 /*! @{ */ 5204 5205 #define SIUL2_GPDI160_PDI_n_MASK (0x1U) 5206 #define SIUL2_GPDI160_PDI_n_SHIFT (0U) 5207 #define SIUL2_GPDI160_PDI_n_WIDTH (1U) 5208 #define SIUL2_GPDI160_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI160_PDI_n_SHIFT)) & SIUL2_GPDI160_PDI_n_MASK) 5209 /*! @} */ 5210 5211 /*! @name GPDI167 - SIUL2 GPIO Pad Data Input Register */ 5212 /*! @{ */ 5213 5214 #define SIUL2_GPDI167_PDI_n_MASK (0x1U) 5215 #define SIUL2_GPDI167_PDI_n_SHIFT (0U) 5216 #define SIUL2_GPDI167_PDI_n_WIDTH (1U) 5217 #define SIUL2_GPDI167_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI167_PDI_n_SHIFT)) & SIUL2_GPDI167_PDI_n_MASK) 5218 /*! @} */ 5219 5220 /*! @name GPDI166 - SIUL2 GPIO Pad Data Input Register */ 5221 /*! @{ */ 5222 5223 #define SIUL2_GPDI166_PDI_n_MASK (0x1U) 5224 #define SIUL2_GPDI166_PDI_n_SHIFT (0U) 5225 #define SIUL2_GPDI166_PDI_n_WIDTH (1U) 5226 #define SIUL2_GPDI166_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI166_PDI_n_SHIFT)) & SIUL2_GPDI166_PDI_n_MASK) 5227 /*! @} */ 5228 5229 /*! @name GPDI165 - SIUL2 GPIO Pad Data Input Register */ 5230 /*! @{ */ 5231 5232 #define SIUL2_GPDI165_PDI_n_MASK (0x1U) 5233 #define SIUL2_GPDI165_PDI_n_SHIFT (0U) 5234 #define SIUL2_GPDI165_PDI_n_WIDTH (1U) 5235 #define SIUL2_GPDI165_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI165_PDI_n_SHIFT)) & SIUL2_GPDI165_PDI_n_MASK) 5236 /*! @} */ 5237 5238 /*! @name GPDI164 - SIUL2 GPIO Pad Data Input Register */ 5239 /*! @{ */ 5240 5241 #define SIUL2_GPDI164_PDI_n_MASK (0x1U) 5242 #define SIUL2_GPDI164_PDI_n_SHIFT (0U) 5243 #define SIUL2_GPDI164_PDI_n_WIDTH (1U) 5244 #define SIUL2_GPDI164_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI164_PDI_n_SHIFT)) & SIUL2_GPDI164_PDI_n_MASK) 5245 /*! @} */ 5246 5247 /*! @name GPDI171 - SIUL2 GPIO Pad Data Input Register */ 5248 /*! @{ */ 5249 5250 #define SIUL2_GPDI171_PDI_n_MASK (0x1U) 5251 #define SIUL2_GPDI171_PDI_n_SHIFT (0U) 5252 #define SIUL2_GPDI171_PDI_n_WIDTH (1U) 5253 #define SIUL2_GPDI171_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI171_PDI_n_SHIFT)) & SIUL2_GPDI171_PDI_n_MASK) 5254 /*! @} */ 5255 5256 /*! @name GPDI170 - SIUL2 GPIO Pad Data Input Register */ 5257 /*! @{ */ 5258 5259 #define SIUL2_GPDI170_PDI_n_MASK (0x1U) 5260 #define SIUL2_GPDI170_PDI_n_SHIFT (0U) 5261 #define SIUL2_GPDI170_PDI_n_WIDTH (1U) 5262 #define SIUL2_GPDI170_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI170_PDI_n_SHIFT)) & SIUL2_GPDI170_PDI_n_MASK) 5263 /*! @} */ 5264 5265 /*! @name GPDI169 - SIUL2 GPIO Pad Data Input Register */ 5266 /*! @{ */ 5267 5268 #define SIUL2_GPDI169_PDI_n_MASK (0x1U) 5269 #define SIUL2_GPDI169_PDI_n_SHIFT (0U) 5270 #define SIUL2_GPDI169_PDI_n_WIDTH (1U) 5271 #define SIUL2_GPDI169_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI169_PDI_n_SHIFT)) & SIUL2_GPDI169_PDI_n_MASK) 5272 /*! @} */ 5273 5274 /*! @name GPDI168 - SIUL2 GPIO Pad Data Input Register */ 5275 /*! @{ */ 5276 5277 #define SIUL2_GPDI168_PDI_n_MASK (0x1U) 5278 #define SIUL2_GPDI168_PDI_n_SHIFT (0U) 5279 #define SIUL2_GPDI168_PDI_n_WIDTH (1U) 5280 #define SIUL2_GPDI168_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI168_PDI_n_SHIFT)) & SIUL2_GPDI168_PDI_n_MASK) 5281 /*! @} */ 5282 5283 /*! @name GPDI175 - SIUL2 GPIO Pad Data Input Register */ 5284 /*! @{ */ 5285 5286 #define SIUL2_GPDI175_PDI_n_MASK (0x1U) 5287 #define SIUL2_GPDI175_PDI_n_SHIFT (0U) 5288 #define SIUL2_GPDI175_PDI_n_WIDTH (1U) 5289 #define SIUL2_GPDI175_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI175_PDI_n_SHIFT)) & SIUL2_GPDI175_PDI_n_MASK) 5290 /*! @} */ 5291 5292 /*! @name GPDI174 - SIUL2 GPIO Pad Data Input Register */ 5293 /*! @{ */ 5294 5295 #define SIUL2_GPDI174_PDI_n_MASK (0x1U) 5296 #define SIUL2_GPDI174_PDI_n_SHIFT (0U) 5297 #define SIUL2_GPDI174_PDI_n_WIDTH (1U) 5298 #define SIUL2_GPDI174_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI174_PDI_n_SHIFT)) & SIUL2_GPDI174_PDI_n_MASK) 5299 /*! @} */ 5300 5301 /*! @name GPDI173 - SIUL2 GPIO Pad Data Input Register */ 5302 /*! @{ */ 5303 5304 #define SIUL2_GPDI173_PDI_n_MASK (0x1U) 5305 #define SIUL2_GPDI173_PDI_n_SHIFT (0U) 5306 #define SIUL2_GPDI173_PDI_n_WIDTH (1U) 5307 #define SIUL2_GPDI173_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI173_PDI_n_SHIFT)) & SIUL2_GPDI173_PDI_n_MASK) 5308 /*! @} */ 5309 5310 /*! @name GPDI172 - SIUL2 GPIO Pad Data Input Register */ 5311 /*! @{ */ 5312 5313 #define SIUL2_GPDI172_PDI_n_MASK (0x1U) 5314 #define SIUL2_GPDI172_PDI_n_SHIFT (0U) 5315 #define SIUL2_GPDI172_PDI_n_WIDTH (1U) 5316 #define SIUL2_GPDI172_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI172_PDI_n_SHIFT)) & SIUL2_GPDI172_PDI_n_MASK) 5317 /*! @} */ 5318 5319 /*! @name GPDI179 - SIUL2 GPIO Pad Data Input Register */ 5320 /*! @{ */ 5321 5322 #define SIUL2_GPDI179_PDI_n_MASK (0x1U) 5323 #define SIUL2_GPDI179_PDI_n_SHIFT (0U) 5324 #define SIUL2_GPDI179_PDI_n_WIDTH (1U) 5325 #define SIUL2_GPDI179_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI179_PDI_n_SHIFT)) & SIUL2_GPDI179_PDI_n_MASK) 5326 /*! @} */ 5327 5328 /*! @name GPDI178 - SIUL2 GPIO Pad Data Input Register */ 5329 /*! @{ */ 5330 5331 #define SIUL2_GPDI178_PDI_n_MASK (0x1U) 5332 #define SIUL2_GPDI178_PDI_n_SHIFT (0U) 5333 #define SIUL2_GPDI178_PDI_n_WIDTH (1U) 5334 #define SIUL2_GPDI178_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI178_PDI_n_SHIFT)) & SIUL2_GPDI178_PDI_n_MASK) 5335 /*! @} */ 5336 5337 /*! @name GPDI177 - SIUL2 GPIO Pad Data Input Register */ 5338 /*! @{ */ 5339 5340 #define SIUL2_GPDI177_PDI_n_MASK (0x1U) 5341 #define SIUL2_GPDI177_PDI_n_SHIFT (0U) 5342 #define SIUL2_GPDI177_PDI_n_WIDTH (1U) 5343 #define SIUL2_GPDI177_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI177_PDI_n_SHIFT)) & SIUL2_GPDI177_PDI_n_MASK) 5344 /*! @} */ 5345 5346 /*! @name GPDI176 - SIUL2 GPIO Pad Data Input Register */ 5347 /*! @{ */ 5348 5349 #define SIUL2_GPDI176_PDI_n_MASK (0x1U) 5350 #define SIUL2_GPDI176_PDI_n_SHIFT (0U) 5351 #define SIUL2_GPDI176_PDI_n_WIDTH (1U) 5352 #define SIUL2_GPDI176_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI176_PDI_n_SHIFT)) & SIUL2_GPDI176_PDI_n_MASK) 5353 /*! @} */ 5354 5355 /*! @name GPDI183 - SIUL2 GPIO Pad Data Input Register */ 5356 /*! @{ */ 5357 5358 #define SIUL2_GPDI183_PDI_n_MASK (0x1U) 5359 #define SIUL2_GPDI183_PDI_n_SHIFT (0U) 5360 #define SIUL2_GPDI183_PDI_n_WIDTH (1U) 5361 #define SIUL2_GPDI183_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI183_PDI_n_SHIFT)) & SIUL2_GPDI183_PDI_n_MASK) 5362 /*! @} */ 5363 5364 /*! @name GPDI182 - SIUL2 GPIO Pad Data Input Register */ 5365 /*! @{ */ 5366 5367 #define SIUL2_GPDI182_PDI_n_MASK (0x1U) 5368 #define SIUL2_GPDI182_PDI_n_SHIFT (0U) 5369 #define SIUL2_GPDI182_PDI_n_WIDTH (1U) 5370 #define SIUL2_GPDI182_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI182_PDI_n_SHIFT)) & SIUL2_GPDI182_PDI_n_MASK) 5371 /*! @} */ 5372 5373 /*! @name GPDI181 - SIUL2 GPIO Pad Data Input Register */ 5374 /*! @{ */ 5375 5376 #define SIUL2_GPDI181_PDI_n_MASK (0x1U) 5377 #define SIUL2_GPDI181_PDI_n_SHIFT (0U) 5378 #define SIUL2_GPDI181_PDI_n_WIDTH (1U) 5379 #define SIUL2_GPDI181_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI181_PDI_n_SHIFT)) & SIUL2_GPDI181_PDI_n_MASK) 5380 /*! @} */ 5381 5382 /*! @name GPDI180 - SIUL2 GPIO Pad Data Input Register */ 5383 /*! @{ */ 5384 5385 #define SIUL2_GPDI180_PDI_n_MASK (0x1U) 5386 #define SIUL2_GPDI180_PDI_n_SHIFT (0U) 5387 #define SIUL2_GPDI180_PDI_n_WIDTH (1U) 5388 #define SIUL2_GPDI180_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI180_PDI_n_SHIFT)) & SIUL2_GPDI180_PDI_n_MASK) 5389 /*! @} */ 5390 5391 /*! @name GPDI187 - SIUL2 GPIO Pad Data Input Register */ 5392 /*! @{ */ 5393 5394 #define SIUL2_GPDI187_PDI_n_MASK (0x1U) 5395 #define SIUL2_GPDI187_PDI_n_SHIFT (0U) 5396 #define SIUL2_GPDI187_PDI_n_WIDTH (1U) 5397 #define SIUL2_GPDI187_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI187_PDI_n_SHIFT)) & SIUL2_GPDI187_PDI_n_MASK) 5398 /*! @} */ 5399 5400 /*! @name GPDI186 - SIUL2 GPIO Pad Data Input Register */ 5401 /*! @{ */ 5402 5403 #define SIUL2_GPDI186_PDI_n_MASK (0x1U) 5404 #define SIUL2_GPDI186_PDI_n_SHIFT (0U) 5405 #define SIUL2_GPDI186_PDI_n_WIDTH (1U) 5406 #define SIUL2_GPDI186_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI186_PDI_n_SHIFT)) & SIUL2_GPDI186_PDI_n_MASK) 5407 /*! @} */ 5408 5409 /*! @name GPDI185 - SIUL2 GPIO Pad Data Input Register */ 5410 /*! @{ */ 5411 5412 #define SIUL2_GPDI185_PDI_n_MASK (0x1U) 5413 #define SIUL2_GPDI185_PDI_n_SHIFT (0U) 5414 #define SIUL2_GPDI185_PDI_n_WIDTH (1U) 5415 #define SIUL2_GPDI185_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI185_PDI_n_SHIFT)) & SIUL2_GPDI185_PDI_n_MASK) 5416 /*! @} */ 5417 5418 /*! @name GPDI184 - SIUL2 GPIO Pad Data Input Register */ 5419 /*! @{ */ 5420 5421 #define SIUL2_GPDI184_PDI_n_MASK (0x1U) 5422 #define SIUL2_GPDI184_PDI_n_SHIFT (0U) 5423 #define SIUL2_GPDI184_PDI_n_WIDTH (1U) 5424 #define SIUL2_GPDI184_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI184_PDI_n_SHIFT)) & SIUL2_GPDI184_PDI_n_MASK) 5425 /*! @} */ 5426 5427 /*! @name GPDI191 - SIUL2 GPIO Pad Data Input Register */ 5428 /*! @{ */ 5429 5430 #define SIUL2_GPDI191_PDI_n_MASK (0x1U) 5431 #define SIUL2_GPDI191_PDI_n_SHIFT (0U) 5432 #define SIUL2_GPDI191_PDI_n_WIDTH (1U) 5433 #define SIUL2_GPDI191_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI191_PDI_n_SHIFT)) & SIUL2_GPDI191_PDI_n_MASK) 5434 /*! @} */ 5435 5436 /*! @name GPDI190 - SIUL2 GPIO Pad Data Input Register */ 5437 /*! @{ */ 5438 5439 #define SIUL2_GPDI190_PDI_n_MASK (0x1U) 5440 #define SIUL2_GPDI190_PDI_n_SHIFT (0U) 5441 #define SIUL2_GPDI190_PDI_n_WIDTH (1U) 5442 #define SIUL2_GPDI190_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI190_PDI_n_SHIFT)) & SIUL2_GPDI190_PDI_n_MASK) 5443 /*! @} */ 5444 5445 /*! @name GPDI189 - SIUL2 GPIO Pad Data Input Register */ 5446 /*! @{ */ 5447 5448 #define SIUL2_GPDI189_PDI_n_MASK (0x1U) 5449 #define SIUL2_GPDI189_PDI_n_SHIFT (0U) 5450 #define SIUL2_GPDI189_PDI_n_WIDTH (1U) 5451 #define SIUL2_GPDI189_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI189_PDI_n_SHIFT)) & SIUL2_GPDI189_PDI_n_MASK) 5452 /*! @} */ 5453 5454 /*! @name GPDI188 - SIUL2 GPIO Pad Data Input Register */ 5455 /*! @{ */ 5456 5457 #define SIUL2_GPDI188_PDI_n_MASK (0x1U) 5458 #define SIUL2_GPDI188_PDI_n_SHIFT (0U) 5459 #define SIUL2_GPDI188_PDI_n_WIDTH (1U) 5460 #define SIUL2_GPDI188_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI188_PDI_n_SHIFT)) & SIUL2_GPDI188_PDI_n_MASK) 5461 /*! @} */ 5462 5463 /*! @name GPDI195 - SIUL2 GPIO Pad Data Input Register */ 5464 /*! @{ */ 5465 5466 #define SIUL2_GPDI195_PDI_n_MASK (0x1U) 5467 #define SIUL2_GPDI195_PDI_n_SHIFT (0U) 5468 #define SIUL2_GPDI195_PDI_n_WIDTH (1U) 5469 #define SIUL2_GPDI195_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI195_PDI_n_SHIFT)) & SIUL2_GPDI195_PDI_n_MASK) 5470 /*! @} */ 5471 5472 /*! @name GPDI194 - SIUL2 GPIO Pad Data Input Register */ 5473 /*! @{ */ 5474 5475 #define SIUL2_GPDI194_PDI_n_MASK (0x1U) 5476 #define SIUL2_GPDI194_PDI_n_SHIFT (0U) 5477 #define SIUL2_GPDI194_PDI_n_WIDTH (1U) 5478 #define SIUL2_GPDI194_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI194_PDI_n_SHIFT)) & SIUL2_GPDI194_PDI_n_MASK) 5479 /*! @} */ 5480 5481 /*! @name GPDI193 - SIUL2 GPIO Pad Data Input Register */ 5482 /*! @{ */ 5483 5484 #define SIUL2_GPDI193_PDI_n_MASK (0x1U) 5485 #define SIUL2_GPDI193_PDI_n_SHIFT (0U) 5486 #define SIUL2_GPDI193_PDI_n_WIDTH (1U) 5487 #define SIUL2_GPDI193_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI193_PDI_n_SHIFT)) & SIUL2_GPDI193_PDI_n_MASK) 5488 /*! @} */ 5489 5490 /*! @name GPDI192 - SIUL2 GPIO Pad Data Input Register */ 5491 /*! @{ */ 5492 5493 #define SIUL2_GPDI192_PDI_n_MASK (0x1U) 5494 #define SIUL2_GPDI192_PDI_n_SHIFT (0U) 5495 #define SIUL2_GPDI192_PDI_n_WIDTH (1U) 5496 #define SIUL2_GPDI192_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI192_PDI_n_SHIFT)) & SIUL2_GPDI192_PDI_n_MASK) 5497 /*! @} */ 5498 5499 /*! @name GPDI199 - SIUL2 GPIO Pad Data Input Register */ 5500 /*! @{ */ 5501 5502 #define SIUL2_GPDI199_PDI_n_MASK (0x1U) 5503 #define SIUL2_GPDI199_PDI_n_SHIFT (0U) 5504 #define SIUL2_GPDI199_PDI_n_WIDTH (1U) 5505 #define SIUL2_GPDI199_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI199_PDI_n_SHIFT)) & SIUL2_GPDI199_PDI_n_MASK) 5506 /*! @} */ 5507 5508 /*! @name GPDI198 - SIUL2 GPIO Pad Data Input Register */ 5509 /*! @{ */ 5510 5511 #define SIUL2_GPDI198_PDI_n_MASK (0x1U) 5512 #define SIUL2_GPDI198_PDI_n_SHIFT (0U) 5513 #define SIUL2_GPDI198_PDI_n_WIDTH (1U) 5514 #define SIUL2_GPDI198_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI198_PDI_n_SHIFT)) & SIUL2_GPDI198_PDI_n_MASK) 5515 /*! @} */ 5516 5517 /*! @name GPDI197 - SIUL2 GPIO Pad Data Input Register */ 5518 /*! @{ */ 5519 5520 #define SIUL2_GPDI197_PDI_n_MASK (0x1U) 5521 #define SIUL2_GPDI197_PDI_n_SHIFT (0U) 5522 #define SIUL2_GPDI197_PDI_n_WIDTH (1U) 5523 #define SIUL2_GPDI197_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI197_PDI_n_SHIFT)) & SIUL2_GPDI197_PDI_n_MASK) 5524 /*! @} */ 5525 5526 /*! @name GPDI196 - SIUL2 GPIO Pad Data Input Register */ 5527 /*! @{ */ 5528 5529 #define SIUL2_GPDI196_PDI_n_MASK (0x1U) 5530 #define SIUL2_GPDI196_PDI_n_SHIFT (0U) 5531 #define SIUL2_GPDI196_PDI_n_WIDTH (1U) 5532 #define SIUL2_GPDI196_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI196_PDI_n_SHIFT)) & SIUL2_GPDI196_PDI_n_MASK) 5533 /*! @} */ 5534 5535 /*! @name GPDI203 - SIUL2 GPIO Pad Data Input Register */ 5536 /*! @{ */ 5537 5538 #define SIUL2_GPDI203_PDI_n_MASK (0x1U) 5539 #define SIUL2_GPDI203_PDI_n_SHIFT (0U) 5540 #define SIUL2_GPDI203_PDI_n_WIDTH (1U) 5541 #define SIUL2_GPDI203_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI203_PDI_n_SHIFT)) & SIUL2_GPDI203_PDI_n_MASK) 5542 /*! @} */ 5543 5544 /*! @name GPDI202 - SIUL2 GPIO Pad Data Input Register */ 5545 /*! @{ */ 5546 5547 #define SIUL2_GPDI202_PDI_n_MASK (0x1U) 5548 #define SIUL2_GPDI202_PDI_n_SHIFT (0U) 5549 #define SIUL2_GPDI202_PDI_n_WIDTH (1U) 5550 #define SIUL2_GPDI202_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI202_PDI_n_SHIFT)) & SIUL2_GPDI202_PDI_n_MASK) 5551 /*! @} */ 5552 5553 /*! @name GPDI201 - SIUL2 GPIO Pad Data Input Register */ 5554 /*! @{ */ 5555 5556 #define SIUL2_GPDI201_PDI_n_MASK (0x1U) 5557 #define SIUL2_GPDI201_PDI_n_SHIFT (0U) 5558 #define SIUL2_GPDI201_PDI_n_WIDTH (1U) 5559 #define SIUL2_GPDI201_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI201_PDI_n_SHIFT)) & SIUL2_GPDI201_PDI_n_MASK) 5560 /*! @} */ 5561 5562 /*! @name GPDI200 - SIUL2 GPIO Pad Data Input Register */ 5563 /*! @{ */ 5564 5565 #define SIUL2_GPDI200_PDI_n_MASK (0x1U) 5566 #define SIUL2_GPDI200_PDI_n_SHIFT (0U) 5567 #define SIUL2_GPDI200_PDI_n_WIDTH (1U) 5568 #define SIUL2_GPDI200_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI200_PDI_n_SHIFT)) & SIUL2_GPDI200_PDI_n_MASK) 5569 /*! @} */ 5570 5571 /*! @name GPDI207 - SIUL2 GPIO Pad Data Input Register */ 5572 /*! @{ */ 5573 5574 #define SIUL2_GPDI207_PDI_n_MASK (0x1U) 5575 #define SIUL2_GPDI207_PDI_n_SHIFT (0U) 5576 #define SIUL2_GPDI207_PDI_n_WIDTH (1U) 5577 #define SIUL2_GPDI207_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI207_PDI_n_SHIFT)) & SIUL2_GPDI207_PDI_n_MASK) 5578 /*! @} */ 5579 5580 /*! @name GPDI206 - SIUL2 GPIO Pad Data Input Register */ 5581 /*! @{ */ 5582 5583 #define SIUL2_GPDI206_PDI_n_MASK (0x1U) 5584 #define SIUL2_GPDI206_PDI_n_SHIFT (0U) 5585 #define SIUL2_GPDI206_PDI_n_WIDTH (1U) 5586 #define SIUL2_GPDI206_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI206_PDI_n_SHIFT)) & SIUL2_GPDI206_PDI_n_MASK) 5587 /*! @} */ 5588 5589 /*! @name GPDI205 - SIUL2 GPIO Pad Data Input Register */ 5590 /*! @{ */ 5591 5592 #define SIUL2_GPDI205_PDI_n_MASK (0x1U) 5593 #define SIUL2_GPDI205_PDI_n_SHIFT (0U) 5594 #define SIUL2_GPDI205_PDI_n_WIDTH (1U) 5595 #define SIUL2_GPDI205_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI205_PDI_n_SHIFT)) & SIUL2_GPDI205_PDI_n_MASK) 5596 /*! @} */ 5597 5598 /*! @name GPDI204 - SIUL2 GPIO Pad Data Input Register */ 5599 /*! @{ */ 5600 5601 #define SIUL2_GPDI204_PDI_n_MASK (0x1U) 5602 #define SIUL2_GPDI204_PDI_n_SHIFT (0U) 5603 #define SIUL2_GPDI204_PDI_n_WIDTH (1U) 5604 #define SIUL2_GPDI204_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI204_PDI_n_SHIFT)) & SIUL2_GPDI204_PDI_n_MASK) 5605 /*! @} */ 5606 5607 /*! @name GPDI211 - SIUL2 GPIO Pad Data Input Register */ 5608 /*! @{ */ 5609 5610 #define SIUL2_GPDI211_PDI_n_MASK (0x1U) 5611 #define SIUL2_GPDI211_PDI_n_SHIFT (0U) 5612 #define SIUL2_GPDI211_PDI_n_WIDTH (1U) 5613 #define SIUL2_GPDI211_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI211_PDI_n_SHIFT)) & SIUL2_GPDI211_PDI_n_MASK) 5614 /*! @} */ 5615 5616 /*! @name GPDI210 - SIUL2 GPIO Pad Data Input Register */ 5617 /*! @{ */ 5618 5619 #define SIUL2_GPDI210_PDI_n_MASK (0x1U) 5620 #define SIUL2_GPDI210_PDI_n_SHIFT (0U) 5621 #define SIUL2_GPDI210_PDI_n_WIDTH (1U) 5622 #define SIUL2_GPDI210_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI210_PDI_n_SHIFT)) & SIUL2_GPDI210_PDI_n_MASK) 5623 /*! @} */ 5624 5625 /*! @name GPDI209 - SIUL2 GPIO Pad Data Input Register */ 5626 /*! @{ */ 5627 5628 #define SIUL2_GPDI209_PDI_n_MASK (0x1U) 5629 #define SIUL2_GPDI209_PDI_n_SHIFT (0U) 5630 #define SIUL2_GPDI209_PDI_n_WIDTH (1U) 5631 #define SIUL2_GPDI209_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI209_PDI_n_SHIFT)) & SIUL2_GPDI209_PDI_n_MASK) 5632 /*! @} */ 5633 5634 /*! @name GPDI208 - SIUL2 GPIO Pad Data Input Register */ 5635 /*! @{ */ 5636 5637 #define SIUL2_GPDI208_PDI_n_MASK (0x1U) 5638 #define SIUL2_GPDI208_PDI_n_SHIFT (0U) 5639 #define SIUL2_GPDI208_PDI_n_WIDTH (1U) 5640 #define SIUL2_GPDI208_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI208_PDI_n_SHIFT)) & SIUL2_GPDI208_PDI_n_MASK) 5641 /*! @} */ 5642 5643 /*! @name GPDI215 - SIUL2 GPIO Pad Data Input Register */ 5644 /*! @{ */ 5645 5646 #define SIUL2_GPDI215_PDI_n_MASK (0x1U) 5647 #define SIUL2_GPDI215_PDI_n_SHIFT (0U) 5648 #define SIUL2_GPDI215_PDI_n_WIDTH (1U) 5649 #define SIUL2_GPDI215_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI215_PDI_n_SHIFT)) & SIUL2_GPDI215_PDI_n_MASK) 5650 /*! @} */ 5651 5652 /*! @name GPDI214 - SIUL2 GPIO Pad Data Input Register */ 5653 /*! @{ */ 5654 5655 #define SIUL2_GPDI214_PDI_n_MASK (0x1U) 5656 #define SIUL2_GPDI214_PDI_n_SHIFT (0U) 5657 #define SIUL2_GPDI214_PDI_n_WIDTH (1U) 5658 #define SIUL2_GPDI214_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI214_PDI_n_SHIFT)) & SIUL2_GPDI214_PDI_n_MASK) 5659 /*! @} */ 5660 5661 /*! @name GPDI213 - SIUL2 GPIO Pad Data Input Register */ 5662 /*! @{ */ 5663 5664 #define SIUL2_GPDI213_PDI_n_MASK (0x1U) 5665 #define SIUL2_GPDI213_PDI_n_SHIFT (0U) 5666 #define SIUL2_GPDI213_PDI_n_WIDTH (1U) 5667 #define SIUL2_GPDI213_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI213_PDI_n_SHIFT)) & SIUL2_GPDI213_PDI_n_MASK) 5668 /*! @} */ 5669 5670 /*! @name GPDI212 - SIUL2 GPIO Pad Data Input Register */ 5671 /*! @{ */ 5672 5673 #define SIUL2_GPDI212_PDI_n_MASK (0x1U) 5674 #define SIUL2_GPDI212_PDI_n_SHIFT (0U) 5675 #define SIUL2_GPDI212_PDI_n_WIDTH (1U) 5676 #define SIUL2_GPDI212_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI212_PDI_n_SHIFT)) & SIUL2_GPDI212_PDI_n_MASK) 5677 /*! @} */ 5678 5679 /*! @name GPDI219 - SIUL2 GPIO Pad Data Input Register */ 5680 /*! @{ */ 5681 5682 #define SIUL2_GPDI219_PDI_n_MASK (0x1U) 5683 #define SIUL2_GPDI219_PDI_n_SHIFT (0U) 5684 #define SIUL2_GPDI219_PDI_n_WIDTH (1U) 5685 #define SIUL2_GPDI219_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI219_PDI_n_SHIFT)) & SIUL2_GPDI219_PDI_n_MASK) 5686 /*! @} */ 5687 5688 /*! @name GPDI218 - SIUL2 GPIO Pad Data Input Register */ 5689 /*! @{ */ 5690 5691 #define SIUL2_GPDI218_PDI_n_MASK (0x1U) 5692 #define SIUL2_GPDI218_PDI_n_SHIFT (0U) 5693 #define SIUL2_GPDI218_PDI_n_WIDTH (1U) 5694 #define SIUL2_GPDI218_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI218_PDI_n_SHIFT)) & SIUL2_GPDI218_PDI_n_MASK) 5695 /*! @} */ 5696 5697 /*! @name GPDI217 - SIUL2 GPIO Pad Data Input Register */ 5698 /*! @{ */ 5699 5700 #define SIUL2_GPDI217_PDI_n_MASK (0x1U) 5701 #define SIUL2_GPDI217_PDI_n_SHIFT (0U) 5702 #define SIUL2_GPDI217_PDI_n_WIDTH (1U) 5703 #define SIUL2_GPDI217_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI217_PDI_n_SHIFT)) & SIUL2_GPDI217_PDI_n_MASK) 5704 /*! @} */ 5705 5706 /*! @name GPDI216 - SIUL2 GPIO Pad Data Input Register */ 5707 /*! @{ */ 5708 5709 #define SIUL2_GPDI216_PDI_n_MASK (0x1U) 5710 #define SIUL2_GPDI216_PDI_n_SHIFT (0U) 5711 #define SIUL2_GPDI216_PDI_n_WIDTH (1U) 5712 #define SIUL2_GPDI216_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI216_PDI_n_SHIFT)) & SIUL2_GPDI216_PDI_n_MASK) 5713 /*! @} */ 5714 5715 /*! @name PGPDO1 - SIUL2 Parallel GPIO Pad Data Out Register */ 5716 /*! @{ */ 5717 5718 #define SIUL2_PGPDO1_PPDO0_MASK (0x1U) 5719 #define SIUL2_PGPDO1_PPDO0_SHIFT (0U) 5720 #define SIUL2_PGPDO1_PPDO0_WIDTH (1U) 5721 #define SIUL2_PGPDO1_PPDO0(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO1_PPDO0_SHIFT)) & SIUL2_PGPDO1_PPDO0_MASK) 5722 5723 #define SIUL2_PGPDO1_PPDO1_MASK (0x2U) 5724 #define SIUL2_PGPDO1_PPDO1_SHIFT (1U) 5725 #define SIUL2_PGPDO1_PPDO1_WIDTH (1U) 5726 #define SIUL2_PGPDO1_PPDO1(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO1_PPDO1_SHIFT)) & SIUL2_PGPDO1_PPDO1_MASK) 5727 5728 #define SIUL2_PGPDO1_PPDO2_MASK (0x4U) 5729 #define SIUL2_PGPDO1_PPDO2_SHIFT (2U) 5730 #define SIUL2_PGPDO1_PPDO2_WIDTH (1U) 5731 #define SIUL2_PGPDO1_PPDO2(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO1_PPDO2_SHIFT)) & SIUL2_PGPDO1_PPDO2_MASK) 5732 5733 #define SIUL2_PGPDO1_PPDO3_MASK (0x8U) 5734 #define SIUL2_PGPDO1_PPDO3_SHIFT (3U) 5735 #define SIUL2_PGPDO1_PPDO3_WIDTH (1U) 5736 #define SIUL2_PGPDO1_PPDO3(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO1_PPDO3_SHIFT)) & SIUL2_PGPDO1_PPDO3_MASK) 5737 5738 #define SIUL2_PGPDO1_PPDO4_MASK (0x10U) 5739 #define SIUL2_PGPDO1_PPDO4_SHIFT (4U) 5740 #define SIUL2_PGPDO1_PPDO4_WIDTH (1U) 5741 #define SIUL2_PGPDO1_PPDO4(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO1_PPDO4_SHIFT)) & SIUL2_PGPDO1_PPDO4_MASK) 5742 5743 #define SIUL2_PGPDO1_PPDO5_MASK (0x20U) 5744 #define SIUL2_PGPDO1_PPDO5_SHIFT (5U) 5745 #define SIUL2_PGPDO1_PPDO5_WIDTH (1U) 5746 #define SIUL2_PGPDO1_PPDO5(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO1_PPDO5_SHIFT)) & SIUL2_PGPDO1_PPDO5_MASK) 5747 5748 #define SIUL2_PGPDO1_PPDO6_MASK (0x40U) 5749 #define SIUL2_PGPDO1_PPDO6_SHIFT (6U) 5750 #define SIUL2_PGPDO1_PPDO6_WIDTH (1U) 5751 #define SIUL2_PGPDO1_PPDO6(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO1_PPDO6_SHIFT)) & SIUL2_PGPDO1_PPDO6_MASK) 5752 5753 #define SIUL2_PGPDO1_PPDO7_MASK (0x80U) 5754 #define SIUL2_PGPDO1_PPDO7_SHIFT (7U) 5755 #define SIUL2_PGPDO1_PPDO7_WIDTH (1U) 5756 #define SIUL2_PGPDO1_PPDO7(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO1_PPDO7_SHIFT)) & SIUL2_PGPDO1_PPDO7_MASK) 5757 5758 #define SIUL2_PGPDO1_PPDO8_MASK (0x100U) 5759 #define SIUL2_PGPDO1_PPDO8_SHIFT (8U) 5760 #define SIUL2_PGPDO1_PPDO8_WIDTH (1U) 5761 #define SIUL2_PGPDO1_PPDO8(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO1_PPDO8_SHIFT)) & SIUL2_PGPDO1_PPDO8_MASK) 5762 5763 #define SIUL2_PGPDO1_PPDO9_MASK (0x200U) 5764 #define SIUL2_PGPDO1_PPDO9_SHIFT (9U) 5765 #define SIUL2_PGPDO1_PPDO9_WIDTH (1U) 5766 #define SIUL2_PGPDO1_PPDO9(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO1_PPDO9_SHIFT)) & SIUL2_PGPDO1_PPDO9_MASK) 5767 5768 #define SIUL2_PGPDO1_PPDO10_MASK (0x400U) 5769 #define SIUL2_PGPDO1_PPDO10_SHIFT (10U) 5770 #define SIUL2_PGPDO1_PPDO10_WIDTH (1U) 5771 #define SIUL2_PGPDO1_PPDO10(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO1_PPDO10_SHIFT)) & SIUL2_PGPDO1_PPDO10_MASK) 5772 5773 #define SIUL2_PGPDO1_PPDO11_MASK (0x800U) 5774 #define SIUL2_PGPDO1_PPDO11_SHIFT (11U) 5775 #define SIUL2_PGPDO1_PPDO11_WIDTH (1U) 5776 #define SIUL2_PGPDO1_PPDO11(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO1_PPDO11_SHIFT)) & SIUL2_PGPDO1_PPDO11_MASK) 5777 5778 #define SIUL2_PGPDO1_PPDO12_MASK (0x1000U) 5779 #define SIUL2_PGPDO1_PPDO12_SHIFT (12U) 5780 #define SIUL2_PGPDO1_PPDO12_WIDTH (1U) 5781 #define SIUL2_PGPDO1_PPDO12(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO1_PPDO12_SHIFT)) & SIUL2_PGPDO1_PPDO12_MASK) 5782 5783 #define SIUL2_PGPDO1_PPDO13_MASK (0x2000U) 5784 #define SIUL2_PGPDO1_PPDO13_SHIFT (13U) 5785 #define SIUL2_PGPDO1_PPDO13_WIDTH (1U) 5786 #define SIUL2_PGPDO1_PPDO13(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO1_PPDO13_SHIFT)) & SIUL2_PGPDO1_PPDO13_MASK) 5787 5788 #define SIUL2_PGPDO1_PPDO14_MASK (0x4000U) 5789 #define SIUL2_PGPDO1_PPDO14_SHIFT (14U) 5790 #define SIUL2_PGPDO1_PPDO14_WIDTH (1U) 5791 #define SIUL2_PGPDO1_PPDO14(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO1_PPDO14_SHIFT)) & SIUL2_PGPDO1_PPDO14_MASK) 5792 5793 #define SIUL2_PGPDO1_PPDO15_MASK (0x8000U) 5794 #define SIUL2_PGPDO1_PPDO15_SHIFT (15U) 5795 #define SIUL2_PGPDO1_PPDO15_WIDTH (1U) 5796 #define SIUL2_PGPDO1_PPDO15(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO1_PPDO15_SHIFT)) & SIUL2_PGPDO1_PPDO15_MASK) 5797 /*! @} */ 5798 5799 /*! @name PGPDO0 - SIUL2 Parallel GPIO Pad Data Out Register */ 5800 /*! @{ */ 5801 5802 #define SIUL2_PGPDO0_PPDO0_MASK (0x1U) 5803 #define SIUL2_PGPDO0_PPDO0_SHIFT (0U) 5804 #define SIUL2_PGPDO0_PPDO0_WIDTH (1U) 5805 #define SIUL2_PGPDO0_PPDO0(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO0_PPDO0_SHIFT)) & SIUL2_PGPDO0_PPDO0_MASK) 5806 5807 #define SIUL2_PGPDO0_PPDO1_MASK (0x2U) 5808 #define SIUL2_PGPDO0_PPDO1_SHIFT (1U) 5809 #define SIUL2_PGPDO0_PPDO1_WIDTH (1U) 5810 #define SIUL2_PGPDO0_PPDO1(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO0_PPDO1_SHIFT)) & SIUL2_PGPDO0_PPDO1_MASK) 5811 5812 #define SIUL2_PGPDO0_PPDO2_MASK (0x4U) 5813 #define SIUL2_PGPDO0_PPDO2_SHIFT (2U) 5814 #define SIUL2_PGPDO0_PPDO2_WIDTH (1U) 5815 #define SIUL2_PGPDO0_PPDO2(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO0_PPDO2_SHIFT)) & SIUL2_PGPDO0_PPDO2_MASK) 5816 5817 #define SIUL2_PGPDO0_PPDO3_MASK (0x8U) 5818 #define SIUL2_PGPDO0_PPDO3_SHIFT (3U) 5819 #define SIUL2_PGPDO0_PPDO3_WIDTH (1U) 5820 #define SIUL2_PGPDO0_PPDO3(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO0_PPDO3_SHIFT)) & SIUL2_PGPDO0_PPDO3_MASK) 5821 5822 #define SIUL2_PGPDO0_PPDO4_MASK (0x10U) 5823 #define SIUL2_PGPDO0_PPDO4_SHIFT (4U) 5824 #define SIUL2_PGPDO0_PPDO4_WIDTH (1U) 5825 #define SIUL2_PGPDO0_PPDO4(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO0_PPDO4_SHIFT)) & SIUL2_PGPDO0_PPDO4_MASK) 5826 5827 #define SIUL2_PGPDO0_PPDO5_MASK (0x20U) 5828 #define SIUL2_PGPDO0_PPDO5_SHIFT (5U) 5829 #define SIUL2_PGPDO0_PPDO5_WIDTH (1U) 5830 #define SIUL2_PGPDO0_PPDO5(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO0_PPDO5_SHIFT)) & SIUL2_PGPDO0_PPDO5_MASK) 5831 5832 #define SIUL2_PGPDO0_PPDO6_MASK (0x40U) 5833 #define SIUL2_PGPDO0_PPDO6_SHIFT (6U) 5834 #define SIUL2_PGPDO0_PPDO6_WIDTH (1U) 5835 #define SIUL2_PGPDO0_PPDO6(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO0_PPDO6_SHIFT)) & SIUL2_PGPDO0_PPDO6_MASK) 5836 5837 #define SIUL2_PGPDO0_PPDO7_MASK (0x80U) 5838 #define SIUL2_PGPDO0_PPDO7_SHIFT (7U) 5839 #define SIUL2_PGPDO0_PPDO7_WIDTH (1U) 5840 #define SIUL2_PGPDO0_PPDO7(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO0_PPDO7_SHIFT)) & SIUL2_PGPDO0_PPDO7_MASK) 5841 5842 #define SIUL2_PGPDO0_PPDO8_MASK (0x100U) 5843 #define SIUL2_PGPDO0_PPDO8_SHIFT (8U) 5844 #define SIUL2_PGPDO0_PPDO8_WIDTH (1U) 5845 #define SIUL2_PGPDO0_PPDO8(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO0_PPDO8_SHIFT)) & SIUL2_PGPDO0_PPDO8_MASK) 5846 5847 #define SIUL2_PGPDO0_PPDO9_MASK (0x200U) 5848 #define SIUL2_PGPDO0_PPDO9_SHIFT (9U) 5849 #define SIUL2_PGPDO0_PPDO9_WIDTH (1U) 5850 #define SIUL2_PGPDO0_PPDO9(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO0_PPDO9_SHIFT)) & SIUL2_PGPDO0_PPDO9_MASK) 5851 5852 #define SIUL2_PGPDO0_PPDO10_MASK (0x400U) 5853 #define SIUL2_PGPDO0_PPDO10_SHIFT (10U) 5854 #define SIUL2_PGPDO0_PPDO10_WIDTH (1U) 5855 #define SIUL2_PGPDO0_PPDO10(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO0_PPDO10_SHIFT)) & SIUL2_PGPDO0_PPDO10_MASK) 5856 5857 #define SIUL2_PGPDO0_PPDO11_MASK (0x800U) 5858 #define SIUL2_PGPDO0_PPDO11_SHIFT (11U) 5859 #define SIUL2_PGPDO0_PPDO11_WIDTH (1U) 5860 #define SIUL2_PGPDO0_PPDO11(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO0_PPDO11_SHIFT)) & SIUL2_PGPDO0_PPDO11_MASK) 5861 5862 #define SIUL2_PGPDO0_PPDO12_MASK (0x1000U) 5863 #define SIUL2_PGPDO0_PPDO12_SHIFT (12U) 5864 #define SIUL2_PGPDO0_PPDO12_WIDTH (1U) 5865 #define SIUL2_PGPDO0_PPDO12(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO0_PPDO12_SHIFT)) & SIUL2_PGPDO0_PPDO12_MASK) 5866 5867 #define SIUL2_PGPDO0_PPDO13_MASK (0x2000U) 5868 #define SIUL2_PGPDO0_PPDO13_SHIFT (13U) 5869 #define SIUL2_PGPDO0_PPDO13_WIDTH (1U) 5870 #define SIUL2_PGPDO0_PPDO13(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO0_PPDO13_SHIFT)) & SIUL2_PGPDO0_PPDO13_MASK) 5871 5872 #define SIUL2_PGPDO0_PPDO14_MASK (0x4000U) 5873 #define SIUL2_PGPDO0_PPDO14_SHIFT (14U) 5874 #define SIUL2_PGPDO0_PPDO14_WIDTH (1U) 5875 #define SIUL2_PGPDO0_PPDO14(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO0_PPDO14_SHIFT)) & SIUL2_PGPDO0_PPDO14_MASK) 5876 5877 #define SIUL2_PGPDO0_PPDO15_MASK (0x8000U) 5878 #define SIUL2_PGPDO0_PPDO15_SHIFT (15U) 5879 #define SIUL2_PGPDO0_PPDO15_WIDTH (1U) 5880 #define SIUL2_PGPDO0_PPDO15(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO0_PPDO15_SHIFT)) & SIUL2_PGPDO0_PPDO15_MASK) 5881 /*! @} */ 5882 5883 /*! @name PGPDO3 - SIUL2 Parallel GPIO Pad Data Out Register */ 5884 /*! @{ */ 5885 5886 #define SIUL2_PGPDO3_PPDO0_MASK (0x1U) 5887 #define SIUL2_PGPDO3_PPDO0_SHIFT (0U) 5888 #define SIUL2_PGPDO3_PPDO0_WIDTH (1U) 5889 #define SIUL2_PGPDO3_PPDO0(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO3_PPDO0_SHIFT)) & SIUL2_PGPDO3_PPDO0_MASK) 5890 5891 #define SIUL2_PGPDO3_PPDO1_MASK (0x2U) 5892 #define SIUL2_PGPDO3_PPDO1_SHIFT (1U) 5893 #define SIUL2_PGPDO3_PPDO1_WIDTH (1U) 5894 #define SIUL2_PGPDO3_PPDO1(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO3_PPDO1_SHIFT)) & SIUL2_PGPDO3_PPDO1_MASK) 5895 5896 #define SIUL2_PGPDO3_PPDO2_MASK (0x4U) 5897 #define SIUL2_PGPDO3_PPDO2_SHIFT (2U) 5898 #define SIUL2_PGPDO3_PPDO2_WIDTH (1U) 5899 #define SIUL2_PGPDO3_PPDO2(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO3_PPDO2_SHIFT)) & SIUL2_PGPDO3_PPDO2_MASK) 5900 5901 #define SIUL2_PGPDO3_PPDO3_MASK (0x8U) 5902 #define SIUL2_PGPDO3_PPDO3_SHIFT (3U) 5903 #define SIUL2_PGPDO3_PPDO3_WIDTH (1U) 5904 #define SIUL2_PGPDO3_PPDO3(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO3_PPDO3_SHIFT)) & SIUL2_PGPDO3_PPDO3_MASK) 5905 5906 #define SIUL2_PGPDO3_PPDO4_MASK (0x10U) 5907 #define SIUL2_PGPDO3_PPDO4_SHIFT (4U) 5908 #define SIUL2_PGPDO3_PPDO4_WIDTH (1U) 5909 #define SIUL2_PGPDO3_PPDO4(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO3_PPDO4_SHIFT)) & SIUL2_PGPDO3_PPDO4_MASK) 5910 5911 #define SIUL2_PGPDO3_PPDO5_MASK (0x20U) 5912 #define SIUL2_PGPDO3_PPDO5_SHIFT (5U) 5913 #define SIUL2_PGPDO3_PPDO5_WIDTH (1U) 5914 #define SIUL2_PGPDO3_PPDO5(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO3_PPDO5_SHIFT)) & SIUL2_PGPDO3_PPDO5_MASK) 5915 5916 #define SIUL2_PGPDO3_PPDO6_MASK (0x40U) 5917 #define SIUL2_PGPDO3_PPDO6_SHIFT (6U) 5918 #define SIUL2_PGPDO3_PPDO6_WIDTH (1U) 5919 #define SIUL2_PGPDO3_PPDO6(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO3_PPDO6_SHIFT)) & SIUL2_PGPDO3_PPDO6_MASK) 5920 5921 #define SIUL2_PGPDO3_PPDO7_MASK (0x80U) 5922 #define SIUL2_PGPDO3_PPDO7_SHIFT (7U) 5923 #define SIUL2_PGPDO3_PPDO7_WIDTH (1U) 5924 #define SIUL2_PGPDO3_PPDO7(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO3_PPDO7_SHIFT)) & SIUL2_PGPDO3_PPDO7_MASK) 5925 5926 #define SIUL2_PGPDO3_PPDO8_MASK (0x100U) 5927 #define SIUL2_PGPDO3_PPDO8_SHIFT (8U) 5928 #define SIUL2_PGPDO3_PPDO8_WIDTH (1U) 5929 #define SIUL2_PGPDO3_PPDO8(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO3_PPDO8_SHIFT)) & SIUL2_PGPDO3_PPDO8_MASK) 5930 5931 #define SIUL2_PGPDO3_PPDO9_MASK (0x200U) 5932 #define SIUL2_PGPDO3_PPDO9_SHIFT (9U) 5933 #define SIUL2_PGPDO3_PPDO9_WIDTH (1U) 5934 #define SIUL2_PGPDO3_PPDO9(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO3_PPDO9_SHIFT)) & SIUL2_PGPDO3_PPDO9_MASK) 5935 5936 #define SIUL2_PGPDO3_PPDO10_MASK (0x400U) 5937 #define SIUL2_PGPDO3_PPDO10_SHIFT (10U) 5938 #define SIUL2_PGPDO3_PPDO10_WIDTH (1U) 5939 #define SIUL2_PGPDO3_PPDO10(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO3_PPDO10_SHIFT)) & SIUL2_PGPDO3_PPDO10_MASK) 5940 5941 #define SIUL2_PGPDO3_PPDO11_MASK (0x800U) 5942 #define SIUL2_PGPDO3_PPDO11_SHIFT (11U) 5943 #define SIUL2_PGPDO3_PPDO11_WIDTH (1U) 5944 #define SIUL2_PGPDO3_PPDO11(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO3_PPDO11_SHIFT)) & SIUL2_PGPDO3_PPDO11_MASK) 5945 5946 #define SIUL2_PGPDO3_PPDO12_MASK (0x1000U) 5947 #define SIUL2_PGPDO3_PPDO12_SHIFT (12U) 5948 #define SIUL2_PGPDO3_PPDO12_WIDTH (1U) 5949 #define SIUL2_PGPDO3_PPDO12(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO3_PPDO12_SHIFT)) & SIUL2_PGPDO3_PPDO12_MASK) 5950 5951 #define SIUL2_PGPDO3_PPDO13_MASK (0x2000U) 5952 #define SIUL2_PGPDO3_PPDO13_SHIFT (13U) 5953 #define SIUL2_PGPDO3_PPDO13_WIDTH (1U) 5954 #define SIUL2_PGPDO3_PPDO13(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO3_PPDO13_SHIFT)) & SIUL2_PGPDO3_PPDO13_MASK) 5955 5956 #define SIUL2_PGPDO3_PPDO14_MASK (0x4000U) 5957 #define SIUL2_PGPDO3_PPDO14_SHIFT (14U) 5958 #define SIUL2_PGPDO3_PPDO14_WIDTH (1U) 5959 #define SIUL2_PGPDO3_PPDO14(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO3_PPDO14_SHIFT)) & SIUL2_PGPDO3_PPDO14_MASK) 5960 5961 #define SIUL2_PGPDO3_PPDO15_MASK (0x8000U) 5962 #define SIUL2_PGPDO3_PPDO15_SHIFT (15U) 5963 #define SIUL2_PGPDO3_PPDO15_WIDTH (1U) 5964 #define SIUL2_PGPDO3_PPDO15(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO3_PPDO15_SHIFT)) & SIUL2_PGPDO3_PPDO15_MASK) 5965 /*! @} */ 5966 5967 /*! @name PGPDO2 - SIUL2 Parallel GPIO Pad Data Out Register */ 5968 /*! @{ */ 5969 5970 #define SIUL2_PGPDO2_PPDO0_MASK (0x1U) 5971 #define SIUL2_PGPDO2_PPDO0_SHIFT (0U) 5972 #define SIUL2_PGPDO2_PPDO0_WIDTH (1U) 5973 #define SIUL2_PGPDO2_PPDO0(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO2_PPDO0_SHIFT)) & SIUL2_PGPDO2_PPDO0_MASK) 5974 5975 #define SIUL2_PGPDO2_PPDO1_MASK (0x2U) 5976 #define SIUL2_PGPDO2_PPDO1_SHIFT (1U) 5977 #define SIUL2_PGPDO2_PPDO1_WIDTH (1U) 5978 #define SIUL2_PGPDO2_PPDO1(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO2_PPDO1_SHIFT)) & SIUL2_PGPDO2_PPDO1_MASK) 5979 5980 #define SIUL2_PGPDO2_PPDO2_MASK (0x4U) 5981 #define SIUL2_PGPDO2_PPDO2_SHIFT (2U) 5982 #define SIUL2_PGPDO2_PPDO2_WIDTH (1U) 5983 #define SIUL2_PGPDO2_PPDO2(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO2_PPDO2_SHIFT)) & SIUL2_PGPDO2_PPDO2_MASK) 5984 5985 #define SIUL2_PGPDO2_PPDO3_MASK (0x8U) 5986 #define SIUL2_PGPDO2_PPDO3_SHIFT (3U) 5987 #define SIUL2_PGPDO2_PPDO3_WIDTH (1U) 5988 #define SIUL2_PGPDO2_PPDO3(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO2_PPDO3_SHIFT)) & SIUL2_PGPDO2_PPDO3_MASK) 5989 5990 #define SIUL2_PGPDO2_PPDO4_MASK (0x10U) 5991 #define SIUL2_PGPDO2_PPDO4_SHIFT (4U) 5992 #define SIUL2_PGPDO2_PPDO4_WIDTH (1U) 5993 #define SIUL2_PGPDO2_PPDO4(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO2_PPDO4_SHIFT)) & SIUL2_PGPDO2_PPDO4_MASK) 5994 5995 #define SIUL2_PGPDO2_PPDO5_MASK (0x20U) 5996 #define SIUL2_PGPDO2_PPDO5_SHIFT (5U) 5997 #define SIUL2_PGPDO2_PPDO5_WIDTH (1U) 5998 #define SIUL2_PGPDO2_PPDO5(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO2_PPDO5_SHIFT)) & SIUL2_PGPDO2_PPDO5_MASK) 5999 6000 #define SIUL2_PGPDO2_PPDO6_MASK (0x40U) 6001 #define SIUL2_PGPDO2_PPDO6_SHIFT (6U) 6002 #define SIUL2_PGPDO2_PPDO6_WIDTH (1U) 6003 #define SIUL2_PGPDO2_PPDO6(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO2_PPDO6_SHIFT)) & SIUL2_PGPDO2_PPDO6_MASK) 6004 6005 #define SIUL2_PGPDO2_PPDO7_MASK (0x80U) 6006 #define SIUL2_PGPDO2_PPDO7_SHIFT (7U) 6007 #define SIUL2_PGPDO2_PPDO7_WIDTH (1U) 6008 #define SIUL2_PGPDO2_PPDO7(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO2_PPDO7_SHIFT)) & SIUL2_PGPDO2_PPDO7_MASK) 6009 6010 #define SIUL2_PGPDO2_PPDO10_MASK (0x400U) 6011 #define SIUL2_PGPDO2_PPDO10_SHIFT (10U) 6012 #define SIUL2_PGPDO2_PPDO10_WIDTH (1U) 6013 #define SIUL2_PGPDO2_PPDO10(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO2_PPDO10_SHIFT)) & SIUL2_PGPDO2_PPDO10_MASK) 6014 6015 #define SIUL2_PGPDO2_PPDO11_MASK (0x800U) 6016 #define SIUL2_PGPDO2_PPDO11_SHIFT (11U) 6017 #define SIUL2_PGPDO2_PPDO11_WIDTH (1U) 6018 #define SIUL2_PGPDO2_PPDO11(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO2_PPDO11_SHIFT)) & SIUL2_PGPDO2_PPDO11_MASK) 6019 6020 #define SIUL2_PGPDO2_PPDO12_MASK (0x1000U) 6021 #define SIUL2_PGPDO2_PPDO12_SHIFT (12U) 6022 #define SIUL2_PGPDO2_PPDO12_WIDTH (1U) 6023 #define SIUL2_PGPDO2_PPDO12(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO2_PPDO12_SHIFT)) & SIUL2_PGPDO2_PPDO12_MASK) 6024 6025 #define SIUL2_PGPDO2_PPDO13_MASK (0x2000U) 6026 #define SIUL2_PGPDO2_PPDO13_SHIFT (13U) 6027 #define SIUL2_PGPDO2_PPDO13_WIDTH (1U) 6028 #define SIUL2_PGPDO2_PPDO13(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO2_PPDO13_SHIFT)) & SIUL2_PGPDO2_PPDO13_MASK) 6029 6030 #define SIUL2_PGPDO2_PPDO14_MASK (0x4000U) 6031 #define SIUL2_PGPDO2_PPDO14_SHIFT (14U) 6032 #define SIUL2_PGPDO2_PPDO14_WIDTH (1U) 6033 #define SIUL2_PGPDO2_PPDO14(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO2_PPDO14_SHIFT)) & SIUL2_PGPDO2_PPDO14_MASK) 6034 6035 #define SIUL2_PGPDO2_PPDO15_MASK (0x8000U) 6036 #define SIUL2_PGPDO2_PPDO15_SHIFT (15U) 6037 #define SIUL2_PGPDO2_PPDO15_WIDTH (1U) 6038 #define SIUL2_PGPDO2_PPDO15(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO2_PPDO15_SHIFT)) & SIUL2_PGPDO2_PPDO15_MASK) 6039 /*! @} */ 6040 6041 /*! @name PGPDO5 - SIUL2 Parallel GPIO Pad Data Out Register */ 6042 /*! @{ */ 6043 6044 #define SIUL2_PGPDO5_PPDO0_MASK (0x1U) 6045 #define SIUL2_PGPDO5_PPDO0_SHIFT (0U) 6046 #define SIUL2_PGPDO5_PPDO0_WIDTH (1U) 6047 #define SIUL2_PGPDO5_PPDO0(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO5_PPDO0_SHIFT)) & SIUL2_PGPDO5_PPDO0_MASK) 6048 6049 #define SIUL2_PGPDO5_PPDO1_MASK (0x2U) 6050 #define SIUL2_PGPDO5_PPDO1_SHIFT (1U) 6051 #define SIUL2_PGPDO5_PPDO1_WIDTH (1U) 6052 #define SIUL2_PGPDO5_PPDO1(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO5_PPDO1_SHIFT)) & SIUL2_PGPDO5_PPDO1_MASK) 6053 6054 #define SIUL2_PGPDO5_PPDO2_MASK (0x4U) 6055 #define SIUL2_PGPDO5_PPDO2_SHIFT (2U) 6056 #define SIUL2_PGPDO5_PPDO2_WIDTH (1U) 6057 #define SIUL2_PGPDO5_PPDO2(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO5_PPDO2_SHIFT)) & SIUL2_PGPDO5_PPDO2_MASK) 6058 6059 #define SIUL2_PGPDO5_PPDO3_MASK (0x8U) 6060 #define SIUL2_PGPDO5_PPDO3_SHIFT (3U) 6061 #define SIUL2_PGPDO5_PPDO3_WIDTH (1U) 6062 #define SIUL2_PGPDO5_PPDO3(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO5_PPDO3_SHIFT)) & SIUL2_PGPDO5_PPDO3_MASK) 6063 6064 #define SIUL2_PGPDO5_PPDO4_MASK (0x10U) 6065 #define SIUL2_PGPDO5_PPDO4_SHIFT (4U) 6066 #define SIUL2_PGPDO5_PPDO4_WIDTH (1U) 6067 #define SIUL2_PGPDO5_PPDO4(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO5_PPDO4_SHIFT)) & SIUL2_PGPDO5_PPDO4_MASK) 6068 6069 #define SIUL2_PGPDO5_PPDO5_MASK (0x20U) 6070 #define SIUL2_PGPDO5_PPDO5_SHIFT (5U) 6071 #define SIUL2_PGPDO5_PPDO5_WIDTH (1U) 6072 #define SIUL2_PGPDO5_PPDO5(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO5_PPDO5_SHIFT)) & SIUL2_PGPDO5_PPDO5_MASK) 6073 6074 #define SIUL2_PGPDO5_PPDO6_MASK (0x40U) 6075 #define SIUL2_PGPDO5_PPDO6_SHIFT (6U) 6076 #define SIUL2_PGPDO5_PPDO6_WIDTH (1U) 6077 #define SIUL2_PGPDO5_PPDO6(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO5_PPDO6_SHIFT)) & SIUL2_PGPDO5_PPDO6_MASK) 6078 6079 #define SIUL2_PGPDO5_PPDO7_MASK (0x80U) 6080 #define SIUL2_PGPDO5_PPDO7_SHIFT (7U) 6081 #define SIUL2_PGPDO5_PPDO7_WIDTH (1U) 6082 #define SIUL2_PGPDO5_PPDO7(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO5_PPDO7_SHIFT)) & SIUL2_PGPDO5_PPDO7_MASK) 6083 6084 #define SIUL2_PGPDO5_PPDO8_MASK (0x100U) 6085 #define SIUL2_PGPDO5_PPDO8_SHIFT (8U) 6086 #define SIUL2_PGPDO5_PPDO8_WIDTH (1U) 6087 #define SIUL2_PGPDO5_PPDO8(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO5_PPDO8_SHIFT)) & SIUL2_PGPDO5_PPDO8_MASK) 6088 6089 #define SIUL2_PGPDO5_PPDO9_MASK (0x200U) 6090 #define SIUL2_PGPDO5_PPDO9_SHIFT (9U) 6091 #define SIUL2_PGPDO5_PPDO9_WIDTH (1U) 6092 #define SIUL2_PGPDO5_PPDO9(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO5_PPDO9_SHIFT)) & SIUL2_PGPDO5_PPDO9_MASK) 6093 6094 #define SIUL2_PGPDO5_PPDO10_MASK (0x400U) 6095 #define SIUL2_PGPDO5_PPDO10_SHIFT (10U) 6096 #define SIUL2_PGPDO5_PPDO10_WIDTH (1U) 6097 #define SIUL2_PGPDO5_PPDO10(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO5_PPDO10_SHIFT)) & SIUL2_PGPDO5_PPDO10_MASK) 6098 6099 #define SIUL2_PGPDO5_PPDO11_MASK (0x800U) 6100 #define SIUL2_PGPDO5_PPDO11_SHIFT (11U) 6101 #define SIUL2_PGPDO5_PPDO11_WIDTH (1U) 6102 #define SIUL2_PGPDO5_PPDO11(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO5_PPDO11_SHIFT)) & SIUL2_PGPDO5_PPDO11_MASK) 6103 6104 #define SIUL2_PGPDO5_PPDO12_MASK (0x1000U) 6105 #define SIUL2_PGPDO5_PPDO12_SHIFT (12U) 6106 #define SIUL2_PGPDO5_PPDO12_WIDTH (1U) 6107 #define SIUL2_PGPDO5_PPDO12(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO5_PPDO12_SHIFT)) & SIUL2_PGPDO5_PPDO12_MASK) 6108 6109 #define SIUL2_PGPDO5_PPDO13_MASK (0x2000U) 6110 #define SIUL2_PGPDO5_PPDO13_SHIFT (13U) 6111 #define SIUL2_PGPDO5_PPDO13_WIDTH (1U) 6112 #define SIUL2_PGPDO5_PPDO13(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO5_PPDO13_SHIFT)) & SIUL2_PGPDO5_PPDO13_MASK) 6113 6114 #define SIUL2_PGPDO5_PPDO14_MASK (0x4000U) 6115 #define SIUL2_PGPDO5_PPDO14_SHIFT (14U) 6116 #define SIUL2_PGPDO5_PPDO14_WIDTH (1U) 6117 #define SIUL2_PGPDO5_PPDO14(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO5_PPDO14_SHIFT)) & SIUL2_PGPDO5_PPDO14_MASK) 6118 6119 #define SIUL2_PGPDO5_PPDO15_MASK (0x8000U) 6120 #define SIUL2_PGPDO5_PPDO15_SHIFT (15U) 6121 #define SIUL2_PGPDO5_PPDO15_WIDTH (1U) 6122 #define SIUL2_PGPDO5_PPDO15(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO5_PPDO15_SHIFT)) & SIUL2_PGPDO5_PPDO15_MASK) 6123 /*! @} */ 6124 6125 /*! @name PGPDO4 - SIUL2 Parallel GPIO Pad Data Out Register */ 6126 /*! @{ */ 6127 6128 #define SIUL2_PGPDO4_PPDO0_MASK (0x1U) 6129 #define SIUL2_PGPDO4_PPDO0_SHIFT (0U) 6130 #define SIUL2_PGPDO4_PPDO0_WIDTH (1U) 6131 #define SIUL2_PGPDO4_PPDO0(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO4_PPDO0_SHIFT)) & SIUL2_PGPDO4_PPDO0_MASK) 6132 6133 #define SIUL2_PGPDO4_PPDO1_MASK (0x2U) 6134 #define SIUL2_PGPDO4_PPDO1_SHIFT (1U) 6135 #define SIUL2_PGPDO4_PPDO1_WIDTH (1U) 6136 #define SIUL2_PGPDO4_PPDO1(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO4_PPDO1_SHIFT)) & SIUL2_PGPDO4_PPDO1_MASK) 6137 6138 #define SIUL2_PGPDO4_PPDO2_MASK (0x4U) 6139 #define SIUL2_PGPDO4_PPDO2_SHIFT (2U) 6140 #define SIUL2_PGPDO4_PPDO2_WIDTH (1U) 6141 #define SIUL2_PGPDO4_PPDO2(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO4_PPDO2_SHIFT)) & SIUL2_PGPDO4_PPDO2_MASK) 6142 6143 #define SIUL2_PGPDO4_PPDO3_MASK (0x8U) 6144 #define SIUL2_PGPDO4_PPDO3_SHIFT (3U) 6145 #define SIUL2_PGPDO4_PPDO3_WIDTH (1U) 6146 #define SIUL2_PGPDO4_PPDO3(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO4_PPDO3_SHIFT)) & SIUL2_PGPDO4_PPDO3_MASK) 6147 6148 #define SIUL2_PGPDO4_PPDO4_MASK (0x10U) 6149 #define SIUL2_PGPDO4_PPDO4_SHIFT (4U) 6150 #define SIUL2_PGPDO4_PPDO4_WIDTH (1U) 6151 #define SIUL2_PGPDO4_PPDO4(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO4_PPDO4_SHIFT)) & SIUL2_PGPDO4_PPDO4_MASK) 6152 6153 #define SIUL2_PGPDO4_PPDO5_MASK (0x20U) 6154 #define SIUL2_PGPDO4_PPDO5_SHIFT (5U) 6155 #define SIUL2_PGPDO4_PPDO5_WIDTH (1U) 6156 #define SIUL2_PGPDO4_PPDO5(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO4_PPDO5_SHIFT)) & SIUL2_PGPDO4_PPDO5_MASK) 6157 6158 #define SIUL2_PGPDO4_PPDO6_MASK (0x40U) 6159 #define SIUL2_PGPDO4_PPDO6_SHIFT (6U) 6160 #define SIUL2_PGPDO4_PPDO6_WIDTH (1U) 6161 #define SIUL2_PGPDO4_PPDO6(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO4_PPDO6_SHIFT)) & SIUL2_PGPDO4_PPDO6_MASK) 6162 6163 #define SIUL2_PGPDO4_PPDO7_MASK (0x80U) 6164 #define SIUL2_PGPDO4_PPDO7_SHIFT (7U) 6165 #define SIUL2_PGPDO4_PPDO7_WIDTH (1U) 6166 #define SIUL2_PGPDO4_PPDO7(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO4_PPDO7_SHIFT)) & SIUL2_PGPDO4_PPDO7_MASK) 6167 6168 #define SIUL2_PGPDO4_PPDO8_MASK (0x100U) 6169 #define SIUL2_PGPDO4_PPDO8_SHIFT (8U) 6170 #define SIUL2_PGPDO4_PPDO8_WIDTH (1U) 6171 #define SIUL2_PGPDO4_PPDO8(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO4_PPDO8_SHIFT)) & SIUL2_PGPDO4_PPDO8_MASK) 6172 6173 #define SIUL2_PGPDO4_PPDO9_MASK (0x200U) 6174 #define SIUL2_PGPDO4_PPDO9_SHIFT (9U) 6175 #define SIUL2_PGPDO4_PPDO9_WIDTH (1U) 6176 #define SIUL2_PGPDO4_PPDO9(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO4_PPDO9_SHIFT)) & SIUL2_PGPDO4_PPDO9_MASK) 6177 6178 #define SIUL2_PGPDO4_PPDO10_MASK (0x400U) 6179 #define SIUL2_PGPDO4_PPDO10_SHIFT (10U) 6180 #define SIUL2_PGPDO4_PPDO10_WIDTH (1U) 6181 #define SIUL2_PGPDO4_PPDO10(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO4_PPDO10_SHIFT)) & SIUL2_PGPDO4_PPDO10_MASK) 6182 6183 #define SIUL2_PGPDO4_PPDO11_MASK (0x800U) 6184 #define SIUL2_PGPDO4_PPDO11_SHIFT (11U) 6185 #define SIUL2_PGPDO4_PPDO11_WIDTH (1U) 6186 #define SIUL2_PGPDO4_PPDO11(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO4_PPDO11_SHIFT)) & SIUL2_PGPDO4_PPDO11_MASK) 6187 6188 #define SIUL2_PGPDO4_PPDO12_MASK (0x1000U) 6189 #define SIUL2_PGPDO4_PPDO12_SHIFT (12U) 6190 #define SIUL2_PGPDO4_PPDO12_WIDTH (1U) 6191 #define SIUL2_PGPDO4_PPDO12(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO4_PPDO12_SHIFT)) & SIUL2_PGPDO4_PPDO12_MASK) 6192 6193 #define SIUL2_PGPDO4_PPDO13_MASK (0x2000U) 6194 #define SIUL2_PGPDO4_PPDO13_SHIFT (13U) 6195 #define SIUL2_PGPDO4_PPDO13_WIDTH (1U) 6196 #define SIUL2_PGPDO4_PPDO13(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO4_PPDO13_SHIFT)) & SIUL2_PGPDO4_PPDO13_MASK) 6197 6198 #define SIUL2_PGPDO4_PPDO14_MASK (0x4000U) 6199 #define SIUL2_PGPDO4_PPDO14_SHIFT (14U) 6200 #define SIUL2_PGPDO4_PPDO14_WIDTH (1U) 6201 #define SIUL2_PGPDO4_PPDO14(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO4_PPDO14_SHIFT)) & SIUL2_PGPDO4_PPDO14_MASK) 6202 6203 #define SIUL2_PGPDO4_PPDO15_MASK (0x8000U) 6204 #define SIUL2_PGPDO4_PPDO15_SHIFT (15U) 6205 #define SIUL2_PGPDO4_PPDO15_WIDTH (1U) 6206 #define SIUL2_PGPDO4_PPDO15(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO4_PPDO15_SHIFT)) & SIUL2_PGPDO4_PPDO15_MASK) 6207 /*! @} */ 6208 6209 /*! @name PGPDO7 - SIUL2 Parallel GPIO Pad Data Out Register */ 6210 /*! @{ */ 6211 6212 #define SIUL2_PGPDO7_PPDO0_MASK (0x1U) 6213 #define SIUL2_PGPDO7_PPDO0_SHIFT (0U) 6214 #define SIUL2_PGPDO7_PPDO0_WIDTH (1U) 6215 #define SIUL2_PGPDO7_PPDO0(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO7_PPDO0_SHIFT)) & SIUL2_PGPDO7_PPDO0_MASK) 6216 6217 #define SIUL2_PGPDO7_PPDO1_MASK (0x2U) 6218 #define SIUL2_PGPDO7_PPDO1_SHIFT (1U) 6219 #define SIUL2_PGPDO7_PPDO1_WIDTH (1U) 6220 #define SIUL2_PGPDO7_PPDO1(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO7_PPDO1_SHIFT)) & SIUL2_PGPDO7_PPDO1_MASK) 6221 6222 #define SIUL2_PGPDO7_PPDO2_MASK (0x4U) 6223 #define SIUL2_PGPDO7_PPDO2_SHIFT (2U) 6224 #define SIUL2_PGPDO7_PPDO2_WIDTH (1U) 6225 #define SIUL2_PGPDO7_PPDO2(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO7_PPDO2_SHIFT)) & SIUL2_PGPDO7_PPDO2_MASK) 6226 6227 #define SIUL2_PGPDO7_PPDO3_MASK (0x8U) 6228 #define SIUL2_PGPDO7_PPDO3_SHIFT (3U) 6229 #define SIUL2_PGPDO7_PPDO3_WIDTH (1U) 6230 #define SIUL2_PGPDO7_PPDO3(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO7_PPDO3_SHIFT)) & SIUL2_PGPDO7_PPDO3_MASK) 6231 6232 #define SIUL2_PGPDO7_PPDO4_MASK (0x10U) 6233 #define SIUL2_PGPDO7_PPDO4_SHIFT (4U) 6234 #define SIUL2_PGPDO7_PPDO4_WIDTH (1U) 6235 #define SIUL2_PGPDO7_PPDO4(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO7_PPDO4_SHIFT)) & SIUL2_PGPDO7_PPDO4_MASK) 6236 6237 #define SIUL2_PGPDO7_PPDO5_MASK (0x20U) 6238 #define SIUL2_PGPDO7_PPDO5_SHIFT (5U) 6239 #define SIUL2_PGPDO7_PPDO5_WIDTH (1U) 6240 #define SIUL2_PGPDO7_PPDO5(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO7_PPDO5_SHIFT)) & SIUL2_PGPDO7_PPDO5_MASK) 6241 6242 #define SIUL2_PGPDO7_PPDO6_MASK (0x40U) 6243 #define SIUL2_PGPDO7_PPDO6_SHIFT (6U) 6244 #define SIUL2_PGPDO7_PPDO6_WIDTH (1U) 6245 #define SIUL2_PGPDO7_PPDO6(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO7_PPDO6_SHIFT)) & SIUL2_PGPDO7_PPDO6_MASK) 6246 6247 #define SIUL2_PGPDO7_PPDO7_MASK (0x80U) 6248 #define SIUL2_PGPDO7_PPDO7_SHIFT (7U) 6249 #define SIUL2_PGPDO7_PPDO7_WIDTH (1U) 6250 #define SIUL2_PGPDO7_PPDO7(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO7_PPDO7_SHIFT)) & SIUL2_PGPDO7_PPDO7_MASK) 6251 6252 #define SIUL2_PGPDO7_PPDO8_MASK (0x100U) 6253 #define SIUL2_PGPDO7_PPDO8_SHIFT (8U) 6254 #define SIUL2_PGPDO7_PPDO8_WIDTH (1U) 6255 #define SIUL2_PGPDO7_PPDO8(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO7_PPDO8_SHIFT)) & SIUL2_PGPDO7_PPDO8_MASK) 6256 6257 #define SIUL2_PGPDO7_PPDO9_MASK (0x200U) 6258 #define SIUL2_PGPDO7_PPDO9_SHIFT (9U) 6259 #define SIUL2_PGPDO7_PPDO9_WIDTH (1U) 6260 #define SIUL2_PGPDO7_PPDO9(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO7_PPDO9_SHIFT)) & SIUL2_PGPDO7_PPDO9_MASK) 6261 6262 #define SIUL2_PGPDO7_PPDO10_MASK (0x400U) 6263 #define SIUL2_PGPDO7_PPDO10_SHIFT (10U) 6264 #define SIUL2_PGPDO7_PPDO10_WIDTH (1U) 6265 #define SIUL2_PGPDO7_PPDO10(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO7_PPDO10_SHIFT)) & SIUL2_PGPDO7_PPDO10_MASK) 6266 6267 #define SIUL2_PGPDO7_PPDO11_MASK (0x800U) 6268 #define SIUL2_PGPDO7_PPDO11_SHIFT (11U) 6269 #define SIUL2_PGPDO7_PPDO11_WIDTH (1U) 6270 #define SIUL2_PGPDO7_PPDO11(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO7_PPDO11_SHIFT)) & SIUL2_PGPDO7_PPDO11_MASK) 6271 6272 #define SIUL2_PGPDO7_PPDO12_MASK (0x1000U) 6273 #define SIUL2_PGPDO7_PPDO12_SHIFT (12U) 6274 #define SIUL2_PGPDO7_PPDO12_WIDTH (1U) 6275 #define SIUL2_PGPDO7_PPDO12(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO7_PPDO12_SHIFT)) & SIUL2_PGPDO7_PPDO12_MASK) 6276 6277 #define SIUL2_PGPDO7_PPDO13_MASK (0x2000U) 6278 #define SIUL2_PGPDO7_PPDO13_SHIFT (13U) 6279 #define SIUL2_PGPDO7_PPDO13_WIDTH (1U) 6280 #define SIUL2_PGPDO7_PPDO13(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO7_PPDO13_SHIFT)) & SIUL2_PGPDO7_PPDO13_MASK) 6281 6282 #define SIUL2_PGPDO7_PPDO14_MASK (0x4000U) 6283 #define SIUL2_PGPDO7_PPDO14_SHIFT (14U) 6284 #define SIUL2_PGPDO7_PPDO14_WIDTH (1U) 6285 #define SIUL2_PGPDO7_PPDO14(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO7_PPDO14_SHIFT)) & SIUL2_PGPDO7_PPDO14_MASK) 6286 6287 #define SIUL2_PGPDO7_PPDO15_MASK (0x8000U) 6288 #define SIUL2_PGPDO7_PPDO15_SHIFT (15U) 6289 #define SIUL2_PGPDO7_PPDO15_WIDTH (1U) 6290 #define SIUL2_PGPDO7_PPDO15(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO7_PPDO15_SHIFT)) & SIUL2_PGPDO7_PPDO15_MASK) 6291 /*! @} */ 6292 6293 /*! @name PGPDO6 - SIUL2 Parallel GPIO Pad Data Out Register */ 6294 /*! @{ */ 6295 6296 #define SIUL2_PGPDO6_PPDO0_MASK (0x1U) 6297 #define SIUL2_PGPDO6_PPDO0_SHIFT (0U) 6298 #define SIUL2_PGPDO6_PPDO0_WIDTH (1U) 6299 #define SIUL2_PGPDO6_PPDO0(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO6_PPDO0_SHIFT)) & SIUL2_PGPDO6_PPDO0_MASK) 6300 6301 #define SIUL2_PGPDO6_PPDO1_MASK (0x2U) 6302 #define SIUL2_PGPDO6_PPDO1_SHIFT (1U) 6303 #define SIUL2_PGPDO6_PPDO1_WIDTH (1U) 6304 #define SIUL2_PGPDO6_PPDO1(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO6_PPDO1_SHIFT)) & SIUL2_PGPDO6_PPDO1_MASK) 6305 6306 #define SIUL2_PGPDO6_PPDO2_MASK (0x4U) 6307 #define SIUL2_PGPDO6_PPDO2_SHIFT (2U) 6308 #define SIUL2_PGPDO6_PPDO2_WIDTH (1U) 6309 #define SIUL2_PGPDO6_PPDO2(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO6_PPDO2_SHIFT)) & SIUL2_PGPDO6_PPDO2_MASK) 6310 6311 #define SIUL2_PGPDO6_PPDO3_MASK (0x8U) 6312 #define SIUL2_PGPDO6_PPDO3_SHIFT (3U) 6313 #define SIUL2_PGPDO6_PPDO3_WIDTH (1U) 6314 #define SIUL2_PGPDO6_PPDO3(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO6_PPDO3_SHIFT)) & SIUL2_PGPDO6_PPDO3_MASK) 6315 6316 #define SIUL2_PGPDO6_PPDO4_MASK (0x10U) 6317 #define SIUL2_PGPDO6_PPDO4_SHIFT (4U) 6318 #define SIUL2_PGPDO6_PPDO4_WIDTH (1U) 6319 #define SIUL2_PGPDO6_PPDO4(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO6_PPDO4_SHIFT)) & SIUL2_PGPDO6_PPDO4_MASK) 6320 6321 #define SIUL2_PGPDO6_PPDO5_MASK (0x20U) 6322 #define SIUL2_PGPDO6_PPDO5_SHIFT (5U) 6323 #define SIUL2_PGPDO6_PPDO5_WIDTH (1U) 6324 #define SIUL2_PGPDO6_PPDO5(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO6_PPDO5_SHIFT)) & SIUL2_PGPDO6_PPDO5_MASK) 6325 6326 #define SIUL2_PGPDO6_PPDO6_MASK (0x40U) 6327 #define SIUL2_PGPDO6_PPDO6_SHIFT (6U) 6328 #define SIUL2_PGPDO6_PPDO6_WIDTH (1U) 6329 #define SIUL2_PGPDO6_PPDO6(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO6_PPDO6_SHIFT)) & SIUL2_PGPDO6_PPDO6_MASK) 6330 6331 #define SIUL2_PGPDO6_PPDO7_MASK (0x80U) 6332 #define SIUL2_PGPDO6_PPDO7_SHIFT (7U) 6333 #define SIUL2_PGPDO6_PPDO7_WIDTH (1U) 6334 #define SIUL2_PGPDO6_PPDO7(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO6_PPDO7_SHIFT)) & SIUL2_PGPDO6_PPDO7_MASK) 6335 6336 #define SIUL2_PGPDO6_PPDO8_MASK (0x100U) 6337 #define SIUL2_PGPDO6_PPDO8_SHIFT (8U) 6338 #define SIUL2_PGPDO6_PPDO8_WIDTH (1U) 6339 #define SIUL2_PGPDO6_PPDO8(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO6_PPDO8_SHIFT)) & SIUL2_PGPDO6_PPDO8_MASK) 6340 6341 #define SIUL2_PGPDO6_PPDO9_MASK (0x200U) 6342 #define SIUL2_PGPDO6_PPDO9_SHIFT (9U) 6343 #define SIUL2_PGPDO6_PPDO9_WIDTH (1U) 6344 #define SIUL2_PGPDO6_PPDO9(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO6_PPDO9_SHIFT)) & SIUL2_PGPDO6_PPDO9_MASK) 6345 6346 #define SIUL2_PGPDO6_PPDO10_MASK (0x400U) 6347 #define SIUL2_PGPDO6_PPDO10_SHIFT (10U) 6348 #define SIUL2_PGPDO6_PPDO10_WIDTH (1U) 6349 #define SIUL2_PGPDO6_PPDO10(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO6_PPDO10_SHIFT)) & SIUL2_PGPDO6_PPDO10_MASK) 6350 6351 #define SIUL2_PGPDO6_PPDO11_MASK (0x800U) 6352 #define SIUL2_PGPDO6_PPDO11_SHIFT (11U) 6353 #define SIUL2_PGPDO6_PPDO11_WIDTH (1U) 6354 #define SIUL2_PGPDO6_PPDO11(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO6_PPDO11_SHIFT)) & SIUL2_PGPDO6_PPDO11_MASK) 6355 6356 #define SIUL2_PGPDO6_PPDO12_MASK (0x1000U) 6357 #define SIUL2_PGPDO6_PPDO12_SHIFT (12U) 6358 #define SIUL2_PGPDO6_PPDO12_WIDTH (1U) 6359 #define SIUL2_PGPDO6_PPDO12(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO6_PPDO12_SHIFT)) & SIUL2_PGPDO6_PPDO12_MASK) 6360 6361 #define SIUL2_PGPDO6_PPDO13_MASK (0x2000U) 6362 #define SIUL2_PGPDO6_PPDO13_SHIFT (13U) 6363 #define SIUL2_PGPDO6_PPDO13_WIDTH (1U) 6364 #define SIUL2_PGPDO6_PPDO13(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO6_PPDO13_SHIFT)) & SIUL2_PGPDO6_PPDO13_MASK) 6365 6366 #define SIUL2_PGPDO6_PPDO14_MASK (0x4000U) 6367 #define SIUL2_PGPDO6_PPDO14_SHIFT (14U) 6368 #define SIUL2_PGPDO6_PPDO14_WIDTH (1U) 6369 #define SIUL2_PGPDO6_PPDO14(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO6_PPDO14_SHIFT)) & SIUL2_PGPDO6_PPDO14_MASK) 6370 6371 #define SIUL2_PGPDO6_PPDO15_MASK (0x8000U) 6372 #define SIUL2_PGPDO6_PPDO15_SHIFT (15U) 6373 #define SIUL2_PGPDO6_PPDO15_WIDTH (1U) 6374 #define SIUL2_PGPDO6_PPDO15(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO6_PPDO15_SHIFT)) & SIUL2_PGPDO6_PPDO15_MASK) 6375 /*! @} */ 6376 6377 /*! @name PGPDO9 - SIUL2 Parallel GPIO Pad Data Out Register */ 6378 /*! @{ */ 6379 6380 #define SIUL2_PGPDO9_PPDO0_MASK (0x1U) 6381 #define SIUL2_PGPDO9_PPDO0_SHIFT (0U) 6382 #define SIUL2_PGPDO9_PPDO0_WIDTH (1U) 6383 #define SIUL2_PGPDO9_PPDO0(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO9_PPDO0_SHIFT)) & SIUL2_PGPDO9_PPDO0_MASK) 6384 6385 #define SIUL2_PGPDO9_PPDO1_MASK (0x2U) 6386 #define SIUL2_PGPDO9_PPDO1_SHIFT (1U) 6387 #define SIUL2_PGPDO9_PPDO1_WIDTH (1U) 6388 #define SIUL2_PGPDO9_PPDO1(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO9_PPDO1_SHIFT)) & SIUL2_PGPDO9_PPDO1_MASK) 6389 6390 #define SIUL2_PGPDO9_PPDO2_MASK (0x4U) 6391 #define SIUL2_PGPDO9_PPDO2_SHIFT (2U) 6392 #define SIUL2_PGPDO9_PPDO2_WIDTH (1U) 6393 #define SIUL2_PGPDO9_PPDO2(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO9_PPDO2_SHIFT)) & SIUL2_PGPDO9_PPDO2_MASK) 6394 6395 #define SIUL2_PGPDO9_PPDO3_MASK (0x8U) 6396 #define SIUL2_PGPDO9_PPDO3_SHIFT (3U) 6397 #define SIUL2_PGPDO9_PPDO3_WIDTH (1U) 6398 #define SIUL2_PGPDO9_PPDO3(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO9_PPDO3_SHIFT)) & SIUL2_PGPDO9_PPDO3_MASK) 6399 6400 #define SIUL2_PGPDO9_PPDO4_MASK (0x10U) 6401 #define SIUL2_PGPDO9_PPDO4_SHIFT (4U) 6402 #define SIUL2_PGPDO9_PPDO4_WIDTH (1U) 6403 #define SIUL2_PGPDO9_PPDO4(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO9_PPDO4_SHIFT)) & SIUL2_PGPDO9_PPDO4_MASK) 6404 6405 #define SIUL2_PGPDO9_PPDO5_MASK (0x20U) 6406 #define SIUL2_PGPDO9_PPDO5_SHIFT (5U) 6407 #define SIUL2_PGPDO9_PPDO5_WIDTH (1U) 6408 #define SIUL2_PGPDO9_PPDO5(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO9_PPDO5_SHIFT)) & SIUL2_PGPDO9_PPDO5_MASK) 6409 6410 #define SIUL2_PGPDO9_PPDO6_MASK (0x40U) 6411 #define SIUL2_PGPDO9_PPDO6_SHIFT (6U) 6412 #define SIUL2_PGPDO9_PPDO6_WIDTH (1U) 6413 #define SIUL2_PGPDO9_PPDO6(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO9_PPDO6_SHIFT)) & SIUL2_PGPDO9_PPDO6_MASK) 6414 6415 #define SIUL2_PGPDO9_PPDO7_MASK (0x80U) 6416 #define SIUL2_PGPDO9_PPDO7_SHIFT (7U) 6417 #define SIUL2_PGPDO9_PPDO7_WIDTH (1U) 6418 #define SIUL2_PGPDO9_PPDO7(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO9_PPDO7_SHIFT)) & SIUL2_PGPDO9_PPDO7_MASK) 6419 6420 #define SIUL2_PGPDO9_PPDO8_MASK (0x100U) 6421 #define SIUL2_PGPDO9_PPDO8_SHIFT (8U) 6422 #define SIUL2_PGPDO9_PPDO8_WIDTH (1U) 6423 #define SIUL2_PGPDO9_PPDO8(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO9_PPDO8_SHIFT)) & SIUL2_PGPDO9_PPDO8_MASK) 6424 6425 #define SIUL2_PGPDO9_PPDO9_MASK (0x200U) 6426 #define SIUL2_PGPDO9_PPDO9_SHIFT (9U) 6427 #define SIUL2_PGPDO9_PPDO9_WIDTH (1U) 6428 #define SIUL2_PGPDO9_PPDO9(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO9_PPDO9_SHIFT)) & SIUL2_PGPDO9_PPDO9_MASK) 6429 6430 #define SIUL2_PGPDO9_PPDO10_MASK (0x400U) 6431 #define SIUL2_PGPDO9_PPDO10_SHIFT (10U) 6432 #define SIUL2_PGPDO9_PPDO10_WIDTH (1U) 6433 #define SIUL2_PGPDO9_PPDO10(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO9_PPDO10_SHIFT)) & SIUL2_PGPDO9_PPDO10_MASK) 6434 6435 #define SIUL2_PGPDO9_PPDO11_MASK (0x800U) 6436 #define SIUL2_PGPDO9_PPDO11_SHIFT (11U) 6437 #define SIUL2_PGPDO9_PPDO11_WIDTH (1U) 6438 #define SIUL2_PGPDO9_PPDO11(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO9_PPDO11_SHIFT)) & SIUL2_PGPDO9_PPDO11_MASK) 6439 6440 #define SIUL2_PGPDO9_PPDO12_MASK (0x1000U) 6441 #define SIUL2_PGPDO9_PPDO12_SHIFT (12U) 6442 #define SIUL2_PGPDO9_PPDO12_WIDTH (1U) 6443 #define SIUL2_PGPDO9_PPDO12(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO9_PPDO12_SHIFT)) & SIUL2_PGPDO9_PPDO12_MASK) 6444 6445 #define SIUL2_PGPDO9_PPDO13_MASK (0x2000U) 6446 #define SIUL2_PGPDO9_PPDO13_SHIFT (13U) 6447 #define SIUL2_PGPDO9_PPDO13_WIDTH (1U) 6448 #define SIUL2_PGPDO9_PPDO13(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO9_PPDO13_SHIFT)) & SIUL2_PGPDO9_PPDO13_MASK) 6449 6450 #define SIUL2_PGPDO9_PPDO14_MASK (0x4000U) 6451 #define SIUL2_PGPDO9_PPDO14_SHIFT (14U) 6452 #define SIUL2_PGPDO9_PPDO14_WIDTH (1U) 6453 #define SIUL2_PGPDO9_PPDO14(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO9_PPDO14_SHIFT)) & SIUL2_PGPDO9_PPDO14_MASK) 6454 6455 #define SIUL2_PGPDO9_PPDO15_MASK (0x8000U) 6456 #define SIUL2_PGPDO9_PPDO15_SHIFT (15U) 6457 #define SIUL2_PGPDO9_PPDO15_WIDTH (1U) 6458 #define SIUL2_PGPDO9_PPDO15(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO9_PPDO15_SHIFT)) & SIUL2_PGPDO9_PPDO15_MASK) 6459 /*! @} */ 6460 6461 /*! @name PGPDO8 - SIUL2 Parallel GPIO Pad Data Out Register */ 6462 /*! @{ */ 6463 6464 #define SIUL2_PGPDO8_PPDO0_MASK (0x1U) 6465 #define SIUL2_PGPDO8_PPDO0_SHIFT (0U) 6466 #define SIUL2_PGPDO8_PPDO0_WIDTH (1U) 6467 #define SIUL2_PGPDO8_PPDO0(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO8_PPDO0_SHIFT)) & SIUL2_PGPDO8_PPDO0_MASK) 6468 6469 #define SIUL2_PGPDO8_PPDO1_MASK (0x2U) 6470 #define SIUL2_PGPDO8_PPDO1_SHIFT (1U) 6471 #define SIUL2_PGPDO8_PPDO1_WIDTH (1U) 6472 #define SIUL2_PGPDO8_PPDO1(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO8_PPDO1_SHIFT)) & SIUL2_PGPDO8_PPDO1_MASK) 6473 6474 #define SIUL2_PGPDO8_PPDO2_MASK (0x4U) 6475 #define SIUL2_PGPDO8_PPDO2_SHIFT (2U) 6476 #define SIUL2_PGPDO8_PPDO2_WIDTH (1U) 6477 #define SIUL2_PGPDO8_PPDO2(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO8_PPDO2_SHIFT)) & SIUL2_PGPDO8_PPDO2_MASK) 6478 6479 #define SIUL2_PGPDO8_PPDO3_MASK (0x8U) 6480 #define SIUL2_PGPDO8_PPDO3_SHIFT (3U) 6481 #define SIUL2_PGPDO8_PPDO3_WIDTH (1U) 6482 #define SIUL2_PGPDO8_PPDO3(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO8_PPDO3_SHIFT)) & SIUL2_PGPDO8_PPDO3_MASK) 6483 6484 #define SIUL2_PGPDO8_PPDO4_MASK (0x10U) 6485 #define SIUL2_PGPDO8_PPDO4_SHIFT (4U) 6486 #define SIUL2_PGPDO8_PPDO4_WIDTH (1U) 6487 #define SIUL2_PGPDO8_PPDO4(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO8_PPDO4_SHIFT)) & SIUL2_PGPDO8_PPDO4_MASK) 6488 6489 #define SIUL2_PGPDO8_PPDO5_MASK (0x20U) 6490 #define SIUL2_PGPDO8_PPDO5_SHIFT (5U) 6491 #define SIUL2_PGPDO8_PPDO5_WIDTH (1U) 6492 #define SIUL2_PGPDO8_PPDO5(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO8_PPDO5_SHIFT)) & SIUL2_PGPDO8_PPDO5_MASK) 6493 6494 #define SIUL2_PGPDO8_PPDO6_MASK (0x40U) 6495 #define SIUL2_PGPDO8_PPDO6_SHIFT (6U) 6496 #define SIUL2_PGPDO8_PPDO6_WIDTH (1U) 6497 #define SIUL2_PGPDO8_PPDO6(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO8_PPDO6_SHIFT)) & SIUL2_PGPDO8_PPDO6_MASK) 6498 6499 #define SIUL2_PGPDO8_PPDO7_MASK (0x80U) 6500 #define SIUL2_PGPDO8_PPDO7_SHIFT (7U) 6501 #define SIUL2_PGPDO8_PPDO7_WIDTH (1U) 6502 #define SIUL2_PGPDO8_PPDO7(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO8_PPDO7_SHIFT)) & SIUL2_PGPDO8_PPDO7_MASK) 6503 6504 #define SIUL2_PGPDO8_PPDO8_MASK (0x100U) 6505 #define SIUL2_PGPDO8_PPDO8_SHIFT (8U) 6506 #define SIUL2_PGPDO8_PPDO8_WIDTH (1U) 6507 #define SIUL2_PGPDO8_PPDO8(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO8_PPDO8_SHIFT)) & SIUL2_PGPDO8_PPDO8_MASK) 6508 6509 #define SIUL2_PGPDO8_PPDO9_MASK (0x200U) 6510 #define SIUL2_PGPDO8_PPDO9_SHIFT (9U) 6511 #define SIUL2_PGPDO8_PPDO9_WIDTH (1U) 6512 #define SIUL2_PGPDO8_PPDO9(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO8_PPDO9_SHIFT)) & SIUL2_PGPDO8_PPDO9_MASK) 6513 6514 #define SIUL2_PGPDO8_PPDO10_MASK (0x400U) 6515 #define SIUL2_PGPDO8_PPDO10_SHIFT (10U) 6516 #define SIUL2_PGPDO8_PPDO10_WIDTH (1U) 6517 #define SIUL2_PGPDO8_PPDO10(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO8_PPDO10_SHIFT)) & SIUL2_PGPDO8_PPDO10_MASK) 6518 6519 #define SIUL2_PGPDO8_PPDO11_MASK (0x800U) 6520 #define SIUL2_PGPDO8_PPDO11_SHIFT (11U) 6521 #define SIUL2_PGPDO8_PPDO11_WIDTH (1U) 6522 #define SIUL2_PGPDO8_PPDO11(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO8_PPDO11_SHIFT)) & SIUL2_PGPDO8_PPDO11_MASK) 6523 6524 #define SIUL2_PGPDO8_PPDO12_MASK (0x1000U) 6525 #define SIUL2_PGPDO8_PPDO12_SHIFT (12U) 6526 #define SIUL2_PGPDO8_PPDO12_WIDTH (1U) 6527 #define SIUL2_PGPDO8_PPDO12(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO8_PPDO12_SHIFT)) & SIUL2_PGPDO8_PPDO12_MASK) 6528 6529 #define SIUL2_PGPDO8_PPDO13_MASK (0x2000U) 6530 #define SIUL2_PGPDO8_PPDO13_SHIFT (13U) 6531 #define SIUL2_PGPDO8_PPDO13_WIDTH (1U) 6532 #define SIUL2_PGPDO8_PPDO13(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO8_PPDO13_SHIFT)) & SIUL2_PGPDO8_PPDO13_MASK) 6533 6534 #define SIUL2_PGPDO8_PPDO14_MASK (0x4000U) 6535 #define SIUL2_PGPDO8_PPDO14_SHIFT (14U) 6536 #define SIUL2_PGPDO8_PPDO14_WIDTH (1U) 6537 #define SIUL2_PGPDO8_PPDO14(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO8_PPDO14_SHIFT)) & SIUL2_PGPDO8_PPDO14_MASK) 6538 6539 #define SIUL2_PGPDO8_PPDO15_MASK (0x8000U) 6540 #define SIUL2_PGPDO8_PPDO15_SHIFT (15U) 6541 #define SIUL2_PGPDO8_PPDO15_WIDTH (1U) 6542 #define SIUL2_PGPDO8_PPDO15(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO8_PPDO15_SHIFT)) & SIUL2_PGPDO8_PPDO15_MASK) 6543 /*! @} */ 6544 6545 /*! @name PGPDO11 - SIUL2 Parallel GPIO Pad Data Out Register */ 6546 /*! @{ */ 6547 6548 #define SIUL2_PGPDO11_PPDO0_MASK (0x1U) 6549 #define SIUL2_PGPDO11_PPDO0_SHIFT (0U) 6550 #define SIUL2_PGPDO11_PPDO0_WIDTH (1U) 6551 #define SIUL2_PGPDO11_PPDO0(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO11_PPDO0_SHIFT)) & SIUL2_PGPDO11_PPDO0_MASK) 6552 6553 #define SIUL2_PGPDO11_PPDO1_MASK (0x2U) 6554 #define SIUL2_PGPDO11_PPDO1_SHIFT (1U) 6555 #define SIUL2_PGPDO11_PPDO1_WIDTH (1U) 6556 #define SIUL2_PGPDO11_PPDO1(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO11_PPDO1_SHIFT)) & SIUL2_PGPDO11_PPDO1_MASK) 6557 6558 #define SIUL2_PGPDO11_PPDO2_MASK (0x4U) 6559 #define SIUL2_PGPDO11_PPDO2_SHIFT (2U) 6560 #define SIUL2_PGPDO11_PPDO2_WIDTH (1U) 6561 #define SIUL2_PGPDO11_PPDO2(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO11_PPDO2_SHIFT)) & SIUL2_PGPDO11_PPDO2_MASK) 6562 6563 #define SIUL2_PGPDO11_PPDO3_MASK (0x8U) 6564 #define SIUL2_PGPDO11_PPDO3_SHIFT (3U) 6565 #define SIUL2_PGPDO11_PPDO3_WIDTH (1U) 6566 #define SIUL2_PGPDO11_PPDO3(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO11_PPDO3_SHIFT)) & SIUL2_PGPDO11_PPDO3_MASK) 6567 6568 #define SIUL2_PGPDO11_PPDO4_MASK (0x10U) 6569 #define SIUL2_PGPDO11_PPDO4_SHIFT (4U) 6570 #define SIUL2_PGPDO11_PPDO4_WIDTH (1U) 6571 #define SIUL2_PGPDO11_PPDO4(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO11_PPDO4_SHIFT)) & SIUL2_PGPDO11_PPDO4_MASK) 6572 6573 #define SIUL2_PGPDO11_PPDO5_MASK (0x20U) 6574 #define SIUL2_PGPDO11_PPDO5_SHIFT (5U) 6575 #define SIUL2_PGPDO11_PPDO5_WIDTH (1U) 6576 #define SIUL2_PGPDO11_PPDO5(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO11_PPDO5_SHIFT)) & SIUL2_PGPDO11_PPDO5_MASK) 6577 6578 #define SIUL2_PGPDO11_PPDO6_MASK (0x40U) 6579 #define SIUL2_PGPDO11_PPDO6_SHIFT (6U) 6580 #define SIUL2_PGPDO11_PPDO6_WIDTH (1U) 6581 #define SIUL2_PGPDO11_PPDO6(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO11_PPDO6_SHIFT)) & SIUL2_PGPDO11_PPDO6_MASK) 6582 6583 #define SIUL2_PGPDO11_PPDO7_MASK (0x80U) 6584 #define SIUL2_PGPDO11_PPDO7_SHIFT (7U) 6585 #define SIUL2_PGPDO11_PPDO7_WIDTH (1U) 6586 #define SIUL2_PGPDO11_PPDO7(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO11_PPDO7_SHIFT)) & SIUL2_PGPDO11_PPDO7_MASK) 6587 6588 #define SIUL2_PGPDO11_PPDO8_MASK (0x100U) 6589 #define SIUL2_PGPDO11_PPDO8_SHIFT (8U) 6590 #define SIUL2_PGPDO11_PPDO8_WIDTH (1U) 6591 #define SIUL2_PGPDO11_PPDO8(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO11_PPDO8_SHIFT)) & SIUL2_PGPDO11_PPDO8_MASK) 6592 6593 #define SIUL2_PGPDO11_PPDO9_MASK (0x200U) 6594 #define SIUL2_PGPDO11_PPDO9_SHIFT (9U) 6595 #define SIUL2_PGPDO11_PPDO9_WIDTH (1U) 6596 #define SIUL2_PGPDO11_PPDO9(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO11_PPDO9_SHIFT)) & SIUL2_PGPDO11_PPDO9_MASK) 6597 6598 #define SIUL2_PGPDO11_PPDO10_MASK (0x400U) 6599 #define SIUL2_PGPDO11_PPDO10_SHIFT (10U) 6600 #define SIUL2_PGPDO11_PPDO10_WIDTH (1U) 6601 #define SIUL2_PGPDO11_PPDO10(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO11_PPDO10_SHIFT)) & SIUL2_PGPDO11_PPDO10_MASK) 6602 6603 #define SIUL2_PGPDO11_PPDO11_MASK (0x800U) 6604 #define SIUL2_PGPDO11_PPDO11_SHIFT (11U) 6605 #define SIUL2_PGPDO11_PPDO11_WIDTH (1U) 6606 #define SIUL2_PGPDO11_PPDO11(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO11_PPDO11_SHIFT)) & SIUL2_PGPDO11_PPDO11_MASK) 6607 6608 #define SIUL2_PGPDO11_PPDO12_MASK (0x1000U) 6609 #define SIUL2_PGPDO11_PPDO12_SHIFT (12U) 6610 #define SIUL2_PGPDO11_PPDO12_WIDTH (1U) 6611 #define SIUL2_PGPDO11_PPDO12(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO11_PPDO12_SHIFT)) & SIUL2_PGPDO11_PPDO12_MASK) 6612 6613 #define SIUL2_PGPDO11_PPDO13_MASK (0x2000U) 6614 #define SIUL2_PGPDO11_PPDO13_SHIFT (13U) 6615 #define SIUL2_PGPDO11_PPDO13_WIDTH (1U) 6616 #define SIUL2_PGPDO11_PPDO13(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO11_PPDO13_SHIFT)) & SIUL2_PGPDO11_PPDO13_MASK) 6617 6618 #define SIUL2_PGPDO11_PPDO14_MASK (0x4000U) 6619 #define SIUL2_PGPDO11_PPDO14_SHIFT (14U) 6620 #define SIUL2_PGPDO11_PPDO14_WIDTH (1U) 6621 #define SIUL2_PGPDO11_PPDO14(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO11_PPDO14_SHIFT)) & SIUL2_PGPDO11_PPDO14_MASK) 6622 6623 #define SIUL2_PGPDO11_PPDO15_MASK (0x8000U) 6624 #define SIUL2_PGPDO11_PPDO15_SHIFT (15U) 6625 #define SIUL2_PGPDO11_PPDO15_WIDTH (1U) 6626 #define SIUL2_PGPDO11_PPDO15(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO11_PPDO15_SHIFT)) & SIUL2_PGPDO11_PPDO15_MASK) 6627 /*! @} */ 6628 6629 /*! @name PGPDO10 - SIUL2 Parallel GPIO Pad Data Out Register */ 6630 /*! @{ */ 6631 6632 #define SIUL2_PGPDO10_PPDO0_MASK (0x1U) 6633 #define SIUL2_PGPDO10_PPDO0_SHIFT (0U) 6634 #define SIUL2_PGPDO10_PPDO0_WIDTH (1U) 6635 #define SIUL2_PGPDO10_PPDO0(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO10_PPDO0_SHIFT)) & SIUL2_PGPDO10_PPDO0_MASK) 6636 6637 #define SIUL2_PGPDO10_PPDO1_MASK (0x2U) 6638 #define SIUL2_PGPDO10_PPDO1_SHIFT (1U) 6639 #define SIUL2_PGPDO10_PPDO1_WIDTH (1U) 6640 #define SIUL2_PGPDO10_PPDO1(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO10_PPDO1_SHIFT)) & SIUL2_PGPDO10_PPDO1_MASK) 6641 6642 #define SIUL2_PGPDO10_PPDO2_MASK (0x4U) 6643 #define SIUL2_PGPDO10_PPDO2_SHIFT (2U) 6644 #define SIUL2_PGPDO10_PPDO2_WIDTH (1U) 6645 #define SIUL2_PGPDO10_PPDO2(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO10_PPDO2_SHIFT)) & SIUL2_PGPDO10_PPDO2_MASK) 6646 6647 #define SIUL2_PGPDO10_PPDO3_MASK (0x8U) 6648 #define SIUL2_PGPDO10_PPDO3_SHIFT (3U) 6649 #define SIUL2_PGPDO10_PPDO3_WIDTH (1U) 6650 #define SIUL2_PGPDO10_PPDO3(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO10_PPDO3_SHIFT)) & SIUL2_PGPDO10_PPDO3_MASK) 6651 6652 #define SIUL2_PGPDO10_PPDO4_MASK (0x10U) 6653 #define SIUL2_PGPDO10_PPDO4_SHIFT (4U) 6654 #define SIUL2_PGPDO10_PPDO4_WIDTH (1U) 6655 #define SIUL2_PGPDO10_PPDO4(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO10_PPDO4_SHIFT)) & SIUL2_PGPDO10_PPDO4_MASK) 6656 6657 #define SIUL2_PGPDO10_PPDO5_MASK (0x20U) 6658 #define SIUL2_PGPDO10_PPDO5_SHIFT (5U) 6659 #define SIUL2_PGPDO10_PPDO5_WIDTH (1U) 6660 #define SIUL2_PGPDO10_PPDO5(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO10_PPDO5_SHIFT)) & SIUL2_PGPDO10_PPDO5_MASK) 6661 6662 #define SIUL2_PGPDO10_PPDO6_MASK (0x40U) 6663 #define SIUL2_PGPDO10_PPDO6_SHIFT (6U) 6664 #define SIUL2_PGPDO10_PPDO6_WIDTH (1U) 6665 #define SIUL2_PGPDO10_PPDO6(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO10_PPDO6_SHIFT)) & SIUL2_PGPDO10_PPDO6_MASK) 6666 6667 #define SIUL2_PGPDO10_PPDO7_MASK (0x80U) 6668 #define SIUL2_PGPDO10_PPDO7_SHIFT (7U) 6669 #define SIUL2_PGPDO10_PPDO7_WIDTH (1U) 6670 #define SIUL2_PGPDO10_PPDO7(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO10_PPDO7_SHIFT)) & SIUL2_PGPDO10_PPDO7_MASK) 6671 6672 #define SIUL2_PGPDO10_PPDO8_MASK (0x100U) 6673 #define SIUL2_PGPDO10_PPDO8_SHIFT (8U) 6674 #define SIUL2_PGPDO10_PPDO8_WIDTH (1U) 6675 #define SIUL2_PGPDO10_PPDO8(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO10_PPDO8_SHIFT)) & SIUL2_PGPDO10_PPDO8_MASK) 6676 6677 #define SIUL2_PGPDO10_PPDO9_MASK (0x200U) 6678 #define SIUL2_PGPDO10_PPDO9_SHIFT (9U) 6679 #define SIUL2_PGPDO10_PPDO9_WIDTH (1U) 6680 #define SIUL2_PGPDO10_PPDO9(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO10_PPDO9_SHIFT)) & SIUL2_PGPDO10_PPDO9_MASK) 6681 6682 #define SIUL2_PGPDO10_PPDO10_MASK (0x400U) 6683 #define SIUL2_PGPDO10_PPDO10_SHIFT (10U) 6684 #define SIUL2_PGPDO10_PPDO10_WIDTH (1U) 6685 #define SIUL2_PGPDO10_PPDO10(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO10_PPDO10_SHIFT)) & SIUL2_PGPDO10_PPDO10_MASK) 6686 6687 #define SIUL2_PGPDO10_PPDO11_MASK (0x800U) 6688 #define SIUL2_PGPDO10_PPDO11_SHIFT (11U) 6689 #define SIUL2_PGPDO10_PPDO11_WIDTH (1U) 6690 #define SIUL2_PGPDO10_PPDO11(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO10_PPDO11_SHIFT)) & SIUL2_PGPDO10_PPDO11_MASK) 6691 6692 #define SIUL2_PGPDO10_PPDO12_MASK (0x1000U) 6693 #define SIUL2_PGPDO10_PPDO12_SHIFT (12U) 6694 #define SIUL2_PGPDO10_PPDO12_WIDTH (1U) 6695 #define SIUL2_PGPDO10_PPDO12(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO10_PPDO12_SHIFT)) & SIUL2_PGPDO10_PPDO12_MASK) 6696 6697 #define SIUL2_PGPDO10_PPDO13_MASK (0x2000U) 6698 #define SIUL2_PGPDO10_PPDO13_SHIFT (13U) 6699 #define SIUL2_PGPDO10_PPDO13_WIDTH (1U) 6700 #define SIUL2_PGPDO10_PPDO13(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO10_PPDO13_SHIFT)) & SIUL2_PGPDO10_PPDO13_MASK) 6701 6702 #define SIUL2_PGPDO10_PPDO14_MASK (0x4000U) 6703 #define SIUL2_PGPDO10_PPDO14_SHIFT (14U) 6704 #define SIUL2_PGPDO10_PPDO14_WIDTH (1U) 6705 #define SIUL2_PGPDO10_PPDO14(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO10_PPDO14_SHIFT)) & SIUL2_PGPDO10_PPDO14_MASK) 6706 6707 #define SIUL2_PGPDO10_PPDO15_MASK (0x8000U) 6708 #define SIUL2_PGPDO10_PPDO15_SHIFT (15U) 6709 #define SIUL2_PGPDO10_PPDO15_WIDTH (1U) 6710 #define SIUL2_PGPDO10_PPDO15(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO10_PPDO15_SHIFT)) & SIUL2_PGPDO10_PPDO15_MASK) 6711 /*! @} */ 6712 6713 /*! @name PGPDO13 - SIUL2 Parallel GPIO Pad Data Out Register */ 6714 /*! @{ */ 6715 6716 #define SIUL2_PGPDO13_PPDO4_MASK (0x10U) 6717 #define SIUL2_PGPDO13_PPDO4_SHIFT (4U) 6718 #define SIUL2_PGPDO13_PPDO4_WIDTH (1U) 6719 #define SIUL2_PGPDO13_PPDO4(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO13_PPDO4_SHIFT)) & SIUL2_PGPDO13_PPDO4_MASK) 6720 6721 #define SIUL2_PGPDO13_PPDO5_MASK (0x20U) 6722 #define SIUL2_PGPDO13_PPDO5_SHIFT (5U) 6723 #define SIUL2_PGPDO13_PPDO5_WIDTH (1U) 6724 #define SIUL2_PGPDO13_PPDO5(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO13_PPDO5_SHIFT)) & SIUL2_PGPDO13_PPDO5_MASK) 6725 6726 #define SIUL2_PGPDO13_PPDO6_MASK (0x40U) 6727 #define SIUL2_PGPDO13_PPDO6_SHIFT (6U) 6728 #define SIUL2_PGPDO13_PPDO6_WIDTH (1U) 6729 #define SIUL2_PGPDO13_PPDO6(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO13_PPDO6_SHIFT)) & SIUL2_PGPDO13_PPDO6_MASK) 6730 6731 #define SIUL2_PGPDO13_PPDO7_MASK (0x80U) 6732 #define SIUL2_PGPDO13_PPDO7_SHIFT (7U) 6733 #define SIUL2_PGPDO13_PPDO7_WIDTH (1U) 6734 #define SIUL2_PGPDO13_PPDO7(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO13_PPDO7_SHIFT)) & SIUL2_PGPDO13_PPDO7_MASK) 6735 6736 #define SIUL2_PGPDO13_PPDO8_MASK (0x100U) 6737 #define SIUL2_PGPDO13_PPDO8_SHIFT (8U) 6738 #define SIUL2_PGPDO13_PPDO8_WIDTH (1U) 6739 #define SIUL2_PGPDO13_PPDO8(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO13_PPDO8_SHIFT)) & SIUL2_PGPDO13_PPDO8_MASK) 6740 6741 #define SIUL2_PGPDO13_PPDO9_MASK (0x200U) 6742 #define SIUL2_PGPDO13_PPDO9_SHIFT (9U) 6743 #define SIUL2_PGPDO13_PPDO9_WIDTH (1U) 6744 #define SIUL2_PGPDO13_PPDO9(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO13_PPDO9_SHIFT)) & SIUL2_PGPDO13_PPDO9_MASK) 6745 6746 #define SIUL2_PGPDO13_PPDO10_MASK (0x400U) 6747 #define SIUL2_PGPDO13_PPDO10_SHIFT (10U) 6748 #define SIUL2_PGPDO13_PPDO10_WIDTH (1U) 6749 #define SIUL2_PGPDO13_PPDO10(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO13_PPDO10_SHIFT)) & SIUL2_PGPDO13_PPDO10_MASK) 6750 6751 #define SIUL2_PGPDO13_PPDO11_MASK (0x800U) 6752 #define SIUL2_PGPDO13_PPDO11_SHIFT (11U) 6753 #define SIUL2_PGPDO13_PPDO11_WIDTH (1U) 6754 #define SIUL2_PGPDO13_PPDO11(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO13_PPDO11_SHIFT)) & SIUL2_PGPDO13_PPDO11_MASK) 6755 6756 #define SIUL2_PGPDO13_PPDO12_MASK (0x1000U) 6757 #define SIUL2_PGPDO13_PPDO12_SHIFT (12U) 6758 #define SIUL2_PGPDO13_PPDO12_WIDTH (1U) 6759 #define SIUL2_PGPDO13_PPDO12(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO13_PPDO12_SHIFT)) & SIUL2_PGPDO13_PPDO12_MASK) 6760 6761 #define SIUL2_PGPDO13_PPDO13_MASK (0x2000U) 6762 #define SIUL2_PGPDO13_PPDO13_SHIFT (13U) 6763 #define SIUL2_PGPDO13_PPDO13_WIDTH (1U) 6764 #define SIUL2_PGPDO13_PPDO13(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO13_PPDO13_SHIFT)) & SIUL2_PGPDO13_PPDO13_MASK) 6765 6766 #define SIUL2_PGPDO13_PPDO14_MASK (0x4000U) 6767 #define SIUL2_PGPDO13_PPDO14_SHIFT (14U) 6768 #define SIUL2_PGPDO13_PPDO14_WIDTH (1U) 6769 #define SIUL2_PGPDO13_PPDO14(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO13_PPDO14_SHIFT)) & SIUL2_PGPDO13_PPDO14_MASK) 6770 6771 #define SIUL2_PGPDO13_PPDO15_MASK (0x8000U) 6772 #define SIUL2_PGPDO13_PPDO15_SHIFT (15U) 6773 #define SIUL2_PGPDO13_PPDO15_WIDTH (1U) 6774 #define SIUL2_PGPDO13_PPDO15(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO13_PPDO15_SHIFT)) & SIUL2_PGPDO13_PPDO15_MASK) 6775 /*! @} */ 6776 6777 /*! @name PGPDO12 - SIUL2 Parallel GPIO Pad Data Out Register */ 6778 /*! @{ */ 6779 6780 #define SIUL2_PGPDO12_PPDO0_MASK (0x1U) 6781 #define SIUL2_PGPDO12_PPDO0_SHIFT (0U) 6782 #define SIUL2_PGPDO12_PPDO0_WIDTH (1U) 6783 #define SIUL2_PGPDO12_PPDO0(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO12_PPDO0_SHIFT)) & SIUL2_PGPDO12_PPDO0_MASK) 6784 6785 #define SIUL2_PGPDO12_PPDO1_MASK (0x2U) 6786 #define SIUL2_PGPDO12_PPDO1_SHIFT (1U) 6787 #define SIUL2_PGPDO12_PPDO1_WIDTH (1U) 6788 #define SIUL2_PGPDO12_PPDO1(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO12_PPDO1_SHIFT)) & SIUL2_PGPDO12_PPDO1_MASK) 6789 6790 #define SIUL2_PGPDO12_PPDO2_MASK (0x4U) 6791 #define SIUL2_PGPDO12_PPDO2_SHIFT (2U) 6792 #define SIUL2_PGPDO12_PPDO2_WIDTH (1U) 6793 #define SIUL2_PGPDO12_PPDO2(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO12_PPDO2_SHIFT)) & SIUL2_PGPDO12_PPDO2_MASK) 6794 6795 #define SIUL2_PGPDO12_PPDO3_MASK (0x8U) 6796 #define SIUL2_PGPDO12_PPDO3_SHIFT (3U) 6797 #define SIUL2_PGPDO12_PPDO3_WIDTH (1U) 6798 #define SIUL2_PGPDO12_PPDO3(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO12_PPDO3_SHIFT)) & SIUL2_PGPDO12_PPDO3_MASK) 6799 6800 #define SIUL2_PGPDO12_PPDO4_MASK (0x10U) 6801 #define SIUL2_PGPDO12_PPDO4_SHIFT (4U) 6802 #define SIUL2_PGPDO12_PPDO4_WIDTH (1U) 6803 #define SIUL2_PGPDO12_PPDO4(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO12_PPDO4_SHIFT)) & SIUL2_PGPDO12_PPDO4_MASK) 6804 6805 #define SIUL2_PGPDO12_PPDO5_MASK (0x20U) 6806 #define SIUL2_PGPDO12_PPDO5_SHIFT (5U) 6807 #define SIUL2_PGPDO12_PPDO5_WIDTH (1U) 6808 #define SIUL2_PGPDO12_PPDO5(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO12_PPDO5_SHIFT)) & SIUL2_PGPDO12_PPDO5_MASK) 6809 6810 #define SIUL2_PGPDO12_PPDO6_MASK (0x40U) 6811 #define SIUL2_PGPDO12_PPDO6_SHIFT (6U) 6812 #define SIUL2_PGPDO12_PPDO6_WIDTH (1U) 6813 #define SIUL2_PGPDO12_PPDO6(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO12_PPDO6_SHIFT)) & SIUL2_PGPDO12_PPDO6_MASK) 6814 6815 #define SIUL2_PGPDO12_PPDO7_MASK (0x80U) 6816 #define SIUL2_PGPDO12_PPDO7_SHIFT (7U) 6817 #define SIUL2_PGPDO12_PPDO7_WIDTH (1U) 6818 #define SIUL2_PGPDO12_PPDO7(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO12_PPDO7_SHIFT)) & SIUL2_PGPDO12_PPDO7_MASK) 6819 6820 #define SIUL2_PGPDO12_PPDO8_MASK (0x100U) 6821 #define SIUL2_PGPDO12_PPDO8_SHIFT (8U) 6822 #define SIUL2_PGPDO12_PPDO8_WIDTH (1U) 6823 #define SIUL2_PGPDO12_PPDO8(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO12_PPDO8_SHIFT)) & SIUL2_PGPDO12_PPDO8_MASK) 6824 6825 #define SIUL2_PGPDO12_PPDO9_MASK (0x200U) 6826 #define SIUL2_PGPDO12_PPDO9_SHIFT (9U) 6827 #define SIUL2_PGPDO12_PPDO9_WIDTH (1U) 6828 #define SIUL2_PGPDO12_PPDO9(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO12_PPDO9_SHIFT)) & SIUL2_PGPDO12_PPDO9_MASK) 6829 6830 #define SIUL2_PGPDO12_PPDO10_MASK (0x400U) 6831 #define SIUL2_PGPDO12_PPDO10_SHIFT (10U) 6832 #define SIUL2_PGPDO12_PPDO10_WIDTH (1U) 6833 #define SIUL2_PGPDO12_PPDO10(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO12_PPDO10_SHIFT)) & SIUL2_PGPDO12_PPDO10_MASK) 6834 6835 #define SIUL2_PGPDO12_PPDO11_MASK (0x800U) 6836 #define SIUL2_PGPDO12_PPDO11_SHIFT (11U) 6837 #define SIUL2_PGPDO12_PPDO11_WIDTH (1U) 6838 #define SIUL2_PGPDO12_PPDO11(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO12_PPDO11_SHIFT)) & SIUL2_PGPDO12_PPDO11_MASK) 6839 6840 #define SIUL2_PGPDO12_PPDO12_MASK (0x1000U) 6841 #define SIUL2_PGPDO12_PPDO12_SHIFT (12U) 6842 #define SIUL2_PGPDO12_PPDO12_WIDTH (1U) 6843 #define SIUL2_PGPDO12_PPDO12(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO12_PPDO12_SHIFT)) & SIUL2_PGPDO12_PPDO12_MASK) 6844 6845 #define SIUL2_PGPDO12_PPDO13_MASK (0x2000U) 6846 #define SIUL2_PGPDO12_PPDO13_SHIFT (13U) 6847 #define SIUL2_PGPDO12_PPDO13_WIDTH (1U) 6848 #define SIUL2_PGPDO12_PPDO13(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO12_PPDO13_SHIFT)) & SIUL2_PGPDO12_PPDO13_MASK) 6849 6850 #define SIUL2_PGPDO12_PPDO14_MASK (0x4000U) 6851 #define SIUL2_PGPDO12_PPDO14_SHIFT (14U) 6852 #define SIUL2_PGPDO12_PPDO14_WIDTH (1U) 6853 #define SIUL2_PGPDO12_PPDO14(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO12_PPDO14_SHIFT)) & SIUL2_PGPDO12_PPDO14_MASK) 6854 6855 #define SIUL2_PGPDO12_PPDO15_MASK (0x8000U) 6856 #define SIUL2_PGPDO12_PPDO15_SHIFT (15U) 6857 #define SIUL2_PGPDO12_PPDO15_WIDTH (1U) 6858 #define SIUL2_PGPDO12_PPDO15(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO12_PPDO15_SHIFT)) & SIUL2_PGPDO12_PPDO15_MASK) 6859 /*! @} */ 6860 6861 /*! @name PGPDI1 - SIUL2 Parallel GPIO Pad Data In Register */ 6862 /*! @{ */ 6863 6864 #define SIUL2_PGPDI1_PPDI0_MASK (0x1U) 6865 #define SIUL2_PGPDI1_PPDI0_SHIFT (0U) 6866 #define SIUL2_PGPDI1_PPDI0_WIDTH (1U) 6867 #define SIUL2_PGPDI1_PPDI0(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI1_PPDI0_SHIFT)) & SIUL2_PGPDI1_PPDI0_MASK) 6868 6869 #define SIUL2_PGPDI1_PPDI1_MASK (0x2U) 6870 #define SIUL2_PGPDI1_PPDI1_SHIFT (1U) 6871 #define SIUL2_PGPDI1_PPDI1_WIDTH (1U) 6872 #define SIUL2_PGPDI1_PPDI1(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI1_PPDI1_SHIFT)) & SIUL2_PGPDI1_PPDI1_MASK) 6873 6874 #define SIUL2_PGPDI1_PPDI2_MASK (0x4U) 6875 #define SIUL2_PGPDI1_PPDI2_SHIFT (2U) 6876 #define SIUL2_PGPDI1_PPDI2_WIDTH (1U) 6877 #define SIUL2_PGPDI1_PPDI2(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI1_PPDI2_SHIFT)) & SIUL2_PGPDI1_PPDI2_MASK) 6878 6879 #define SIUL2_PGPDI1_PPDI3_MASK (0x8U) 6880 #define SIUL2_PGPDI1_PPDI3_SHIFT (3U) 6881 #define SIUL2_PGPDI1_PPDI3_WIDTH (1U) 6882 #define SIUL2_PGPDI1_PPDI3(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI1_PPDI3_SHIFT)) & SIUL2_PGPDI1_PPDI3_MASK) 6883 6884 #define SIUL2_PGPDI1_PPDI4_MASK (0x10U) 6885 #define SIUL2_PGPDI1_PPDI4_SHIFT (4U) 6886 #define SIUL2_PGPDI1_PPDI4_WIDTH (1U) 6887 #define SIUL2_PGPDI1_PPDI4(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI1_PPDI4_SHIFT)) & SIUL2_PGPDI1_PPDI4_MASK) 6888 6889 #define SIUL2_PGPDI1_PPDI5_MASK (0x20U) 6890 #define SIUL2_PGPDI1_PPDI5_SHIFT (5U) 6891 #define SIUL2_PGPDI1_PPDI5_WIDTH (1U) 6892 #define SIUL2_PGPDI1_PPDI5(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI1_PPDI5_SHIFT)) & SIUL2_PGPDI1_PPDI5_MASK) 6893 6894 #define SIUL2_PGPDI1_PPDI6_MASK (0x40U) 6895 #define SIUL2_PGPDI1_PPDI6_SHIFT (6U) 6896 #define SIUL2_PGPDI1_PPDI6_WIDTH (1U) 6897 #define SIUL2_PGPDI1_PPDI6(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI1_PPDI6_SHIFT)) & SIUL2_PGPDI1_PPDI6_MASK) 6898 6899 #define SIUL2_PGPDI1_PPDI7_MASK (0x80U) 6900 #define SIUL2_PGPDI1_PPDI7_SHIFT (7U) 6901 #define SIUL2_PGPDI1_PPDI7_WIDTH (1U) 6902 #define SIUL2_PGPDI1_PPDI7(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI1_PPDI7_SHIFT)) & SIUL2_PGPDI1_PPDI7_MASK) 6903 6904 #define SIUL2_PGPDI1_PPDI8_MASK (0x100U) 6905 #define SIUL2_PGPDI1_PPDI8_SHIFT (8U) 6906 #define SIUL2_PGPDI1_PPDI8_WIDTH (1U) 6907 #define SIUL2_PGPDI1_PPDI8(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI1_PPDI8_SHIFT)) & SIUL2_PGPDI1_PPDI8_MASK) 6908 6909 #define SIUL2_PGPDI1_PPDI9_MASK (0x200U) 6910 #define SIUL2_PGPDI1_PPDI9_SHIFT (9U) 6911 #define SIUL2_PGPDI1_PPDI9_WIDTH (1U) 6912 #define SIUL2_PGPDI1_PPDI9(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI1_PPDI9_SHIFT)) & SIUL2_PGPDI1_PPDI9_MASK) 6913 6914 #define SIUL2_PGPDI1_PPDI10_MASK (0x400U) 6915 #define SIUL2_PGPDI1_PPDI10_SHIFT (10U) 6916 #define SIUL2_PGPDI1_PPDI10_WIDTH (1U) 6917 #define SIUL2_PGPDI1_PPDI10(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI1_PPDI10_SHIFT)) & SIUL2_PGPDI1_PPDI10_MASK) 6918 6919 #define SIUL2_PGPDI1_PPDI11_MASK (0x800U) 6920 #define SIUL2_PGPDI1_PPDI11_SHIFT (11U) 6921 #define SIUL2_PGPDI1_PPDI11_WIDTH (1U) 6922 #define SIUL2_PGPDI1_PPDI11(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI1_PPDI11_SHIFT)) & SIUL2_PGPDI1_PPDI11_MASK) 6923 6924 #define SIUL2_PGPDI1_PPDI12_MASK (0x1000U) 6925 #define SIUL2_PGPDI1_PPDI12_SHIFT (12U) 6926 #define SIUL2_PGPDI1_PPDI12_WIDTH (1U) 6927 #define SIUL2_PGPDI1_PPDI12(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI1_PPDI12_SHIFT)) & SIUL2_PGPDI1_PPDI12_MASK) 6928 6929 #define SIUL2_PGPDI1_PPDI13_MASK (0x2000U) 6930 #define SIUL2_PGPDI1_PPDI13_SHIFT (13U) 6931 #define SIUL2_PGPDI1_PPDI13_WIDTH (1U) 6932 #define SIUL2_PGPDI1_PPDI13(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI1_PPDI13_SHIFT)) & SIUL2_PGPDI1_PPDI13_MASK) 6933 6934 #define SIUL2_PGPDI1_PPDI14_MASK (0x4000U) 6935 #define SIUL2_PGPDI1_PPDI14_SHIFT (14U) 6936 #define SIUL2_PGPDI1_PPDI14_WIDTH (1U) 6937 #define SIUL2_PGPDI1_PPDI14(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI1_PPDI14_SHIFT)) & SIUL2_PGPDI1_PPDI14_MASK) 6938 6939 #define SIUL2_PGPDI1_PPDI15_MASK (0x8000U) 6940 #define SIUL2_PGPDI1_PPDI15_SHIFT (15U) 6941 #define SIUL2_PGPDI1_PPDI15_WIDTH (1U) 6942 #define SIUL2_PGPDI1_PPDI15(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI1_PPDI15_SHIFT)) & SIUL2_PGPDI1_PPDI15_MASK) 6943 /*! @} */ 6944 6945 /*! @name PGPDI0 - SIUL2 Parallel GPIO Pad Data In Register */ 6946 /*! @{ */ 6947 6948 #define SIUL2_PGPDI0_PPDI0_MASK (0x1U) 6949 #define SIUL2_PGPDI0_PPDI0_SHIFT (0U) 6950 #define SIUL2_PGPDI0_PPDI0_WIDTH (1U) 6951 #define SIUL2_PGPDI0_PPDI0(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI0_PPDI0_SHIFT)) & SIUL2_PGPDI0_PPDI0_MASK) 6952 6953 #define SIUL2_PGPDI0_PPDI1_MASK (0x2U) 6954 #define SIUL2_PGPDI0_PPDI1_SHIFT (1U) 6955 #define SIUL2_PGPDI0_PPDI1_WIDTH (1U) 6956 #define SIUL2_PGPDI0_PPDI1(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI0_PPDI1_SHIFT)) & SIUL2_PGPDI0_PPDI1_MASK) 6957 6958 #define SIUL2_PGPDI0_PPDI2_MASK (0x4U) 6959 #define SIUL2_PGPDI0_PPDI2_SHIFT (2U) 6960 #define SIUL2_PGPDI0_PPDI2_WIDTH (1U) 6961 #define SIUL2_PGPDI0_PPDI2(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI0_PPDI2_SHIFT)) & SIUL2_PGPDI0_PPDI2_MASK) 6962 6963 #define SIUL2_PGPDI0_PPDI3_MASK (0x8U) 6964 #define SIUL2_PGPDI0_PPDI3_SHIFT (3U) 6965 #define SIUL2_PGPDI0_PPDI3_WIDTH (1U) 6966 #define SIUL2_PGPDI0_PPDI3(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI0_PPDI3_SHIFT)) & SIUL2_PGPDI0_PPDI3_MASK) 6967 6968 #define SIUL2_PGPDI0_PPDI4_MASK (0x10U) 6969 #define SIUL2_PGPDI0_PPDI4_SHIFT (4U) 6970 #define SIUL2_PGPDI0_PPDI4_WIDTH (1U) 6971 #define SIUL2_PGPDI0_PPDI4(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI0_PPDI4_SHIFT)) & SIUL2_PGPDI0_PPDI4_MASK) 6972 6973 #define SIUL2_PGPDI0_PPDI5_MASK (0x20U) 6974 #define SIUL2_PGPDI0_PPDI5_SHIFT (5U) 6975 #define SIUL2_PGPDI0_PPDI5_WIDTH (1U) 6976 #define SIUL2_PGPDI0_PPDI5(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI0_PPDI5_SHIFT)) & SIUL2_PGPDI0_PPDI5_MASK) 6977 6978 #define SIUL2_PGPDI0_PPDI6_MASK (0x40U) 6979 #define SIUL2_PGPDI0_PPDI6_SHIFT (6U) 6980 #define SIUL2_PGPDI0_PPDI6_WIDTH (1U) 6981 #define SIUL2_PGPDI0_PPDI6(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI0_PPDI6_SHIFT)) & SIUL2_PGPDI0_PPDI6_MASK) 6982 6983 #define SIUL2_PGPDI0_PPDI7_MASK (0x80U) 6984 #define SIUL2_PGPDI0_PPDI7_SHIFT (7U) 6985 #define SIUL2_PGPDI0_PPDI7_WIDTH (1U) 6986 #define SIUL2_PGPDI0_PPDI7(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI0_PPDI7_SHIFT)) & SIUL2_PGPDI0_PPDI7_MASK) 6987 6988 #define SIUL2_PGPDI0_PPDI8_MASK (0x100U) 6989 #define SIUL2_PGPDI0_PPDI8_SHIFT (8U) 6990 #define SIUL2_PGPDI0_PPDI8_WIDTH (1U) 6991 #define SIUL2_PGPDI0_PPDI8(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI0_PPDI8_SHIFT)) & SIUL2_PGPDI0_PPDI8_MASK) 6992 6993 #define SIUL2_PGPDI0_PPDI9_MASK (0x200U) 6994 #define SIUL2_PGPDI0_PPDI9_SHIFT (9U) 6995 #define SIUL2_PGPDI0_PPDI9_WIDTH (1U) 6996 #define SIUL2_PGPDI0_PPDI9(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI0_PPDI9_SHIFT)) & SIUL2_PGPDI0_PPDI9_MASK) 6997 6998 #define SIUL2_PGPDI0_PPDI10_MASK (0x400U) 6999 #define SIUL2_PGPDI0_PPDI10_SHIFT (10U) 7000 #define SIUL2_PGPDI0_PPDI10_WIDTH (1U) 7001 #define SIUL2_PGPDI0_PPDI10(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI0_PPDI10_SHIFT)) & SIUL2_PGPDI0_PPDI10_MASK) 7002 7003 #define SIUL2_PGPDI0_PPDI11_MASK (0x800U) 7004 #define SIUL2_PGPDI0_PPDI11_SHIFT (11U) 7005 #define SIUL2_PGPDI0_PPDI11_WIDTH (1U) 7006 #define SIUL2_PGPDI0_PPDI11(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI0_PPDI11_SHIFT)) & SIUL2_PGPDI0_PPDI11_MASK) 7007 7008 #define SIUL2_PGPDI0_PPDI12_MASK (0x1000U) 7009 #define SIUL2_PGPDI0_PPDI12_SHIFT (12U) 7010 #define SIUL2_PGPDI0_PPDI12_WIDTH (1U) 7011 #define SIUL2_PGPDI0_PPDI12(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI0_PPDI12_SHIFT)) & SIUL2_PGPDI0_PPDI12_MASK) 7012 7013 #define SIUL2_PGPDI0_PPDI13_MASK (0x2000U) 7014 #define SIUL2_PGPDI0_PPDI13_SHIFT (13U) 7015 #define SIUL2_PGPDI0_PPDI13_WIDTH (1U) 7016 #define SIUL2_PGPDI0_PPDI13(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI0_PPDI13_SHIFT)) & SIUL2_PGPDI0_PPDI13_MASK) 7017 7018 #define SIUL2_PGPDI0_PPDI14_MASK (0x4000U) 7019 #define SIUL2_PGPDI0_PPDI14_SHIFT (14U) 7020 #define SIUL2_PGPDI0_PPDI14_WIDTH (1U) 7021 #define SIUL2_PGPDI0_PPDI14(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI0_PPDI14_SHIFT)) & SIUL2_PGPDI0_PPDI14_MASK) 7022 7023 #define SIUL2_PGPDI0_PPDI15_MASK (0x8000U) 7024 #define SIUL2_PGPDI0_PPDI15_SHIFT (15U) 7025 #define SIUL2_PGPDI0_PPDI15_WIDTH (1U) 7026 #define SIUL2_PGPDI0_PPDI15(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI0_PPDI15_SHIFT)) & SIUL2_PGPDI0_PPDI15_MASK) 7027 /*! @} */ 7028 7029 /*! @name PGPDI3 - SIUL2 Parallel GPIO Pad Data In Register */ 7030 /*! @{ */ 7031 7032 #define SIUL2_PGPDI3_PPDI0_MASK (0x1U) 7033 #define SIUL2_PGPDI3_PPDI0_SHIFT (0U) 7034 #define SIUL2_PGPDI3_PPDI0_WIDTH (1U) 7035 #define SIUL2_PGPDI3_PPDI0(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI3_PPDI0_SHIFT)) & SIUL2_PGPDI3_PPDI0_MASK) 7036 7037 #define SIUL2_PGPDI3_PPDI1_MASK (0x2U) 7038 #define SIUL2_PGPDI3_PPDI1_SHIFT (1U) 7039 #define SIUL2_PGPDI3_PPDI1_WIDTH (1U) 7040 #define SIUL2_PGPDI3_PPDI1(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI3_PPDI1_SHIFT)) & SIUL2_PGPDI3_PPDI1_MASK) 7041 7042 #define SIUL2_PGPDI3_PPDI2_MASK (0x4U) 7043 #define SIUL2_PGPDI3_PPDI2_SHIFT (2U) 7044 #define SIUL2_PGPDI3_PPDI2_WIDTH (1U) 7045 #define SIUL2_PGPDI3_PPDI2(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI3_PPDI2_SHIFT)) & SIUL2_PGPDI3_PPDI2_MASK) 7046 7047 #define SIUL2_PGPDI3_PPDI3_MASK (0x8U) 7048 #define SIUL2_PGPDI3_PPDI3_SHIFT (3U) 7049 #define SIUL2_PGPDI3_PPDI3_WIDTH (1U) 7050 #define SIUL2_PGPDI3_PPDI3(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI3_PPDI3_SHIFT)) & SIUL2_PGPDI3_PPDI3_MASK) 7051 7052 #define SIUL2_PGPDI3_PPDI4_MASK (0x10U) 7053 #define SIUL2_PGPDI3_PPDI4_SHIFT (4U) 7054 #define SIUL2_PGPDI3_PPDI4_WIDTH (1U) 7055 #define SIUL2_PGPDI3_PPDI4(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI3_PPDI4_SHIFT)) & SIUL2_PGPDI3_PPDI4_MASK) 7056 7057 #define SIUL2_PGPDI3_PPDI5_MASK (0x20U) 7058 #define SIUL2_PGPDI3_PPDI5_SHIFT (5U) 7059 #define SIUL2_PGPDI3_PPDI5_WIDTH (1U) 7060 #define SIUL2_PGPDI3_PPDI5(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI3_PPDI5_SHIFT)) & SIUL2_PGPDI3_PPDI5_MASK) 7061 7062 #define SIUL2_PGPDI3_PPDI6_MASK (0x40U) 7063 #define SIUL2_PGPDI3_PPDI6_SHIFT (6U) 7064 #define SIUL2_PGPDI3_PPDI6_WIDTH (1U) 7065 #define SIUL2_PGPDI3_PPDI6(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI3_PPDI6_SHIFT)) & SIUL2_PGPDI3_PPDI6_MASK) 7066 7067 #define SIUL2_PGPDI3_PPDI7_MASK (0x80U) 7068 #define SIUL2_PGPDI3_PPDI7_SHIFT (7U) 7069 #define SIUL2_PGPDI3_PPDI7_WIDTH (1U) 7070 #define SIUL2_PGPDI3_PPDI7(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI3_PPDI7_SHIFT)) & SIUL2_PGPDI3_PPDI7_MASK) 7071 7072 #define SIUL2_PGPDI3_PPDI8_MASK (0x100U) 7073 #define SIUL2_PGPDI3_PPDI8_SHIFT (8U) 7074 #define SIUL2_PGPDI3_PPDI8_WIDTH (1U) 7075 #define SIUL2_PGPDI3_PPDI8(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI3_PPDI8_SHIFT)) & SIUL2_PGPDI3_PPDI8_MASK) 7076 7077 #define SIUL2_PGPDI3_PPDI9_MASK (0x200U) 7078 #define SIUL2_PGPDI3_PPDI9_SHIFT (9U) 7079 #define SIUL2_PGPDI3_PPDI9_WIDTH (1U) 7080 #define SIUL2_PGPDI3_PPDI9(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI3_PPDI9_SHIFT)) & SIUL2_PGPDI3_PPDI9_MASK) 7081 7082 #define SIUL2_PGPDI3_PPDI10_MASK (0x400U) 7083 #define SIUL2_PGPDI3_PPDI10_SHIFT (10U) 7084 #define SIUL2_PGPDI3_PPDI10_WIDTH (1U) 7085 #define SIUL2_PGPDI3_PPDI10(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI3_PPDI10_SHIFT)) & SIUL2_PGPDI3_PPDI10_MASK) 7086 7087 #define SIUL2_PGPDI3_PPDI11_MASK (0x800U) 7088 #define SIUL2_PGPDI3_PPDI11_SHIFT (11U) 7089 #define SIUL2_PGPDI3_PPDI11_WIDTH (1U) 7090 #define SIUL2_PGPDI3_PPDI11(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI3_PPDI11_SHIFT)) & SIUL2_PGPDI3_PPDI11_MASK) 7091 7092 #define SIUL2_PGPDI3_PPDI12_MASK (0x1000U) 7093 #define SIUL2_PGPDI3_PPDI12_SHIFT (12U) 7094 #define SIUL2_PGPDI3_PPDI12_WIDTH (1U) 7095 #define SIUL2_PGPDI3_PPDI12(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI3_PPDI12_SHIFT)) & SIUL2_PGPDI3_PPDI12_MASK) 7096 7097 #define SIUL2_PGPDI3_PPDI13_MASK (0x2000U) 7098 #define SIUL2_PGPDI3_PPDI13_SHIFT (13U) 7099 #define SIUL2_PGPDI3_PPDI13_WIDTH (1U) 7100 #define SIUL2_PGPDI3_PPDI13(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI3_PPDI13_SHIFT)) & SIUL2_PGPDI3_PPDI13_MASK) 7101 7102 #define SIUL2_PGPDI3_PPDI14_MASK (0x4000U) 7103 #define SIUL2_PGPDI3_PPDI14_SHIFT (14U) 7104 #define SIUL2_PGPDI3_PPDI14_WIDTH (1U) 7105 #define SIUL2_PGPDI3_PPDI14(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI3_PPDI14_SHIFT)) & SIUL2_PGPDI3_PPDI14_MASK) 7106 7107 #define SIUL2_PGPDI3_PPDI15_MASK (0x8000U) 7108 #define SIUL2_PGPDI3_PPDI15_SHIFT (15U) 7109 #define SIUL2_PGPDI3_PPDI15_WIDTH (1U) 7110 #define SIUL2_PGPDI3_PPDI15(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI3_PPDI15_SHIFT)) & SIUL2_PGPDI3_PPDI15_MASK) 7111 /*! @} */ 7112 7113 /*! @name PGPDI2 - SIUL2 Parallel GPIO Pad Data In Register */ 7114 /*! @{ */ 7115 7116 #define SIUL2_PGPDI2_PPDI0_MASK (0x1U) 7117 #define SIUL2_PGPDI2_PPDI0_SHIFT (0U) 7118 #define SIUL2_PGPDI2_PPDI0_WIDTH (1U) 7119 #define SIUL2_PGPDI2_PPDI0(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI2_PPDI0_SHIFT)) & SIUL2_PGPDI2_PPDI0_MASK) 7120 7121 #define SIUL2_PGPDI2_PPDI1_MASK (0x2U) 7122 #define SIUL2_PGPDI2_PPDI1_SHIFT (1U) 7123 #define SIUL2_PGPDI2_PPDI1_WIDTH (1U) 7124 #define SIUL2_PGPDI2_PPDI1(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI2_PPDI1_SHIFT)) & SIUL2_PGPDI2_PPDI1_MASK) 7125 7126 #define SIUL2_PGPDI2_PPDI2_MASK (0x4U) 7127 #define SIUL2_PGPDI2_PPDI2_SHIFT (2U) 7128 #define SIUL2_PGPDI2_PPDI2_WIDTH (1U) 7129 #define SIUL2_PGPDI2_PPDI2(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI2_PPDI2_SHIFT)) & SIUL2_PGPDI2_PPDI2_MASK) 7130 7131 #define SIUL2_PGPDI2_PPDI3_MASK (0x8U) 7132 #define SIUL2_PGPDI2_PPDI3_SHIFT (3U) 7133 #define SIUL2_PGPDI2_PPDI3_WIDTH (1U) 7134 #define SIUL2_PGPDI2_PPDI3(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI2_PPDI3_SHIFT)) & SIUL2_PGPDI2_PPDI3_MASK) 7135 7136 #define SIUL2_PGPDI2_PPDI4_MASK (0x10U) 7137 #define SIUL2_PGPDI2_PPDI4_SHIFT (4U) 7138 #define SIUL2_PGPDI2_PPDI4_WIDTH (1U) 7139 #define SIUL2_PGPDI2_PPDI4(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI2_PPDI4_SHIFT)) & SIUL2_PGPDI2_PPDI4_MASK) 7140 7141 #define SIUL2_PGPDI2_PPDI5_MASK (0x20U) 7142 #define SIUL2_PGPDI2_PPDI5_SHIFT (5U) 7143 #define SIUL2_PGPDI2_PPDI5_WIDTH (1U) 7144 #define SIUL2_PGPDI2_PPDI5(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI2_PPDI5_SHIFT)) & SIUL2_PGPDI2_PPDI5_MASK) 7145 7146 #define SIUL2_PGPDI2_PPDI6_MASK (0x40U) 7147 #define SIUL2_PGPDI2_PPDI6_SHIFT (6U) 7148 #define SIUL2_PGPDI2_PPDI6_WIDTH (1U) 7149 #define SIUL2_PGPDI2_PPDI6(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI2_PPDI6_SHIFT)) & SIUL2_PGPDI2_PPDI6_MASK) 7150 7151 #define SIUL2_PGPDI2_PPDI7_MASK (0x80U) 7152 #define SIUL2_PGPDI2_PPDI7_SHIFT (7U) 7153 #define SIUL2_PGPDI2_PPDI7_WIDTH (1U) 7154 #define SIUL2_PGPDI2_PPDI7(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI2_PPDI7_SHIFT)) & SIUL2_PGPDI2_PPDI7_MASK) 7155 7156 #define SIUL2_PGPDI2_PPDI10_MASK (0x400U) 7157 #define SIUL2_PGPDI2_PPDI10_SHIFT (10U) 7158 #define SIUL2_PGPDI2_PPDI10_WIDTH (1U) 7159 #define SIUL2_PGPDI2_PPDI10(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI2_PPDI10_SHIFT)) & SIUL2_PGPDI2_PPDI10_MASK) 7160 7161 #define SIUL2_PGPDI2_PPDI11_MASK (0x800U) 7162 #define SIUL2_PGPDI2_PPDI11_SHIFT (11U) 7163 #define SIUL2_PGPDI2_PPDI11_WIDTH (1U) 7164 #define SIUL2_PGPDI2_PPDI11(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI2_PPDI11_SHIFT)) & SIUL2_PGPDI2_PPDI11_MASK) 7165 7166 #define SIUL2_PGPDI2_PPDI12_MASK (0x1000U) 7167 #define SIUL2_PGPDI2_PPDI12_SHIFT (12U) 7168 #define SIUL2_PGPDI2_PPDI12_WIDTH (1U) 7169 #define SIUL2_PGPDI2_PPDI12(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI2_PPDI12_SHIFT)) & SIUL2_PGPDI2_PPDI12_MASK) 7170 7171 #define SIUL2_PGPDI2_PPDI13_MASK (0x2000U) 7172 #define SIUL2_PGPDI2_PPDI13_SHIFT (13U) 7173 #define SIUL2_PGPDI2_PPDI13_WIDTH (1U) 7174 #define SIUL2_PGPDI2_PPDI13(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI2_PPDI13_SHIFT)) & SIUL2_PGPDI2_PPDI13_MASK) 7175 7176 #define SIUL2_PGPDI2_PPDI14_MASK (0x4000U) 7177 #define SIUL2_PGPDI2_PPDI14_SHIFT (14U) 7178 #define SIUL2_PGPDI2_PPDI14_WIDTH (1U) 7179 #define SIUL2_PGPDI2_PPDI14(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI2_PPDI14_SHIFT)) & SIUL2_PGPDI2_PPDI14_MASK) 7180 7181 #define SIUL2_PGPDI2_PPDI15_MASK (0x8000U) 7182 #define SIUL2_PGPDI2_PPDI15_SHIFT (15U) 7183 #define SIUL2_PGPDI2_PPDI15_WIDTH (1U) 7184 #define SIUL2_PGPDI2_PPDI15(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI2_PPDI15_SHIFT)) & SIUL2_PGPDI2_PPDI15_MASK) 7185 /*! @} */ 7186 7187 /*! @name PGPDI5 - SIUL2 Parallel GPIO Pad Data In Register */ 7188 /*! @{ */ 7189 7190 #define SIUL2_PGPDI5_PPDI0_MASK (0x1U) 7191 #define SIUL2_PGPDI5_PPDI0_SHIFT (0U) 7192 #define SIUL2_PGPDI5_PPDI0_WIDTH (1U) 7193 #define SIUL2_PGPDI5_PPDI0(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI5_PPDI0_SHIFT)) & SIUL2_PGPDI5_PPDI0_MASK) 7194 7195 #define SIUL2_PGPDI5_PPDI1_MASK (0x2U) 7196 #define SIUL2_PGPDI5_PPDI1_SHIFT (1U) 7197 #define SIUL2_PGPDI5_PPDI1_WIDTH (1U) 7198 #define SIUL2_PGPDI5_PPDI1(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI5_PPDI1_SHIFT)) & SIUL2_PGPDI5_PPDI1_MASK) 7199 7200 #define SIUL2_PGPDI5_PPDI2_MASK (0x4U) 7201 #define SIUL2_PGPDI5_PPDI2_SHIFT (2U) 7202 #define SIUL2_PGPDI5_PPDI2_WIDTH (1U) 7203 #define SIUL2_PGPDI5_PPDI2(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI5_PPDI2_SHIFT)) & SIUL2_PGPDI5_PPDI2_MASK) 7204 7205 #define SIUL2_PGPDI5_PPDI3_MASK (0x8U) 7206 #define SIUL2_PGPDI5_PPDI3_SHIFT (3U) 7207 #define SIUL2_PGPDI5_PPDI3_WIDTH (1U) 7208 #define SIUL2_PGPDI5_PPDI3(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI5_PPDI3_SHIFT)) & SIUL2_PGPDI5_PPDI3_MASK) 7209 7210 #define SIUL2_PGPDI5_PPDI4_MASK (0x10U) 7211 #define SIUL2_PGPDI5_PPDI4_SHIFT (4U) 7212 #define SIUL2_PGPDI5_PPDI4_WIDTH (1U) 7213 #define SIUL2_PGPDI5_PPDI4(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI5_PPDI4_SHIFT)) & SIUL2_PGPDI5_PPDI4_MASK) 7214 7215 #define SIUL2_PGPDI5_PPDI5_MASK (0x20U) 7216 #define SIUL2_PGPDI5_PPDI5_SHIFT (5U) 7217 #define SIUL2_PGPDI5_PPDI5_WIDTH (1U) 7218 #define SIUL2_PGPDI5_PPDI5(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI5_PPDI5_SHIFT)) & SIUL2_PGPDI5_PPDI5_MASK) 7219 7220 #define SIUL2_PGPDI5_PPDI6_MASK (0x40U) 7221 #define SIUL2_PGPDI5_PPDI6_SHIFT (6U) 7222 #define SIUL2_PGPDI5_PPDI6_WIDTH (1U) 7223 #define SIUL2_PGPDI5_PPDI6(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI5_PPDI6_SHIFT)) & SIUL2_PGPDI5_PPDI6_MASK) 7224 7225 #define SIUL2_PGPDI5_PPDI7_MASK (0x80U) 7226 #define SIUL2_PGPDI5_PPDI7_SHIFT (7U) 7227 #define SIUL2_PGPDI5_PPDI7_WIDTH (1U) 7228 #define SIUL2_PGPDI5_PPDI7(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI5_PPDI7_SHIFT)) & SIUL2_PGPDI5_PPDI7_MASK) 7229 7230 #define SIUL2_PGPDI5_PPDI8_MASK (0x100U) 7231 #define SIUL2_PGPDI5_PPDI8_SHIFT (8U) 7232 #define SIUL2_PGPDI5_PPDI8_WIDTH (1U) 7233 #define SIUL2_PGPDI5_PPDI8(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI5_PPDI8_SHIFT)) & SIUL2_PGPDI5_PPDI8_MASK) 7234 7235 #define SIUL2_PGPDI5_PPDI9_MASK (0x200U) 7236 #define SIUL2_PGPDI5_PPDI9_SHIFT (9U) 7237 #define SIUL2_PGPDI5_PPDI9_WIDTH (1U) 7238 #define SIUL2_PGPDI5_PPDI9(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI5_PPDI9_SHIFT)) & SIUL2_PGPDI5_PPDI9_MASK) 7239 7240 #define SIUL2_PGPDI5_PPDI10_MASK (0x400U) 7241 #define SIUL2_PGPDI5_PPDI10_SHIFT (10U) 7242 #define SIUL2_PGPDI5_PPDI10_WIDTH (1U) 7243 #define SIUL2_PGPDI5_PPDI10(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI5_PPDI10_SHIFT)) & SIUL2_PGPDI5_PPDI10_MASK) 7244 7245 #define SIUL2_PGPDI5_PPDI11_MASK (0x800U) 7246 #define SIUL2_PGPDI5_PPDI11_SHIFT (11U) 7247 #define SIUL2_PGPDI5_PPDI11_WIDTH (1U) 7248 #define SIUL2_PGPDI5_PPDI11(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI5_PPDI11_SHIFT)) & SIUL2_PGPDI5_PPDI11_MASK) 7249 7250 #define SIUL2_PGPDI5_PPDI12_MASK (0x1000U) 7251 #define SIUL2_PGPDI5_PPDI12_SHIFT (12U) 7252 #define SIUL2_PGPDI5_PPDI12_WIDTH (1U) 7253 #define SIUL2_PGPDI5_PPDI12(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI5_PPDI12_SHIFT)) & SIUL2_PGPDI5_PPDI12_MASK) 7254 7255 #define SIUL2_PGPDI5_PPDI13_MASK (0x2000U) 7256 #define SIUL2_PGPDI5_PPDI13_SHIFT (13U) 7257 #define SIUL2_PGPDI5_PPDI13_WIDTH (1U) 7258 #define SIUL2_PGPDI5_PPDI13(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI5_PPDI13_SHIFT)) & SIUL2_PGPDI5_PPDI13_MASK) 7259 7260 #define SIUL2_PGPDI5_PPDI14_MASK (0x4000U) 7261 #define SIUL2_PGPDI5_PPDI14_SHIFT (14U) 7262 #define SIUL2_PGPDI5_PPDI14_WIDTH (1U) 7263 #define SIUL2_PGPDI5_PPDI14(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI5_PPDI14_SHIFT)) & SIUL2_PGPDI5_PPDI14_MASK) 7264 7265 #define SIUL2_PGPDI5_PPDI15_MASK (0x8000U) 7266 #define SIUL2_PGPDI5_PPDI15_SHIFT (15U) 7267 #define SIUL2_PGPDI5_PPDI15_WIDTH (1U) 7268 #define SIUL2_PGPDI5_PPDI15(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI5_PPDI15_SHIFT)) & SIUL2_PGPDI5_PPDI15_MASK) 7269 /*! @} */ 7270 7271 /*! @name PGPDI4 - SIUL2 Parallel GPIO Pad Data In Register */ 7272 /*! @{ */ 7273 7274 #define SIUL2_PGPDI4_PPDI0_MASK (0x1U) 7275 #define SIUL2_PGPDI4_PPDI0_SHIFT (0U) 7276 #define SIUL2_PGPDI4_PPDI0_WIDTH (1U) 7277 #define SIUL2_PGPDI4_PPDI0(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI4_PPDI0_SHIFT)) & SIUL2_PGPDI4_PPDI0_MASK) 7278 7279 #define SIUL2_PGPDI4_PPDI1_MASK (0x2U) 7280 #define SIUL2_PGPDI4_PPDI1_SHIFT (1U) 7281 #define SIUL2_PGPDI4_PPDI1_WIDTH (1U) 7282 #define SIUL2_PGPDI4_PPDI1(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI4_PPDI1_SHIFT)) & SIUL2_PGPDI4_PPDI1_MASK) 7283 7284 #define SIUL2_PGPDI4_PPDI2_MASK (0x4U) 7285 #define SIUL2_PGPDI4_PPDI2_SHIFT (2U) 7286 #define SIUL2_PGPDI4_PPDI2_WIDTH (1U) 7287 #define SIUL2_PGPDI4_PPDI2(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI4_PPDI2_SHIFT)) & SIUL2_PGPDI4_PPDI2_MASK) 7288 7289 #define SIUL2_PGPDI4_PPDI3_MASK (0x8U) 7290 #define SIUL2_PGPDI4_PPDI3_SHIFT (3U) 7291 #define SIUL2_PGPDI4_PPDI3_WIDTH (1U) 7292 #define SIUL2_PGPDI4_PPDI3(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI4_PPDI3_SHIFT)) & SIUL2_PGPDI4_PPDI3_MASK) 7293 7294 #define SIUL2_PGPDI4_PPDI4_MASK (0x10U) 7295 #define SIUL2_PGPDI4_PPDI4_SHIFT (4U) 7296 #define SIUL2_PGPDI4_PPDI4_WIDTH (1U) 7297 #define SIUL2_PGPDI4_PPDI4(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI4_PPDI4_SHIFT)) & SIUL2_PGPDI4_PPDI4_MASK) 7298 7299 #define SIUL2_PGPDI4_PPDI5_MASK (0x20U) 7300 #define SIUL2_PGPDI4_PPDI5_SHIFT (5U) 7301 #define SIUL2_PGPDI4_PPDI5_WIDTH (1U) 7302 #define SIUL2_PGPDI4_PPDI5(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI4_PPDI5_SHIFT)) & SIUL2_PGPDI4_PPDI5_MASK) 7303 7304 #define SIUL2_PGPDI4_PPDI6_MASK (0x40U) 7305 #define SIUL2_PGPDI4_PPDI6_SHIFT (6U) 7306 #define SIUL2_PGPDI4_PPDI6_WIDTH (1U) 7307 #define SIUL2_PGPDI4_PPDI6(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI4_PPDI6_SHIFT)) & SIUL2_PGPDI4_PPDI6_MASK) 7308 7309 #define SIUL2_PGPDI4_PPDI7_MASK (0x80U) 7310 #define SIUL2_PGPDI4_PPDI7_SHIFT (7U) 7311 #define SIUL2_PGPDI4_PPDI7_WIDTH (1U) 7312 #define SIUL2_PGPDI4_PPDI7(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI4_PPDI7_SHIFT)) & SIUL2_PGPDI4_PPDI7_MASK) 7313 7314 #define SIUL2_PGPDI4_PPDI8_MASK (0x100U) 7315 #define SIUL2_PGPDI4_PPDI8_SHIFT (8U) 7316 #define SIUL2_PGPDI4_PPDI8_WIDTH (1U) 7317 #define SIUL2_PGPDI4_PPDI8(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI4_PPDI8_SHIFT)) & SIUL2_PGPDI4_PPDI8_MASK) 7318 7319 #define SIUL2_PGPDI4_PPDI9_MASK (0x200U) 7320 #define SIUL2_PGPDI4_PPDI9_SHIFT (9U) 7321 #define SIUL2_PGPDI4_PPDI9_WIDTH (1U) 7322 #define SIUL2_PGPDI4_PPDI9(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI4_PPDI9_SHIFT)) & SIUL2_PGPDI4_PPDI9_MASK) 7323 7324 #define SIUL2_PGPDI4_PPDI10_MASK (0x400U) 7325 #define SIUL2_PGPDI4_PPDI10_SHIFT (10U) 7326 #define SIUL2_PGPDI4_PPDI10_WIDTH (1U) 7327 #define SIUL2_PGPDI4_PPDI10(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI4_PPDI10_SHIFT)) & SIUL2_PGPDI4_PPDI10_MASK) 7328 7329 #define SIUL2_PGPDI4_PPDI11_MASK (0x800U) 7330 #define SIUL2_PGPDI4_PPDI11_SHIFT (11U) 7331 #define SIUL2_PGPDI4_PPDI11_WIDTH (1U) 7332 #define SIUL2_PGPDI4_PPDI11(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI4_PPDI11_SHIFT)) & SIUL2_PGPDI4_PPDI11_MASK) 7333 7334 #define SIUL2_PGPDI4_PPDI12_MASK (0x1000U) 7335 #define SIUL2_PGPDI4_PPDI12_SHIFT (12U) 7336 #define SIUL2_PGPDI4_PPDI12_WIDTH (1U) 7337 #define SIUL2_PGPDI4_PPDI12(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI4_PPDI12_SHIFT)) & SIUL2_PGPDI4_PPDI12_MASK) 7338 7339 #define SIUL2_PGPDI4_PPDI13_MASK (0x2000U) 7340 #define SIUL2_PGPDI4_PPDI13_SHIFT (13U) 7341 #define SIUL2_PGPDI4_PPDI13_WIDTH (1U) 7342 #define SIUL2_PGPDI4_PPDI13(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI4_PPDI13_SHIFT)) & SIUL2_PGPDI4_PPDI13_MASK) 7343 7344 #define SIUL2_PGPDI4_PPDI14_MASK (0x4000U) 7345 #define SIUL2_PGPDI4_PPDI14_SHIFT (14U) 7346 #define SIUL2_PGPDI4_PPDI14_WIDTH (1U) 7347 #define SIUL2_PGPDI4_PPDI14(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI4_PPDI14_SHIFT)) & SIUL2_PGPDI4_PPDI14_MASK) 7348 7349 #define SIUL2_PGPDI4_PPDI15_MASK (0x8000U) 7350 #define SIUL2_PGPDI4_PPDI15_SHIFT (15U) 7351 #define SIUL2_PGPDI4_PPDI15_WIDTH (1U) 7352 #define SIUL2_PGPDI4_PPDI15(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI4_PPDI15_SHIFT)) & SIUL2_PGPDI4_PPDI15_MASK) 7353 /*! @} */ 7354 7355 /*! @name PGPDI7 - SIUL2 Parallel GPIO Pad Data In Register */ 7356 /*! @{ */ 7357 7358 #define SIUL2_PGPDI7_PPDI0_MASK (0x1U) 7359 #define SIUL2_PGPDI7_PPDI0_SHIFT (0U) 7360 #define SIUL2_PGPDI7_PPDI0_WIDTH (1U) 7361 #define SIUL2_PGPDI7_PPDI0(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI7_PPDI0_SHIFT)) & SIUL2_PGPDI7_PPDI0_MASK) 7362 7363 #define SIUL2_PGPDI7_PPDI1_MASK (0x2U) 7364 #define SIUL2_PGPDI7_PPDI1_SHIFT (1U) 7365 #define SIUL2_PGPDI7_PPDI1_WIDTH (1U) 7366 #define SIUL2_PGPDI7_PPDI1(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI7_PPDI1_SHIFT)) & SIUL2_PGPDI7_PPDI1_MASK) 7367 7368 #define SIUL2_PGPDI7_PPDI2_MASK (0x4U) 7369 #define SIUL2_PGPDI7_PPDI2_SHIFT (2U) 7370 #define SIUL2_PGPDI7_PPDI2_WIDTH (1U) 7371 #define SIUL2_PGPDI7_PPDI2(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI7_PPDI2_SHIFT)) & SIUL2_PGPDI7_PPDI2_MASK) 7372 7373 #define SIUL2_PGPDI7_PPDI3_MASK (0x8U) 7374 #define SIUL2_PGPDI7_PPDI3_SHIFT (3U) 7375 #define SIUL2_PGPDI7_PPDI3_WIDTH (1U) 7376 #define SIUL2_PGPDI7_PPDI3(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI7_PPDI3_SHIFT)) & SIUL2_PGPDI7_PPDI3_MASK) 7377 7378 #define SIUL2_PGPDI7_PPDI4_MASK (0x10U) 7379 #define SIUL2_PGPDI7_PPDI4_SHIFT (4U) 7380 #define SIUL2_PGPDI7_PPDI4_WIDTH (1U) 7381 #define SIUL2_PGPDI7_PPDI4(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI7_PPDI4_SHIFT)) & SIUL2_PGPDI7_PPDI4_MASK) 7382 7383 #define SIUL2_PGPDI7_PPDI5_MASK (0x20U) 7384 #define SIUL2_PGPDI7_PPDI5_SHIFT (5U) 7385 #define SIUL2_PGPDI7_PPDI5_WIDTH (1U) 7386 #define SIUL2_PGPDI7_PPDI5(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI7_PPDI5_SHIFT)) & SIUL2_PGPDI7_PPDI5_MASK) 7387 7388 #define SIUL2_PGPDI7_PPDI6_MASK (0x40U) 7389 #define SIUL2_PGPDI7_PPDI6_SHIFT (6U) 7390 #define SIUL2_PGPDI7_PPDI6_WIDTH (1U) 7391 #define SIUL2_PGPDI7_PPDI6(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI7_PPDI6_SHIFT)) & SIUL2_PGPDI7_PPDI6_MASK) 7392 7393 #define SIUL2_PGPDI7_PPDI7_MASK (0x80U) 7394 #define SIUL2_PGPDI7_PPDI7_SHIFT (7U) 7395 #define SIUL2_PGPDI7_PPDI7_WIDTH (1U) 7396 #define SIUL2_PGPDI7_PPDI7(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI7_PPDI7_SHIFT)) & SIUL2_PGPDI7_PPDI7_MASK) 7397 7398 #define SIUL2_PGPDI7_PPDI8_MASK (0x100U) 7399 #define SIUL2_PGPDI7_PPDI8_SHIFT (8U) 7400 #define SIUL2_PGPDI7_PPDI8_WIDTH (1U) 7401 #define SIUL2_PGPDI7_PPDI8(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI7_PPDI8_SHIFT)) & SIUL2_PGPDI7_PPDI8_MASK) 7402 7403 #define SIUL2_PGPDI7_PPDI9_MASK (0x200U) 7404 #define SIUL2_PGPDI7_PPDI9_SHIFT (9U) 7405 #define SIUL2_PGPDI7_PPDI9_WIDTH (1U) 7406 #define SIUL2_PGPDI7_PPDI9(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI7_PPDI9_SHIFT)) & SIUL2_PGPDI7_PPDI9_MASK) 7407 7408 #define SIUL2_PGPDI7_PPDI10_MASK (0x400U) 7409 #define SIUL2_PGPDI7_PPDI10_SHIFT (10U) 7410 #define SIUL2_PGPDI7_PPDI10_WIDTH (1U) 7411 #define SIUL2_PGPDI7_PPDI10(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI7_PPDI10_SHIFT)) & SIUL2_PGPDI7_PPDI10_MASK) 7412 7413 #define SIUL2_PGPDI7_PPDI11_MASK (0x800U) 7414 #define SIUL2_PGPDI7_PPDI11_SHIFT (11U) 7415 #define SIUL2_PGPDI7_PPDI11_WIDTH (1U) 7416 #define SIUL2_PGPDI7_PPDI11(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI7_PPDI11_SHIFT)) & SIUL2_PGPDI7_PPDI11_MASK) 7417 7418 #define SIUL2_PGPDI7_PPDI12_MASK (0x1000U) 7419 #define SIUL2_PGPDI7_PPDI12_SHIFT (12U) 7420 #define SIUL2_PGPDI7_PPDI12_WIDTH (1U) 7421 #define SIUL2_PGPDI7_PPDI12(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI7_PPDI12_SHIFT)) & SIUL2_PGPDI7_PPDI12_MASK) 7422 7423 #define SIUL2_PGPDI7_PPDI13_MASK (0x2000U) 7424 #define SIUL2_PGPDI7_PPDI13_SHIFT (13U) 7425 #define SIUL2_PGPDI7_PPDI13_WIDTH (1U) 7426 #define SIUL2_PGPDI7_PPDI13(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI7_PPDI13_SHIFT)) & SIUL2_PGPDI7_PPDI13_MASK) 7427 7428 #define SIUL2_PGPDI7_PPDI14_MASK (0x4000U) 7429 #define SIUL2_PGPDI7_PPDI14_SHIFT (14U) 7430 #define SIUL2_PGPDI7_PPDI14_WIDTH (1U) 7431 #define SIUL2_PGPDI7_PPDI14(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI7_PPDI14_SHIFT)) & SIUL2_PGPDI7_PPDI14_MASK) 7432 7433 #define SIUL2_PGPDI7_PPDI15_MASK (0x8000U) 7434 #define SIUL2_PGPDI7_PPDI15_SHIFT (15U) 7435 #define SIUL2_PGPDI7_PPDI15_WIDTH (1U) 7436 #define SIUL2_PGPDI7_PPDI15(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI7_PPDI15_SHIFT)) & SIUL2_PGPDI7_PPDI15_MASK) 7437 /*! @} */ 7438 7439 /*! @name PGPDI6 - SIUL2 Parallel GPIO Pad Data In Register */ 7440 /*! @{ */ 7441 7442 #define SIUL2_PGPDI6_PPDI0_MASK (0x1U) 7443 #define SIUL2_PGPDI6_PPDI0_SHIFT (0U) 7444 #define SIUL2_PGPDI6_PPDI0_WIDTH (1U) 7445 #define SIUL2_PGPDI6_PPDI0(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI6_PPDI0_SHIFT)) & SIUL2_PGPDI6_PPDI0_MASK) 7446 7447 #define SIUL2_PGPDI6_PPDI1_MASK (0x2U) 7448 #define SIUL2_PGPDI6_PPDI1_SHIFT (1U) 7449 #define SIUL2_PGPDI6_PPDI1_WIDTH (1U) 7450 #define SIUL2_PGPDI6_PPDI1(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI6_PPDI1_SHIFT)) & SIUL2_PGPDI6_PPDI1_MASK) 7451 7452 #define SIUL2_PGPDI6_PPDI2_MASK (0x4U) 7453 #define SIUL2_PGPDI6_PPDI2_SHIFT (2U) 7454 #define SIUL2_PGPDI6_PPDI2_WIDTH (1U) 7455 #define SIUL2_PGPDI6_PPDI2(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI6_PPDI2_SHIFT)) & SIUL2_PGPDI6_PPDI2_MASK) 7456 7457 #define SIUL2_PGPDI6_PPDI3_MASK (0x8U) 7458 #define SIUL2_PGPDI6_PPDI3_SHIFT (3U) 7459 #define SIUL2_PGPDI6_PPDI3_WIDTH (1U) 7460 #define SIUL2_PGPDI6_PPDI3(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI6_PPDI3_SHIFT)) & SIUL2_PGPDI6_PPDI3_MASK) 7461 7462 #define SIUL2_PGPDI6_PPDI4_MASK (0x10U) 7463 #define SIUL2_PGPDI6_PPDI4_SHIFT (4U) 7464 #define SIUL2_PGPDI6_PPDI4_WIDTH (1U) 7465 #define SIUL2_PGPDI6_PPDI4(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI6_PPDI4_SHIFT)) & SIUL2_PGPDI6_PPDI4_MASK) 7466 7467 #define SIUL2_PGPDI6_PPDI5_MASK (0x20U) 7468 #define SIUL2_PGPDI6_PPDI5_SHIFT (5U) 7469 #define SIUL2_PGPDI6_PPDI5_WIDTH (1U) 7470 #define SIUL2_PGPDI6_PPDI5(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI6_PPDI5_SHIFT)) & SIUL2_PGPDI6_PPDI5_MASK) 7471 7472 #define SIUL2_PGPDI6_PPDI6_MASK (0x40U) 7473 #define SIUL2_PGPDI6_PPDI6_SHIFT (6U) 7474 #define SIUL2_PGPDI6_PPDI6_WIDTH (1U) 7475 #define SIUL2_PGPDI6_PPDI6(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI6_PPDI6_SHIFT)) & SIUL2_PGPDI6_PPDI6_MASK) 7476 7477 #define SIUL2_PGPDI6_PPDI7_MASK (0x80U) 7478 #define SIUL2_PGPDI6_PPDI7_SHIFT (7U) 7479 #define SIUL2_PGPDI6_PPDI7_WIDTH (1U) 7480 #define SIUL2_PGPDI6_PPDI7(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI6_PPDI7_SHIFT)) & SIUL2_PGPDI6_PPDI7_MASK) 7481 7482 #define SIUL2_PGPDI6_PPDI8_MASK (0x100U) 7483 #define SIUL2_PGPDI6_PPDI8_SHIFT (8U) 7484 #define SIUL2_PGPDI6_PPDI8_WIDTH (1U) 7485 #define SIUL2_PGPDI6_PPDI8(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI6_PPDI8_SHIFT)) & SIUL2_PGPDI6_PPDI8_MASK) 7486 7487 #define SIUL2_PGPDI6_PPDI9_MASK (0x200U) 7488 #define SIUL2_PGPDI6_PPDI9_SHIFT (9U) 7489 #define SIUL2_PGPDI6_PPDI9_WIDTH (1U) 7490 #define SIUL2_PGPDI6_PPDI9(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI6_PPDI9_SHIFT)) & SIUL2_PGPDI6_PPDI9_MASK) 7491 7492 #define SIUL2_PGPDI6_PPDI10_MASK (0x400U) 7493 #define SIUL2_PGPDI6_PPDI10_SHIFT (10U) 7494 #define SIUL2_PGPDI6_PPDI10_WIDTH (1U) 7495 #define SIUL2_PGPDI6_PPDI10(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI6_PPDI10_SHIFT)) & SIUL2_PGPDI6_PPDI10_MASK) 7496 7497 #define SIUL2_PGPDI6_PPDI11_MASK (0x800U) 7498 #define SIUL2_PGPDI6_PPDI11_SHIFT (11U) 7499 #define SIUL2_PGPDI6_PPDI11_WIDTH (1U) 7500 #define SIUL2_PGPDI6_PPDI11(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI6_PPDI11_SHIFT)) & SIUL2_PGPDI6_PPDI11_MASK) 7501 7502 #define SIUL2_PGPDI6_PPDI12_MASK (0x1000U) 7503 #define SIUL2_PGPDI6_PPDI12_SHIFT (12U) 7504 #define SIUL2_PGPDI6_PPDI12_WIDTH (1U) 7505 #define SIUL2_PGPDI6_PPDI12(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI6_PPDI12_SHIFT)) & SIUL2_PGPDI6_PPDI12_MASK) 7506 7507 #define SIUL2_PGPDI6_PPDI13_MASK (0x2000U) 7508 #define SIUL2_PGPDI6_PPDI13_SHIFT (13U) 7509 #define SIUL2_PGPDI6_PPDI13_WIDTH (1U) 7510 #define SIUL2_PGPDI6_PPDI13(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI6_PPDI13_SHIFT)) & SIUL2_PGPDI6_PPDI13_MASK) 7511 7512 #define SIUL2_PGPDI6_PPDI14_MASK (0x4000U) 7513 #define SIUL2_PGPDI6_PPDI14_SHIFT (14U) 7514 #define SIUL2_PGPDI6_PPDI14_WIDTH (1U) 7515 #define SIUL2_PGPDI6_PPDI14(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI6_PPDI14_SHIFT)) & SIUL2_PGPDI6_PPDI14_MASK) 7516 7517 #define SIUL2_PGPDI6_PPDI15_MASK (0x8000U) 7518 #define SIUL2_PGPDI6_PPDI15_SHIFT (15U) 7519 #define SIUL2_PGPDI6_PPDI15_WIDTH (1U) 7520 #define SIUL2_PGPDI6_PPDI15(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI6_PPDI15_SHIFT)) & SIUL2_PGPDI6_PPDI15_MASK) 7521 /*! @} */ 7522 7523 /*! @name PGPDI9 - SIUL2 Parallel GPIO Pad Data In Register */ 7524 /*! @{ */ 7525 7526 #define SIUL2_PGPDI9_PPDI0_MASK (0x1U) 7527 #define SIUL2_PGPDI9_PPDI0_SHIFT (0U) 7528 #define SIUL2_PGPDI9_PPDI0_WIDTH (1U) 7529 #define SIUL2_PGPDI9_PPDI0(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI9_PPDI0_SHIFT)) & SIUL2_PGPDI9_PPDI0_MASK) 7530 7531 #define SIUL2_PGPDI9_PPDI1_MASK (0x2U) 7532 #define SIUL2_PGPDI9_PPDI1_SHIFT (1U) 7533 #define SIUL2_PGPDI9_PPDI1_WIDTH (1U) 7534 #define SIUL2_PGPDI9_PPDI1(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI9_PPDI1_SHIFT)) & SIUL2_PGPDI9_PPDI1_MASK) 7535 7536 #define SIUL2_PGPDI9_PPDI2_MASK (0x4U) 7537 #define SIUL2_PGPDI9_PPDI2_SHIFT (2U) 7538 #define SIUL2_PGPDI9_PPDI2_WIDTH (1U) 7539 #define SIUL2_PGPDI9_PPDI2(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI9_PPDI2_SHIFT)) & SIUL2_PGPDI9_PPDI2_MASK) 7540 7541 #define SIUL2_PGPDI9_PPDI3_MASK (0x8U) 7542 #define SIUL2_PGPDI9_PPDI3_SHIFT (3U) 7543 #define SIUL2_PGPDI9_PPDI3_WIDTH (1U) 7544 #define SIUL2_PGPDI9_PPDI3(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI9_PPDI3_SHIFT)) & SIUL2_PGPDI9_PPDI3_MASK) 7545 7546 #define SIUL2_PGPDI9_PPDI4_MASK (0x10U) 7547 #define SIUL2_PGPDI9_PPDI4_SHIFT (4U) 7548 #define SIUL2_PGPDI9_PPDI4_WIDTH (1U) 7549 #define SIUL2_PGPDI9_PPDI4(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI9_PPDI4_SHIFT)) & SIUL2_PGPDI9_PPDI4_MASK) 7550 7551 #define SIUL2_PGPDI9_PPDI5_MASK (0x20U) 7552 #define SIUL2_PGPDI9_PPDI5_SHIFT (5U) 7553 #define SIUL2_PGPDI9_PPDI5_WIDTH (1U) 7554 #define SIUL2_PGPDI9_PPDI5(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI9_PPDI5_SHIFT)) & SIUL2_PGPDI9_PPDI5_MASK) 7555 7556 #define SIUL2_PGPDI9_PPDI6_MASK (0x40U) 7557 #define SIUL2_PGPDI9_PPDI6_SHIFT (6U) 7558 #define SIUL2_PGPDI9_PPDI6_WIDTH (1U) 7559 #define SIUL2_PGPDI9_PPDI6(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI9_PPDI6_SHIFT)) & SIUL2_PGPDI9_PPDI6_MASK) 7560 7561 #define SIUL2_PGPDI9_PPDI7_MASK (0x80U) 7562 #define SIUL2_PGPDI9_PPDI7_SHIFT (7U) 7563 #define SIUL2_PGPDI9_PPDI7_WIDTH (1U) 7564 #define SIUL2_PGPDI9_PPDI7(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI9_PPDI7_SHIFT)) & SIUL2_PGPDI9_PPDI7_MASK) 7565 7566 #define SIUL2_PGPDI9_PPDI8_MASK (0x100U) 7567 #define SIUL2_PGPDI9_PPDI8_SHIFT (8U) 7568 #define SIUL2_PGPDI9_PPDI8_WIDTH (1U) 7569 #define SIUL2_PGPDI9_PPDI8(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI9_PPDI8_SHIFT)) & SIUL2_PGPDI9_PPDI8_MASK) 7570 7571 #define SIUL2_PGPDI9_PPDI9_MASK (0x200U) 7572 #define SIUL2_PGPDI9_PPDI9_SHIFT (9U) 7573 #define SIUL2_PGPDI9_PPDI9_WIDTH (1U) 7574 #define SIUL2_PGPDI9_PPDI9(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI9_PPDI9_SHIFT)) & SIUL2_PGPDI9_PPDI9_MASK) 7575 7576 #define SIUL2_PGPDI9_PPDI10_MASK (0x400U) 7577 #define SIUL2_PGPDI9_PPDI10_SHIFT (10U) 7578 #define SIUL2_PGPDI9_PPDI10_WIDTH (1U) 7579 #define SIUL2_PGPDI9_PPDI10(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI9_PPDI10_SHIFT)) & SIUL2_PGPDI9_PPDI10_MASK) 7580 7581 #define SIUL2_PGPDI9_PPDI11_MASK (0x800U) 7582 #define SIUL2_PGPDI9_PPDI11_SHIFT (11U) 7583 #define SIUL2_PGPDI9_PPDI11_WIDTH (1U) 7584 #define SIUL2_PGPDI9_PPDI11(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI9_PPDI11_SHIFT)) & SIUL2_PGPDI9_PPDI11_MASK) 7585 7586 #define SIUL2_PGPDI9_PPDI12_MASK (0x1000U) 7587 #define SIUL2_PGPDI9_PPDI12_SHIFT (12U) 7588 #define SIUL2_PGPDI9_PPDI12_WIDTH (1U) 7589 #define SIUL2_PGPDI9_PPDI12(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI9_PPDI12_SHIFT)) & SIUL2_PGPDI9_PPDI12_MASK) 7590 7591 #define SIUL2_PGPDI9_PPDI13_MASK (0x2000U) 7592 #define SIUL2_PGPDI9_PPDI13_SHIFT (13U) 7593 #define SIUL2_PGPDI9_PPDI13_WIDTH (1U) 7594 #define SIUL2_PGPDI9_PPDI13(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI9_PPDI13_SHIFT)) & SIUL2_PGPDI9_PPDI13_MASK) 7595 7596 #define SIUL2_PGPDI9_PPDI14_MASK (0x4000U) 7597 #define SIUL2_PGPDI9_PPDI14_SHIFT (14U) 7598 #define SIUL2_PGPDI9_PPDI14_WIDTH (1U) 7599 #define SIUL2_PGPDI9_PPDI14(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI9_PPDI14_SHIFT)) & SIUL2_PGPDI9_PPDI14_MASK) 7600 7601 #define SIUL2_PGPDI9_PPDI15_MASK (0x8000U) 7602 #define SIUL2_PGPDI9_PPDI15_SHIFT (15U) 7603 #define SIUL2_PGPDI9_PPDI15_WIDTH (1U) 7604 #define SIUL2_PGPDI9_PPDI15(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI9_PPDI15_SHIFT)) & SIUL2_PGPDI9_PPDI15_MASK) 7605 /*! @} */ 7606 7607 /*! @name PGPDI8 - SIUL2 Parallel GPIO Pad Data In Register */ 7608 /*! @{ */ 7609 7610 #define SIUL2_PGPDI8_PPDI0_MASK (0x1U) 7611 #define SIUL2_PGPDI8_PPDI0_SHIFT (0U) 7612 #define SIUL2_PGPDI8_PPDI0_WIDTH (1U) 7613 #define SIUL2_PGPDI8_PPDI0(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI8_PPDI0_SHIFT)) & SIUL2_PGPDI8_PPDI0_MASK) 7614 7615 #define SIUL2_PGPDI8_PPDI1_MASK (0x2U) 7616 #define SIUL2_PGPDI8_PPDI1_SHIFT (1U) 7617 #define SIUL2_PGPDI8_PPDI1_WIDTH (1U) 7618 #define SIUL2_PGPDI8_PPDI1(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI8_PPDI1_SHIFT)) & SIUL2_PGPDI8_PPDI1_MASK) 7619 7620 #define SIUL2_PGPDI8_PPDI2_MASK (0x4U) 7621 #define SIUL2_PGPDI8_PPDI2_SHIFT (2U) 7622 #define SIUL2_PGPDI8_PPDI2_WIDTH (1U) 7623 #define SIUL2_PGPDI8_PPDI2(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI8_PPDI2_SHIFT)) & SIUL2_PGPDI8_PPDI2_MASK) 7624 7625 #define SIUL2_PGPDI8_PPDI3_MASK (0x8U) 7626 #define SIUL2_PGPDI8_PPDI3_SHIFT (3U) 7627 #define SIUL2_PGPDI8_PPDI3_WIDTH (1U) 7628 #define SIUL2_PGPDI8_PPDI3(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI8_PPDI3_SHIFT)) & SIUL2_PGPDI8_PPDI3_MASK) 7629 7630 #define SIUL2_PGPDI8_PPDI4_MASK (0x10U) 7631 #define SIUL2_PGPDI8_PPDI4_SHIFT (4U) 7632 #define SIUL2_PGPDI8_PPDI4_WIDTH (1U) 7633 #define SIUL2_PGPDI8_PPDI4(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI8_PPDI4_SHIFT)) & SIUL2_PGPDI8_PPDI4_MASK) 7634 7635 #define SIUL2_PGPDI8_PPDI5_MASK (0x20U) 7636 #define SIUL2_PGPDI8_PPDI5_SHIFT (5U) 7637 #define SIUL2_PGPDI8_PPDI5_WIDTH (1U) 7638 #define SIUL2_PGPDI8_PPDI5(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI8_PPDI5_SHIFT)) & SIUL2_PGPDI8_PPDI5_MASK) 7639 7640 #define SIUL2_PGPDI8_PPDI6_MASK (0x40U) 7641 #define SIUL2_PGPDI8_PPDI6_SHIFT (6U) 7642 #define SIUL2_PGPDI8_PPDI6_WIDTH (1U) 7643 #define SIUL2_PGPDI8_PPDI6(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI8_PPDI6_SHIFT)) & SIUL2_PGPDI8_PPDI6_MASK) 7644 7645 #define SIUL2_PGPDI8_PPDI7_MASK (0x80U) 7646 #define SIUL2_PGPDI8_PPDI7_SHIFT (7U) 7647 #define SIUL2_PGPDI8_PPDI7_WIDTH (1U) 7648 #define SIUL2_PGPDI8_PPDI7(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI8_PPDI7_SHIFT)) & SIUL2_PGPDI8_PPDI7_MASK) 7649 7650 #define SIUL2_PGPDI8_PPDI8_MASK (0x100U) 7651 #define SIUL2_PGPDI8_PPDI8_SHIFT (8U) 7652 #define SIUL2_PGPDI8_PPDI8_WIDTH (1U) 7653 #define SIUL2_PGPDI8_PPDI8(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI8_PPDI8_SHIFT)) & SIUL2_PGPDI8_PPDI8_MASK) 7654 7655 #define SIUL2_PGPDI8_PPDI9_MASK (0x200U) 7656 #define SIUL2_PGPDI8_PPDI9_SHIFT (9U) 7657 #define SIUL2_PGPDI8_PPDI9_WIDTH (1U) 7658 #define SIUL2_PGPDI8_PPDI9(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI8_PPDI9_SHIFT)) & SIUL2_PGPDI8_PPDI9_MASK) 7659 7660 #define SIUL2_PGPDI8_PPDI10_MASK (0x400U) 7661 #define SIUL2_PGPDI8_PPDI10_SHIFT (10U) 7662 #define SIUL2_PGPDI8_PPDI10_WIDTH (1U) 7663 #define SIUL2_PGPDI8_PPDI10(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI8_PPDI10_SHIFT)) & SIUL2_PGPDI8_PPDI10_MASK) 7664 7665 #define SIUL2_PGPDI8_PPDI11_MASK (0x800U) 7666 #define SIUL2_PGPDI8_PPDI11_SHIFT (11U) 7667 #define SIUL2_PGPDI8_PPDI11_WIDTH (1U) 7668 #define SIUL2_PGPDI8_PPDI11(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI8_PPDI11_SHIFT)) & SIUL2_PGPDI8_PPDI11_MASK) 7669 7670 #define SIUL2_PGPDI8_PPDI12_MASK (0x1000U) 7671 #define SIUL2_PGPDI8_PPDI12_SHIFT (12U) 7672 #define SIUL2_PGPDI8_PPDI12_WIDTH (1U) 7673 #define SIUL2_PGPDI8_PPDI12(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI8_PPDI12_SHIFT)) & SIUL2_PGPDI8_PPDI12_MASK) 7674 7675 #define SIUL2_PGPDI8_PPDI13_MASK (0x2000U) 7676 #define SIUL2_PGPDI8_PPDI13_SHIFT (13U) 7677 #define SIUL2_PGPDI8_PPDI13_WIDTH (1U) 7678 #define SIUL2_PGPDI8_PPDI13(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI8_PPDI13_SHIFT)) & SIUL2_PGPDI8_PPDI13_MASK) 7679 7680 #define SIUL2_PGPDI8_PPDI14_MASK (0x4000U) 7681 #define SIUL2_PGPDI8_PPDI14_SHIFT (14U) 7682 #define SIUL2_PGPDI8_PPDI14_WIDTH (1U) 7683 #define SIUL2_PGPDI8_PPDI14(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI8_PPDI14_SHIFT)) & SIUL2_PGPDI8_PPDI14_MASK) 7684 7685 #define SIUL2_PGPDI8_PPDI15_MASK (0x8000U) 7686 #define SIUL2_PGPDI8_PPDI15_SHIFT (15U) 7687 #define SIUL2_PGPDI8_PPDI15_WIDTH (1U) 7688 #define SIUL2_PGPDI8_PPDI15(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI8_PPDI15_SHIFT)) & SIUL2_PGPDI8_PPDI15_MASK) 7689 /*! @} */ 7690 7691 /*! @name PGPDI11 - SIUL2 Parallel GPIO Pad Data In Register */ 7692 /*! @{ */ 7693 7694 #define SIUL2_PGPDI11_PPDI0_MASK (0x1U) 7695 #define SIUL2_PGPDI11_PPDI0_SHIFT (0U) 7696 #define SIUL2_PGPDI11_PPDI0_WIDTH (1U) 7697 #define SIUL2_PGPDI11_PPDI0(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI11_PPDI0_SHIFT)) & SIUL2_PGPDI11_PPDI0_MASK) 7698 7699 #define SIUL2_PGPDI11_PPDI1_MASK (0x2U) 7700 #define SIUL2_PGPDI11_PPDI1_SHIFT (1U) 7701 #define SIUL2_PGPDI11_PPDI1_WIDTH (1U) 7702 #define SIUL2_PGPDI11_PPDI1(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI11_PPDI1_SHIFT)) & SIUL2_PGPDI11_PPDI1_MASK) 7703 7704 #define SIUL2_PGPDI11_PPDI2_MASK (0x4U) 7705 #define SIUL2_PGPDI11_PPDI2_SHIFT (2U) 7706 #define SIUL2_PGPDI11_PPDI2_WIDTH (1U) 7707 #define SIUL2_PGPDI11_PPDI2(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI11_PPDI2_SHIFT)) & SIUL2_PGPDI11_PPDI2_MASK) 7708 7709 #define SIUL2_PGPDI11_PPDI3_MASK (0x8U) 7710 #define SIUL2_PGPDI11_PPDI3_SHIFT (3U) 7711 #define SIUL2_PGPDI11_PPDI3_WIDTH (1U) 7712 #define SIUL2_PGPDI11_PPDI3(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI11_PPDI3_SHIFT)) & SIUL2_PGPDI11_PPDI3_MASK) 7713 7714 #define SIUL2_PGPDI11_PPDI4_MASK (0x10U) 7715 #define SIUL2_PGPDI11_PPDI4_SHIFT (4U) 7716 #define SIUL2_PGPDI11_PPDI4_WIDTH (1U) 7717 #define SIUL2_PGPDI11_PPDI4(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI11_PPDI4_SHIFT)) & SIUL2_PGPDI11_PPDI4_MASK) 7718 7719 #define SIUL2_PGPDI11_PPDI5_MASK (0x20U) 7720 #define SIUL2_PGPDI11_PPDI5_SHIFT (5U) 7721 #define SIUL2_PGPDI11_PPDI5_WIDTH (1U) 7722 #define SIUL2_PGPDI11_PPDI5(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI11_PPDI5_SHIFT)) & SIUL2_PGPDI11_PPDI5_MASK) 7723 7724 #define SIUL2_PGPDI11_PPDI6_MASK (0x40U) 7725 #define SIUL2_PGPDI11_PPDI6_SHIFT (6U) 7726 #define SIUL2_PGPDI11_PPDI6_WIDTH (1U) 7727 #define SIUL2_PGPDI11_PPDI6(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI11_PPDI6_SHIFT)) & SIUL2_PGPDI11_PPDI6_MASK) 7728 7729 #define SIUL2_PGPDI11_PPDI7_MASK (0x80U) 7730 #define SIUL2_PGPDI11_PPDI7_SHIFT (7U) 7731 #define SIUL2_PGPDI11_PPDI7_WIDTH (1U) 7732 #define SIUL2_PGPDI11_PPDI7(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI11_PPDI7_SHIFT)) & SIUL2_PGPDI11_PPDI7_MASK) 7733 7734 #define SIUL2_PGPDI11_PPDI8_MASK (0x100U) 7735 #define SIUL2_PGPDI11_PPDI8_SHIFT (8U) 7736 #define SIUL2_PGPDI11_PPDI8_WIDTH (1U) 7737 #define SIUL2_PGPDI11_PPDI8(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI11_PPDI8_SHIFT)) & SIUL2_PGPDI11_PPDI8_MASK) 7738 7739 #define SIUL2_PGPDI11_PPDI9_MASK (0x200U) 7740 #define SIUL2_PGPDI11_PPDI9_SHIFT (9U) 7741 #define SIUL2_PGPDI11_PPDI9_WIDTH (1U) 7742 #define SIUL2_PGPDI11_PPDI9(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI11_PPDI9_SHIFT)) & SIUL2_PGPDI11_PPDI9_MASK) 7743 7744 #define SIUL2_PGPDI11_PPDI10_MASK (0x400U) 7745 #define SIUL2_PGPDI11_PPDI10_SHIFT (10U) 7746 #define SIUL2_PGPDI11_PPDI10_WIDTH (1U) 7747 #define SIUL2_PGPDI11_PPDI10(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI11_PPDI10_SHIFT)) & SIUL2_PGPDI11_PPDI10_MASK) 7748 7749 #define SIUL2_PGPDI11_PPDI11_MASK (0x800U) 7750 #define SIUL2_PGPDI11_PPDI11_SHIFT (11U) 7751 #define SIUL2_PGPDI11_PPDI11_WIDTH (1U) 7752 #define SIUL2_PGPDI11_PPDI11(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI11_PPDI11_SHIFT)) & SIUL2_PGPDI11_PPDI11_MASK) 7753 7754 #define SIUL2_PGPDI11_PPDI12_MASK (0x1000U) 7755 #define SIUL2_PGPDI11_PPDI12_SHIFT (12U) 7756 #define SIUL2_PGPDI11_PPDI12_WIDTH (1U) 7757 #define SIUL2_PGPDI11_PPDI12(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI11_PPDI12_SHIFT)) & SIUL2_PGPDI11_PPDI12_MASK) 7758 7759 #define SIUL2_PGPDI11_PPDI13_MASK (0x2000U) 7760 #define SIUL2_PGPDI11_PPDI13_SHIFT (13U) 7761 #define SIUL2_PGPDI11_PPDI13_WIDTH (1U) 7762 #define SIUL2_PGPDI11_PPDI13(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI11_PPDI13_SHIFT)) & SIUL2_PGPDI11_PPDI13_MASK) 7763 7764 #define SIUL2_PGPDI11_PPDI14_MASK (0x4000U) 7765 #define SIUL2_PGPDI11_PPDI14_SHIFT (14U) 7766 #define SIUL2_PGPDI11_PPDI14_WIDTH (1U) 7767 #define SIUL2_PGPDI11_PPDI14(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI11_PPDI14_SHIFT)) & SIUL2_PGPDI11_PPDI14_MASK) 7768 7769 #define SIUL2_PGPDI11_PPDI15_MASK (0x8000U) 7770 #define SIUL2_PGPDI11_PPDI15_SHIFT (15U) 7771 #define SIUL2_PGPDI11_PPDI15_WIDTH (1U) 7772 #define SIUL2_PGPDI11_PPDI15(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI11_PPDI15_SHIFT)) & SIUL2_PGPDI11_PPDI15_MASK) 7773 /*! @} */ 7774 7775 /*! @name PGPDI10 - SIUL2 Parallel GPIO Pad Data In Register */ 7776 /*! @{ */ 7777 7778 #define SIUL2_PGPDI10_PPDI0_MASK (0x1U) 7779 #define SIUL2_PGPDI10_PPDI0_SHIFT (0U) 7780 #define SIUL2_PGPDI10_PPDI0_WIDTH (1U) 7781 #define SIUL2_PGPDI10_PPDI0(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI10_PPDI0_SHIFT)) & SIUL2_PGPDI10_PPDI0_MASK) 7782 7783 #define SIUL2_PGPDI10_PPDI1_MASK (0x2U) 7784 #define SIUL2_PGPDI10_PPDI1_SHIFT (1U) 7785 #define SIUL2_PGPDI10_PPDI1_WIDTH (1U) 7786 #define SIUL2_PGPDI10_PPDI1(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI10_PPDI1_SHIFT)) & SIUL2_PGPDI10_PPDI1_MASK) 7787 7788 #define SIUL2_PGPDI10_PPDI2_MASK (0x4U) 7789 #define SIUL2_PGPDI10_PPDI2_SHIFT (2U) 7790 #define SIUL2_PGPDI10_PPDI2_WIDTH (1U) 7791 #define SIUL2_PGPDI10_PPDI2(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI10_PPDI2_SHIFT)) & SIUL2_PGPDI10_PPDI2_MASK) 7792 7793 #define SIUL2_PGPDI10_PPDI3_MASK (0x8U) 7794 #define SIUL2_PGPDI10_PPDI3_SHIFT (3U) 7795 #define SIUL2_PGPDI10_PPDI3_WIDTH (1U) 7796 #define SIUL2_PGPDI10_PPDI3(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI10_PPDI3_SHIFT)) & SIUL2_PGPDI10_PPDI3_MASK) 7797 7798 #define SIUL2_PGPDI10_PPDI4_MASK (0x10U) 7799 #define SIUL2_PGPDI10_PPDI4_SHIFT (4U) 7800 #define SIUL2_PGPDI10_PPDI4_WIDTH (1U) 7801 #define SIUL2_PGPDI10_PPDI4(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI10_PPDI4_SHIFT)) & SIUL2_PGPDI10_PPDI4_MASK) 7802 7803 #define SIUL2_PGPDI10_PPDI5_MASK (0x20U) 7804 #define SIUL2_PGPDI10_PPDI5_SHIFT (5U) 7805 #define SIUL2_PGPDI10_PPDI5_WIDTH (1U) 7806 #define SIUL2_PGPDI10_PPDI5(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI10_PPDI5_SHIFT)) & SIUL2_PGPDI10_PPDI5_MASK) 7807 7808 #define SIUL2_PGPDI10_PPDI6_MASK (0x40U) 7809 #define SIUL2_PGPDI10_PPDI6_SHIFT (6U) 7810 #define SIUL2_PGPDI10_PPDI6_WIDTH (1U) 7811 #define SIUL2_PGPDI10_PPDI6(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI10_PPDI6_SHIFT)) & SIUL2_PGPDI10_PPDI6_MASK) 7812 7813 #define SIUL2_PGPDI10_PPDI7_MASK (0x80U) 7814 #define SIUL2_PGPDI10_PPDI7_SHIFT (7U) 7815 #define SIUL2_PGPDI10_PPDI7_WIDTH (1U) 7816 #define SIUL2_PGPDI10_PPDI7(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI10_PPDI7_SHIFT)) & SIUL2_PGPDI10_PPDI7_MASK) 7817 7818 #define SIUL2_PGPDI10_PPDI8_MASK (0x100U) 7819 #define SIUL2_PGPDI10_PPDI8_SHIFT (8U) 7820 #define SIUL2_PGPDI10_PPDI8_WIDTH (1U) 7821 #define SIUL2_PGPDI10_PPDI8(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI10_PPDI8_SHIFT)) & SIUL2_PGPDI10_PPDI8_MASK) 7822 7823 #define SIUL2_PGPDI10_PPDI9_MASK (0x200U) 7824 #define SIUL2_PGPDI10_PPDI9_SHIFT (9U) 7825 #define SIUL2_PGPDI10_PPDI9_WIDTH (1U) 7826 #define SIUL2_PGPDI10_PPDI9(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI10_PPDI9_SHIFT)) & SIUL2_PGPDI10_PPDI9_MASK) 7827 7828 #define SIUL2_PGPDI10_PPDI10_MASK (0x400U) 7829 #define SIUL2_PGPDI10_PPDI10_SHIFT (10U) 7830 #define SIUL2_PGPDI10_PPDI10_WIDTH (1U) 7831 #define SIUL2_PGPDI10_PPDI10(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI10_PPDI10_SHIFT)) & SIUL2_PGPDI10_PPDI10_MASK) 7832 7833 #define SIUL2_PGPDI10_PPDI11_MASK (0x800U) 7834 #define SIUL2_PGPDI10_PPDI11_SHIFT (11U) 7835 #define SIUL2_PGPDI10_PPDI11_WIDTH (1U) 7836 #define SIUL2_PGPDI10_PPDI11(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI10_PPDI11_SHIFT)) & SIUL2_PGPDI10_PPDI11_MASK) 7837 7838 #define SIUL2_PGPDI10_PPDI12_MASK (0x1000U) 7839 #define SIUL2_PGPDI10_PPDI12_SHIFT (12U) 7840 #define SIUL2_PGPDI10_PPDI12_WIDTH (1U) 7841 #define SIUL2_PGPDI10_PPDI12(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI10_PPDI12_SHIFT)) & SIUL2_PGPDI10_PPDI12_MASK) 7842 7843 #define SIUL2_PGPDI10_PPDI13_MASK (0x2000U) 7844 #define SIUL2_PGPDI10_PPDI13_SHIFT (13U) 7845 #define SIUL2_PGPDI10_PPDI13_WIDTH (1U) 7846 #define SIUL2_PGPDI10_PPDI13(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI10_PPDI13_SHIFT)) & SIUL2_PGPDI10_PPDI13_MASK) 7847 7848 #define SIUL2_PGPDI10_PPDI14_MASK (0x4000U) 7849 #define SIUL2_PGPDI10_PPDI14_SHIFT (14U) 7850 #define SIUL2_PGPDI10_PPDI14_WIDTH (1U) 7851 #define SIUL2_PGPDI10_PPDI14(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI10_PPDI14_SHIFT)) & SIUL2_PGPDI10_PPDI14_MASK) 7852 7853 #define SIUL2_PGPDI10_PPDI15_MASK (0x8000U) 7854 #define SIUL2_PGPDI10_PPDI15_SHIFT (15U) 7855 #define SIUL2_PGPDI10_PPDI15_WIDTH (1U) 7856 #define SIUL2_PGPDI10_PPDI15(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI10_PPDI15_SHIFT)) & SIUL2_PGPDI10_PPDI15_MASK) 7857 /*! @} */ 7858 7859 /*! @name PGPDI13 - SIUL2 Parallel GPIO Pad Data In Register */ 7860 /*! @{ */ 7861 7862 #define SIUL2_PGPDI13_PPDI4_MASK (0x10U) 7863 #define SIUL2_PGPDI13_PPDI4_SHIFT (4U) 7864 #define SIUL2_PGPDI13_PPDI4_WIDTH (1U) 7865 #define SIUL2_PGPDI13_PPDI4(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI13_PPDI4_SHIFT)) & SIUL2_PGPDI13_PPDI4_MASK) 7866 7867 #define SIUL2_PGPDI13_PPDI5_MASK (0x20U) 7868 #define SIUL2_PGPDI13_PPDI5_SHIFT (5U) 7869 #define SIUL2_PGPDI13_PPDI5_WIDTH (1U) 7870 #define SIUL2_PGPDI13_PPDI5(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI13_PPDI5_SHIFT)) & SIUL2_PGPDI13_PPDI5_MASK) 7871 7872 #define SIUL2_PGPDI13_PPDI6_MASK (0x40U) 7873 #define SIUL2_PGPDI13_PPDI6_SHIFT (6U) 7874 #define SIUL2_PGPDI13_PPDI6_WIDTH (1U) 7875 #define SIUL2_PGPDI13_PPDI6(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI13_PPDI6_SHIFT)) & SIUL2_PGPDI13_PPDI6_MASK) 7876 7877 #define SIUL2_PGPDI13_PPDI7_MASK (0x80U) 7878 #define SIUL2_PGPDI13_PPDI7_SHIFT (7U) 7879 #define SIUL2_PGPDI13_PPDI7_WIDTH (1U) 7880 #define SIUL2_PGPDI13_PPDI7(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI13_PPDI7_SHIFT)) & SIUL2_PGPDI13_PPDI7_MASK) 7881 7882 #define SIUL2_PGPDI13_PPDI8_MASK (0x100U) 7883 #define SIUL2_PGPDI13_PPDI8_SHIFT (8U) 7884 #define SIUL2_PGPDI13_PPDI8_WIDTH (1U) 7885 #define SIUL2_PGPDI13_PPDI8(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI13_PPDI8_SHIFT)) & SIUL2_PGPDI13_PPDI8_MASK) 7886 7887 #define SIUL2_PGPDI13_PPDI9_MASK (0x200U) 7888 #define SIUL2_PGPDI13_PPDI9_SHIFT (9U) 7889 #define SIUL2_PGPDI13_PPDI9_WIDTH (1U) 7890 #define SIUL2_PGPDI13_PPDI9(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI13_PPDI9_SHIFT)) & SIUL2_PGPDI13_PPDI9_MASK) 7891 7892 #define SIUL2_PGPDI13_PPDI10_MASK (0x400U) 7893 #define SIUL2_PGPDI13_PPDI10_SHIFT (10U) 7894 #define SIUL2_PGPDI13_PPDI10_WIDTH (1U) 7895 #define SIUL2_PGPDI13_PPDI10(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI13_PPDI10_SHIFT)) & SIUL2_PGPDI13_PPDI10_MASK) 7896 7897 #define SIUL2_PGPDI13_PPDI11_MASK (0x800U) 7898 #define SIUL2_PGPDI13_PPDI11_SHIFT (11U) 7899 #define SIUL2_PGPDI13_PPDI11_WIDTH (1U) 7900 #define SIUL2_PGPDI13_PPDI11(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI13_PPDI11_SHIFT)) & SIUL2_PGPDI13_PPDI11_MASK) 7901 7902 #define SIUL2_PGPDI13_PPDI12_MASK (0x1000U) 7903 #define SIUL2_PGPDI13_PPDI12_SHIFT (12U) 7904 #define SIUL2_PGPDI13_PPDI12_WIDTH (1U) 7905 #define SIUL2_PGPDI13_PPDI12(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI13_PPDI12_SHIFT)) & SIUL2_PGPDI13_PPDI12_MASK) 7906 7907 #define SIUL2_PGPDI13_PPDI13_MASK (0x2000U) 7908 #define SIUL2_PGPDI13_PPDI13_SHIFT (13U) 7909 #define SIUL2_PGPDI13_PPDI13_WIDTH (1U) 7910 #define SIUL2_PGPDI13_PPDI13(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI13_PPDI13_SHIFT)) & SIUL2_PGPDI13_PPDI13_MASK) 7911 7912 #define SIUL2_PGPDI13_PPDI14_MASK (0x4000U) 7913 #define SIUL2_PGPDI13_PPDI14_SHIFT (14U) 7914 #define SIUL2_PGPDI13_PPDI14_WIDTH (1U) 7915 #define SIUL2_PGPDI13_PPDI14(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI13_PPDI14_SHIFT)) & SIUL2_PGPDI13_PPDI14_MASK) 7916 7917 #define SIUL2_PGPDI13_PPDI15_MASK (0x8000U) 7918 #define SIUL2_PGPDI13_PPDI15_SHIFT (15U) 7919 #define SIUL2_PGPDI13_PPDI15_WIDTH (1U) 7920 #define SIUL2_PGPDI13_PPDI15(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI13_PPDI15_SHIFT)) & SIUL2_PGPDI13_PPDI15_MASK) 7921 /*! @} */ 7922 7923 /*! @name PGPDI12 - SIUL2 Parallel GPIO Pad Data In Register */ 7924 /*! @{ */ 7925 7926 #define SIUL2_PGPDI12_PPDI0_MASK (0x1U) 7927 #define SIUL2_PGPDI12_PPDI0_SHIFT (0U) 7928 #define SIUL2_PGPDI12_PPDI0_WIDTH (1U) 7929 #define SIUL2_PGPDI12_PPDI0(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI12_PPDI0_SHIFT)) & SIUL2_PGPDI12_PPDI0_MASK) 7930 7931 #define SIUL2_PGPDI12_PPDI1_MASK (0x2U) 7932 #define SIUL2_PGPDI12_PPDI1_SHIFT (1U) 7933 #define SIUL2_PGPDI12_PPDI1_WIDTH (1U) 7934 #define SIUL2_PGPDI12_PPDI1(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI12_PPDI1_SHIFT)) & SIUL2_PGPDI12_PPDI1_MASK) 7935 7936 #define SIUL2_PGPDI12_PPDI2_MASK (0x4U) 7937 #define SIUL2_PGPDI12_PPDI2_SHIFT (2U) 7938 #define SIUL2_PGPDI12_PPDI2_WIDTH (1U) 7939 #define SIUL2_PGPDI12_PPDI2(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI12_PPDI2_SHIFT)) & SIUL2_PGPDI12_PPDI2_MASK) 7940 7941 #define SIUL2_PGPDI12_PPDI3_MASK (0x8U) 7942 #define SIUL2_PGPDI12_PPDI3_SHIFT (3U) 7943 #define SIUL2_PGPDI12_PPDI3_WIDTH (1U) 7944 #define SIUL2_PGPDI12_PPDI3(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI12_PPDI3_SHIFT)) & SIUL2_PGPDI12_PPDI3_MASK) 7945 7946 #define SIUL2_PGPDI12_PPDI4_MASK (0x10U) 7947 #define SIUL2_PGPDI12_PPDI4_SHIFT (4U) 7948 #define SIUL2_PGPDI12_PPDI4_WIDTH (1U) 7949 #define SIUL2_PGPDI12_PPDI4(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI12_PPDI4_SHIFT)) & SIUL2_PGPDI12_PPDI4_MASK) 7950 7951 #define SIUL2_PGPDI12_PPDI5_MASK (0x20U) 7952 #define SIUL2_PGPDI12_PPDI5_SHIFT (5U) 7953 #define SIUL2_PGPDI12_PPDI5_WIDTH (1U) 7954 #define SIUL2_PGPDI12_PPDI5(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI12_PPDI5_SHIFT)) & SIUL2_PGPDI12_PPDI5_MASK) 7955 7956 #define SIUL2_PGPDI12_PPDI6_MASK (0x40U) 7957 #define SIUL2_PGPDI12_PPDI6_SHIFT (6U) 7958 #define SIUL2_PGPDI12_PPDI6_WIDTH (1U) 7959 #define SIUL2_PGPDI12_PPDI6(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI12_PPDI6_SHIFT)) & SIUL2_PGPDI12_PPDI6_MASK) 7960 7961 #define SIUL2_PGPDI12_PPDI7_MASK (0x80U) 7962 #define SIUL2_PGPDI12_PPDI7_SHIFT (7U) 7963 #define SIUL2_PGPDI12_PPDI7_WIDTH (1U) 7964 #define SIUL2_PGPDI12_PPDI7(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI12_PPDI7_SHIFT)) & SIUL2_PGPDI12_PPDI7_MASK) 7965 7966 #define SIUL2_PGPDI12_PPDI8_MASK (0x100U) 7967 #define SIUL2_PGPDI12_PPDI8_SHIFT (8U) 7968 #define SIUL2_PGPDI12_PPDI8_WIDTH (1U) 7969 #define SIUL2_PGPDI12_PPDI8(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI12_PPDI8_SHIFT)) & SIUL2_PGPDI12_PPDI8_MASK) 7970 7971 #define SIUL2_PGPDI12_PPDI9_MASK (0x200U) 7972 #define SIUL2_PGPDI12_PPDI9_SHIFT (9U) 7973 #define SIUL2_PGPDI12_PPDI9_WIDTH (1U) 7974 #define SIUL2_PGPDI12_PPDI9(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI12_PPDI9_SHIFT)) & SIUL2_PGPDI12_PPDI9_MASK) 7975 7976 #define SIUL2_PGPDI12_PPDI10_MASK (0x400U) 7977 #define SIUL2_PGPDI12_PPDI10_SHIFT (10U) 7978 #define SIUL2_PGPDI12_PPDI10_WIDTH (1U) 7979 #define SIUL2_PGPDI12_PPDI10(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI12_PPDI10_SHIFT)) & SIUL2_PGPDI12_PPDI10_MASK) 7980 7981 #define SIUL2_PGPDI12_PPDI11_MASK (0x800U) 7982 #define SIUL2_PGPDI12_PPDI11_SHIFT (11U) 7983 #define SIUL2_PGPDI12_PPDI11_WIDTH (1U) 7984 #define SIUL2_PGPDI12_PPDI11(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI12_PPDI11_SHIFT)) & SIUL2_PGPDI12_PPDI11_MASK) 7985 7986 #define SIUL2_PGPDI12_PPDI12_MASK (0x1000U) 7987 #define SIUL2_PGPDI12_PPDI12_SHIFT (12U) 7988 #define SIUL2_PGPDI12_PPDI12_WIDTH (1U) 7989 #define SIUL2_PGPDI12_PPDI12(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI12_PPDI12_SHIFT)) & SIUL2_PGPDI12_PPDI12_MASK) 7990 7991 #define SIUL2_PGPDI12_PPDI13_MASK (0x2000U) 7992 #define SIUL2_PGPDI12_PPDI13_SHIFT (13U) 7993 #define SIUL2_PGPDI12_PPDI13_WIDTH (1U) 7994 #define SIUL2_PGPDI12_PPDI13(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI12_PPDI13_SHIFT)) & SIUL2_PGPDI12_PPDI13_MASK) 7995 7996 #define SIUL2_PGPDI12_PPDI14_MASK (0x4000U) 7997 #define SIUL2_PGPDI12_PPDI14_SHIFT (14U) 7998 #define SIUL2_PGPDI12_PPDI14_WIDTH (1U) 7999 #define SIUL2_PGPDI12_PPDI14(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI12_PPDI14_SHIFT)) & SIUL2_PGPDI12_PPDI14_MASK) 8000 8001 #define SIUL2_PGPDI12_PPDI15_MASK (0x8000U) 8002 #define SIUL2_PGPDI12_PPDI15_SHIFT (15U) 8003 #define SIUL2_PGPDI12_PPDI15_WIDTH (1U) 8004 #define SIUL2_PGPDI12_PPDI15(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI12_PPDI15_SHIFT)) & SIUL2_PGPDI12_PPDI15_MASK) 8005 /*! @} */ 8006 8007 /*! @name MPGPDO - SIUL2 Masked Parallel GPIO Pad Data Out Register */ 8008 /*! @{ */ 8009 8010 #define SIUL2_MPGPDO_MPPDO0_MASK (0x1U) 8011 #define SIUL2_MPGPDO_MPPDO0_SHIFT (0U) 8012 #define SIUL2_MPGPDO_MPPDO0_WIDTH (1U) 8013 #define SIUL2_MPGPDO_MPPDO0(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MPPDO0_SHIFT)) & SIUL2_MPGPDO_MPPDO0_MASK) 8014 8015 #define SIUL2_MPGPDO_MPPDO1_MASK (0x2U) 8016 #define SIUL2_MPGPDO_MPPDO1_SHIFT (1U) 8017 #define SIUL2_MPGPDO_MPPDO1_WIDTH (1U) 8018 #define SIUL2_MPGPDO_MPPDO1(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MPPDO1_SHIFT)) & SIUL2_MPGPDO_MPPDO1_MASK) 8019 8020 #define SIUL2_MPGPDO_MPPDO2_MASK (0x4U) 8021 #define SIUL2_MPGPDO_MPPDO2_SHIFT (2U) 8022 #define SIUL2_MPGPDO_MPPDO2_WIDTH (1U) 8023 #define SIUL2_MPGPDO_MPPDO2(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MPPDO2_SHIFT)) & SIUL2_MPGPDO_MPPDO2_MASK) 8024 8025 #define SIUL2_MPGPDO_MPPDO3_MASK (0x8U) 8026 #define SIUL2_MPGPDO_MPPDO3_SHIFT (3U) 8027 #define SIUL2_MPGPDO_MPPDO3_WIDTH (1U) 8028 #define SIUL2_MPGPDO_MPPDO3(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MPPDO3_SHIFT)) & SIUL2_MPGPDO_MPPDO3_MASK) 8029 8030 #define SIUL2_MPGPDO_MPPDO4_MASK (0x10U) 8031 #define SIUL2_MPGPDO_MPPDO4_SHIFT (4U) 8032 #define SIUL2_MPGPDO_MPPDO4_WIDTH (1U) 8033 #define SIUL2_MPGPDO_MPPDO4(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MPPDO4_SHIFT)) & SIUL2_MPGPDO_MPPDO4_MASK) 8034 8035 #define SIUL2_MPGPDO_MPPDO5_MASK (0x20U) 8036 #define SIUL2_MPGPDO_MPPDO5_SHIFT (5U) 8037 #define SIUL2_MPGPDO_MPPDO5_WIDTH (1U) 8038 #define SIUL2_MPGPDO_MPPDO5(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MPPDO5_SHIFT)) & SIUL2_MPGPDO_MPPDO5_MASK) 8039 8040 #define SIUL2_MPGPDO_MPPDO6_MASK (0x40U) 8041 #define SIUL2_MPGPDO_MPPDO6_SHIFT (6U) 8042 #define SIUL2_MPGPDO_MPPDO6_WIDTH (1U) 8043 #define SIUL2_MPGPDO_MPPDO6(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MPPDO6_SHIFT)) & SIUL2_MPGPDO_MPPDO6_MASK) 8044 8045 #define SIUL2_MPGPDO_MPPDO7_MASK (0x80U) 8046 #define SIUL2_MPGPDO_MPPDO7_SHIFT (7U) 8047 #define SIUL2_MPGPDO_MPPDO7_WIDTH (1U) 8048 #define SIUL2_MPGPDO_MPPDO7(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MPPDO7_SHIFT)) & SIUL2_MPGPDO_MPPDO7_MASK) 8049 8050 #define SIUL2_MPGPDO_MPPDO8_MASK (0x100U) 8051 #define SIUL2_MPGPDO_MPPDO8_SHIFT (8U) 8052 #define SIUL2_MPGPDO_MPPDO8_WIDTH (1U) 8053 #define SIUL2_MPGPDO_MPPDO8(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MPPDO8_SHIFT)) & SIUL2_MPGPDO_MPPDO8_MASK) 8054 8055 #define SIUL2_MPGPDO_MPPDO9_MASK (0x200U) 8056 #define SIUL2_MPGPDO_MPPDO9_SHIFT (9U) 8057 #define SIUL2_MPGPDO_MPPDO9_WIDTH (1U) 8058 #define SIUL2_MPGPDO_MPPDO9(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MPPDO9_SHIFT)) & SIUL2_MPGPDO_MPPDO9_MASK) 8059 8060 #define SIUL2_MPGPDO_MPPDO10_MASK (0x400U) 8061 #define SIUL2_MPGPDO_MPPDO10_SHIFT (10U) 8062 #define SIUL2_MPGPDO_MPPDO10_WIDTH (1U) 8063 #define SIUL2_MPGPDO_MPPDO10(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MPPDO10_SHIFT)) & SIUL2_MPGPDO_MPPDO10_MASK) 8064 8065 #define SIUL2_MPGPDO_MPPDO11_MASK (0x800U) 8066 #define SIUL2_MPGPDO_MPPDO11_SHIFT (11U) 8067 #define SIUL2_MPGPDO_MPPDO11_WIDTH (1U) 8068 #define SIUL2_MPGPDO_MPPDO11(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MPPDO11_SHIFT)) & SIUL2_MPGPDO_MPPDO11_MASK) 8069 8070 #define SIUL2_MPGPDO_MPPDO12_MASK (0x1000U) 8071 #define SIUL2_MPGPDO_MPPDO12_SHIFT (12U) 8072 #define SIUL2_MPGPDO_MPPDO12_WIDTH (1U) 8073 #define SIUL2_MPGPDO_MPPDO12(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MPPDO12_SHIFT)) & SIUL2_MPGPDO_MPPDO12_MASK) 8074 8075 #define SIUL2_MPGPDO_MPPDO13_MASK (0x2000U) 8076 #define SIUL2_MPGPDO_MPPDO13_SHIFT (13U) 8077 #define SIUL2_MPGPDO_MPPDO13_WIDTH (1U) 8078 #define SIUL2_MPGPDO_MPPDO13(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MPPDO13_SHIFT)) & SIUL2_MPGPDO_MPPDO13_MASK) 8079 8080 #define SIUL2_MPGPDO_MPPDO14_MASK (0x4000U) 8081 #define SIUL2_MPGPDO_MPPDO14_SHIFT (14U) 8082 #define SIUL2_MPGPDO_MPPDO14_WIDTH (1U) 8083 #define SIUL2_MPGPDO_MPPDO14(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MPPDO14_SHIFT)) & SIUL2_MPGPDO_MPPDO14_MASK) 8084 8085 #define SIUL2_MPGPDO_MPPDO15_MASK (0x8000U) 8086 #define SIUL2_MPGPDO_MPPDO15_SHIFT (15U) 8087 #define SIUL2_MPGPDO_MPPDO15_WIDTH (1U) 8088 #define SIUL2_MPGPDO_MPPDO15(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MPPDO15_SHIFT)) & SIUL2_MPGPDO_MPPDO15_MASK) 8089 8090 #define SIUL2_MPGPDO_MASK0_MASK (0x10000U) 8091 #define SIUL2_MPGPDO_MASK0_SHIFT (16U) 8092 #define SIUL2_MPGPDO_MASK0_WIDTH (1U) 8093 #define SIUL2_MPGPDO_MASK0(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MASK0_SHIFT)) & SIUL2_MPGPDO_MASK0_MASK) 8094 8095 #define SIUL2_MPGPDO_MASK1_MASK (0x20000U) 8096 #define SIUL2_MPGPDO_MASK1_SHIFT (17U) 8097 #define SIUL2_MPGPDO_MASK1_WIDTH (1U) 8098 #define SIUL2_MPGPDO_MASK1(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MASK1_SHIFT)) & SIUL2_MPGPDO_MASK1_MASK) 8099 8100 #define SIUL2_MPGPDO_MASK2_MASK (0x40000U) 8101 #define SIUL2_MPGPDO_MASK2_SHIFT (18U) 8102 #define SIUL2_MPGPDO_MASK2_WIDTH (1U) 8103 #define SIUL2_MPGPDO_MASK2(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MASK2_SHIFT)) & SIUL2_MPGPDO_MASK2_MASK) 8104 8105 #define SIUL2_MPGPDO_MASK3_MASK (0x80000U) 8106 #define SIUL2_MPGPDO_MASK3_SHIFT (19U) 8107 #define SIUL2_MPGPDO_MASK3_WIDTH (1U) 8108 #define SIUL2_MPGPDO_MASK3(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MASK3_SHIFT)) & SIUL2_MPGPDO_MASK3_MASK) 8109 8110 #define SIUL2_MPGPDO_MASK4_MASK (0x100000U) 8111 #define SIUL2_MPGPDO_MASK4_SHIFT (20U) 8112 #define SIUL2_MPGPDO_MASK4_WIDTH (1U) 8113 #define SIUL2_MPGPDO_MASK4(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MASK4_SHIFT)) & SIUL2_MPGPDO_MASK4_MASK) 8114 8115 #define SIUL2_MPGPDO_MASK5_MASK (0x200000U) 8116 #define SIUL2_MPGPDO_MASK5_SHIFT (21U) 8117 #define SIUL2_MPGPDO_MASK5_WIDTH (1U) 8118 #define SIUL2_MPGPDO_MASK5(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MASK5_SHIFT)) & SIUL2_MPGPDO_MASK5_MASK) 8119 8120 #define SIUL2_MPGPDO_MASK6_MASK (0x400000U) 8121 #define SIUL2_MPGPDO_MASK6_SHIFT (22U) 8122 #define SIUL2_MPGPDO_MASK6_WIDTH (1U) 8123 #define SIUL2_MPGPDO_MASK6(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MASK6_SHIFT)) & SIUL2_MPGPDO_MASK6_MASK) 8124 8125 #define SIUL2_MPGPDO_MASK7_MASK (0x800000U) 8126 #define SIUL2_MPGPDO_MASK7_SHIFT (23U) 8127 #define SIUL2_MPGPDO_MASK7_WIDTH (1U) 8128 #define SIUL2_MPGPDO_MASK7(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MASK7_SHIFT)) & SIUL2_MPGPDO_MASK7_MASK) 8129 8130 #define SIUL2_MPGPDO_MASK8_MASK (0x1000000U) 8131 #define SIUL2_MPGPDO_MASK8_SHIFT (24U) 8132 #define SIUL2_MPGPDO_MASK8_WIDTH (1U) 8133 #define SIUL2_MPGPDO_MASK8(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MASK8_SHIFT)) & SIUL2_MPGPDO_MASK8_MASK) 8134 8135 #define SIUL2_MPGPDO_MASK9_MASK (0x2000000U) 8136 #define SIUL2_MPGPDO_MASK9_SHIFT (25U) 8137 #define SIUL2_MPGPDO_MASK9_WIDTH (1U) 8138 #define SIUL2_MPGPDO_MASK9(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MASK9_SHIFT)) & SIUL2_MPGPDO_MASK9_MASK) 8139 8140 #define SIUL2_MPGPDO_MASK10_MASK (0x4000000U) 8141 #define SIUL2_MPGPDO_MASK10_SHIFT (26U) 8142 #define SIUL2_MPGPDO_MASK10_WIDTH (1U) 8143 #define SIUL2_MPGPDO_MASK10(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MASK10_SHIFT)) & SIUL2_MPGPDO_MASK10_MASK) 8144 8145 #define SIUL2_MPGPDO_MASK11_MASK (0x8000000U) 8146 #define SIUL2_MPGPDO_MASK11_SHIFT (27U) 8147 #define SIUL2_MPGPDO_MASK11_WIDTH (1U) 8148 #define SIUL2_MPGPDO_MASK11(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MASK11_SHIFT)) & SIUL2_MPGPDO_MASK11_MASK) 8149 8150 #define SIUL2_MPGPDO_MASK12_MASK (0x10000000U) 8151 #define SIUL2_MPGPDO_MASK12_SHIFT (28U) 8152 #define SIUL2_MPGPDO_MASK12_WIDTH (1U) 8153 #define SIUL2_MPGPDO_MASK12(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MASK12_SHIFT)) & SIUL2_MPGPDO_MASK12_MASK) 8154 8155 #define SIUL2_MPGPDO_MASK13_MASK (0x20000000U) 8156 #define SIUL2_MPGPDO_MASK13_SHIFT (29U) 8157 #define SIUL2_MPGPDO_MASK13_WIDTH (1U) 8158 #define SIUL2_MPGPDO_MASK13(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MASK13_SHIFT)) & SIUL2_MPGPDO_MASK13_MASK) 8159 8160 #define SIUL2_MPGPDO_MASK14_MASK (0x40000000U) 8161 #define SIUL2_MPGPDO_MASK14_SHIFT (30U) 8162 #define SIUL2_MPGPDO_MASK14_WIDTH (1U) 8163 #define SIUL2_MPGPDO_MASK14(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MASK14_SHIFT)) & SIUL2_MPGPDO_MASK14_MASK) 8164 8165 #define SIUL2_MPGPDO_MASK15_MASK (0x80000000U) 8166 #define SIUL2_MPGPDO_MASK15_SHIFT (31U) 8167 #define SIUL2_MPGPDO_MASK15_WIDTH (1U) 8168 #define SIUL2_MPGPDO_MASK15(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MASK15_SHIFT)) & SIUL2_MPGPDO_MASK15_MASK) 8169 /*! @} */ 8170 8171 /*! 8172 * @} 8173 */ /* end of group SIUL2_Register_Masks */ 8174 8175 /*! 8176 * @} 8177 */ /* end of group SIUL2_Peripheral_Access_Layer */ 8178 8179 #endif /* #if !defined(S32K344_SIUL2_H_) */ 8180
