1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016-2017 NXP
4 *
5 * Redistribution and use in source and binary forms, with or without modification,
6 * are permitted provided that the following conditions are met:
7 *
8 * o Redistributions of source code must retain the above copyright notice, this list
9 * of conditions and the following disclaimer.
10 *
11 * o Redistributions in binary form must reproduce the above copyright notice, this
12 * list of conditions and the following disclaimer in the documentation and/or
13 * other materials provided with the distribution.
14 *
15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
16 * contributors may be used to endorse or promote products derived from this
17 * software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30 #include "fsl_device_registers.h"
31 #include "fsl_xcvr.h"
32 #include "dbg_ram_capture.h"
33
34 /*******************************************************************************
35 * Definitions
36 ******************************************************************************/
37 #if RADIO_IS_GEN_3P0
38 #define PKT_RAM_SIZE_16B_WORDS (1152) /* Number of 16bit entries in each Packet RAM bank */
39 #else
40 #define PKT_RAM_SIZE_16B_WORDS (544) /* Number of 16bit entries in each Packet RAM bank */
41 #endif /* RADIO_IS_GEN_3P0 */
42 #define SIGN_EXTND_12_16(x) ((x) | (((x) & 0x800) ? 0xF000 : 0x0))
43 #define SIGN_EXTND_5_8(x) ((x) | (((x) & 0x10) ? 0xE0 : 0x0))
44
45 /*******************************************************************************
46 * Prototypes
47 ******************************************************************************/
48
49 /*******************************************************************************
50 * Variables
51 ******************************************************************************/
52
53 /*******************************************************************************
54 * Code
55 ******************************************************************************/
dbg_ram_init(void)56 void dbg_ram_init(void)
57 {
58 XCVR_RX_DIG->RX_DIG_CTRL |= XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN_MASK; /* Turns on clocking to DMA/DBG blocks */
59 XCVR_MISC->PACKET_RAM_CTRL |= XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_ALLOW_MASK; /* Make PKT RAM available to just XCVR */
60
61 /* Some external code must perform the RX warmup request. */
62 }
63
64
dbg_ram_capture(uint8_t dbg_page,uint16_t buffer_sz_bytes,void * result_buffer)65 dbgRamStatus_t dbg_ram_capture(uint8_t dbg_page, uint16_t buffer_sz_bytes, void * result_buffer)
66 {
67 dbgRamStatus_t status = DBG_RAM_SUCCESS;
68 uint32_t temp;
69 volatile uint8_t *pkt_ram_ptr0, *pkt_ram_ptr1;
70 uint8_t * output_ptr;
71 uint16_t i;
72
73 /* Some external code must perform the RX warmup request after the dbg_ram_init() call */
74
75 if (result_buffer == NULL)
76 {
77 status = DBG_RAM_FAIL_NULL_POINTER;
78 }
79 else
80 {
81 if (buffer_sz_bytes > (544*2*2))
82 {
83 status = DBG_RAM_FAIL_SAMPLE_NUM_LIMIT;
84 }
85 else
86 {
87 temp = XCVR_MISC->PACKET_RAM_CTRL & ~XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE_MASK;
88 switch (dbg_page)
89 {
90 case DBG_PAGE_RXDIGIQ:
91 case DBG_PAGE_RAWADCIQ:
92 case DBG_PAGE_DCESTIQ:
93 XCVR_MISC->PACKET_RAM_CTRL = temp | XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE(dbg_page);
94
95 while (!(XCVR_MISC->PACKET_RAM_CTRL & XCVR_CTRL_PACKET_RAM_CTRL_DBG_RAM_FULL(2)))
96 {
97 /* Waiting for PKT_RAM to fill, wait for PKT_RAM_1 full to ensure complete memory is filled. */
98 }
99 /* Copy to output by bytes to avoid any access size problems in 16 bit packet RAM. */
100 output_ptr = result_buffer;
101 #if !RADIO_IS_GEN_2P1
102 pkt_ram_ptr0 = (volatile uint8_t *)&(XCVR_PKT_RAM->PACKET_RAM_0[0]);
103 pkt_ram_ptr1 = (volatile uint8_t *)&(XCVR_PKT_RAM->PACKET_RAM_1[0]);
104 #else
105 pkt_ram_ptr0 = (volatile uint8_t *)&(XCVR_PKT_RAM->PACKET_RAM[0]);
106 pkt_ram_ptr1 = (volatile uint8_t *)&(XCVR_PKT_RAM->PACKET_RAM[XCVR_PKT_RAM_PACKET_RAM_COUNT>>1]); /* Second packet RAM starts halfway through */
107 #endif /* !RADIO_IS_GEN_2P1 */
108 /* For *IQ pages I and Q are stored alternately in packet ram 0 & 1 */
109 for (i = 0; i < buffer_sz_bytes / 4; i++)
110 {
111 *output_ptr++ = *pkt_ram_ptr0++;
112 *output_ptr++ = *pkt_ram_ptr0++;
113 *output_ptr++ = *pkt_ram_ptr1++;
114 *output_ptr++ = *pkt_ram_ptr1++;
115 }
116
117 break;
118 case DBG_PAGE_RXINPH:
119 case DBG_PAGE_DEMOD_HARD:
120 case DBG_PAGE_DEMOD_SOFT:
121 case DBG_PAGE_DEMOD_DATA:
122 case DBG_PAGE_DEMOD_CFO_PH:
123 XCVR_MISC->PACKET_RAM_CTRL = temp | XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE(dbg_page);
124 while (!(XCVR_MISC->PACKET_RAM_CTRL & XCVR_CTRL_PACKET_RAM_CTRL_DBG_RAM_FULL(2)))
125 {
126 /* Waiting for PKT_RAM to fill, wait for PKT_RAM_1 full to ensure complete memory is filled. */
127 }
128 /* Copy to output by bytes to avoid any access size problems in 16 bit packet RAM. */
129 output_ptr = result_buffer;
130 #if !RADIO_IS_GEN_2P1
131 pkt_ram_ptr0 = (volatile uint8_t *)&(XCVR_PKT_RAM->PACKET_RAM_0[0]);
132 #else
133 pkt_ram_ptr0 = (volatile uint8_t *)&(XCVR_PKT_RAM->PACKET_RAM[0]);
134 #endif /* !RADIO_IS_GEN_2P1 */
135 /* This is for non I/Q */
136 for (i = 0; i < buffer_sz_bytes; i++)
137 {
138 *output_ptr = *pkt_ram_ptr0;
139 pkt_ram_ptr0++;
140 output_ptr++;
141 }
142 break;
143 case DBG_PAGE_IDLE:
144 default:
145 status = DBG_RAM_FAIL_PAGE_ERROR; /* Illegal capture page request. */
146 break;
147 }
148 }
149 }
150
151 XCVR_MISC->PACKET_RAM_CTRL &= ~XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE_MASK; /* Clear DBG_PAGE to terminate the acquisition */
152
153 /* Process the samples and copy to output pointer */
154
155 XCVR_MISC->PACKET_RAM_CTRL &= ~XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_ALLOW_MASK; /* Make PKT RAM available to protocol blocks */
156 XCVR_RX_DIG->RX_DIG_CTRL &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN_MASK; /* Turns off clocking to DMA/DBG blocks */
157
158 return status;
159 }
160
161
