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Searched refs:SDIF_CTRL_DMA_RESET_MASK (Results 1 – 24 of 24) sorted by relevance

/hal_nxp-3.6.0/mcux/mcux-sdk/drivers/sdif/
Dfsl_sdif.h130 kSDIF_ResetDMAInterface = SDIF_CTRL_DMA_RESET_MASK, /*!< reset DMA interface */
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54607/
DLPC54607.h9950 #define SDIF_CTRL_DMA_RESET_MASK (0x4U) macro
9954 … (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54S005/
DLPC54S005.h9765 #define SDIF_CTRL_DMA_RESET_MASK (0x4U) macro
9769 … (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54005/
DLPC54005.h8973 #define SDIF_CTRL_DMA_RESET_MASK (0x4U) macro
8977 … (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54605/
DLPC54605.h9306 #define SDIF_CTRL_DMA_RESET_MASK (0x4U) macro
9310 … (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54616/
DLPC54616.h13529 #define SDIF_CTRL_DMA_RESET_MASK (0x4U) macro
13533 … (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54016/
DLPC54016.h12550 #define SDIF_CTRL_DMA_RESET_MASK (0x4U) macro
12553 … (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54606/
DLPC54606.h13454 #define SDIF_CTRL_DMA_RESET_MASK (0x4U) macro
13458 … (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54628/
DLPC54628.h14172 #define SDIF_CTRL_DMA_RESET_MASK (0x4U) macro
14176 … (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54618/
DLPC54618.h14174 #define SDIF_CTRL_DMA_RESET_MASK (0x4U) macro
14178 … (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54S016/
DLPC54S016.h13256 #define SDIF_CTRL_DMA_RESET_MASK (0x4U) macro
13259 … (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54608/
DLPC54608.h14097 #define SDIF_CTRL_DMA_RESET_MASK (0x4U) macro
14101 … (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54S018M/
DLPC54S018M.h14658 #define SDIF_CTRL_DMA_RESET_MASK (0x4U) macro
14662 … (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54S018/
DLPC54S018.h14658 #define SDIF_CTRL_DMA_RESET_MASK (0x4U) macro
14662 … (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54018/
DLPC54018.h13866 #define SDIF_CTRL_DMA_RESET_MASK (0x4U) macro
13870 … (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54018M/
DLPC54018M.h13866 #define SDIF_CTRL_DMA_RESET_MASK (0x4U) macro
13870 … (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC5528/
DLPC5528.h17213 #define SDIF_CTRL_DMA_RESET_MASK (0x4U) macro
17217 … (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC5526/
DLPC5526.h17213 #define SDIF_CTRL_DMA_RESET_MASK (0x4U) macro
17217 … (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC55S26/
DLPC55S26.h18869 #define SDIF_CTRL_DMA_RESET_MASK (0x4U) macro
18873 … (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC55S28/
DLPC55S28.h18869 #define SDIF_CTRL_DMA_RESET_MASK (0x4U) macro
18873 … (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC55S66/
DLPC55S66_cm33_core0.h19467 #define SDIF_CTRL_DMA_RESET_MASK (0x4U) macro
19471 … (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK)
DLPC55S66_cm33_core1.h19467 #define SDIF_CTRL_DMA_RESET_MASK (0x4U) macro
19471 … (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC55S69/
DLPC55S69_cm33_core1.h19467 #define SDIF_CTRL_DMA_RESET_MASK (0x4U) macro
19471 … (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK)
DLPC55S69_cm33_core0.h19467 #define SDIF_CTRL_DMA_RESET_MASK (0x4U) macro
19471 … (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK)