1 /*
2 * Copyright 2021-2023 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /**
8 * @file SchM_Wdg.c
9 * @version 1.0.0
10 *
11 * @brief AUTOSAR Rte - module implementation
12 * @details This module implements stubs for the AUTOSAR Rte
13 * This file contains sample code only. It is not part of the production code deliverables.
14 *
15 * @addtogroup RTE_MODULE
16 * @{
17 */
18
19 #ifdef __cplusplus
20 extern "C"{
21 #endif
22
23 /*==================================================================================================
24 * INCLUDE FILES
25 * 1) system and project includes
26 * 2) needed interfaces from external units
27 * 3) internal and external interfaces from this unit
28 ==================================================================================================*/
29 #include "Std_Types.h"
30 #include "Mcal.h"
31 #include "OsIf.h"
32 #include "SchM_Wdg.h"
33 #ifdef MCAL_TESTING_ENVIRONMENT
34 #include "EUnit.h" /* EUnit Test Suite */
35 #endif
36
37 /*==================================================================================================
38 * SOURCE FILE VERSION INFORMATION
39 ==================================================================================================*/
40 #define SCHM_WDG_AR_RELEASE_MAJOR_VERSION_C 4
41 #define SCHM_WDG_AR_RELEASE_MINOR_VERSION_C 7
42 #define SCHM_WDG_AR_RELEASE_REVISION_VERSION_C 0
43 #define SCHM_WDG_SW_MAJOR_VERSION_C 1
44 #define SCHM_WDG_SW_MINOR_VERSION_C 0
45 #define SCHM_WDG_SW_PATCH_VERSION_C 0
46
47 /*==================================================================================================
48 * LOCAL CONSTANTS
49 ==================================================================================================*/
50 #ifdef MCAL_PLATFORM_ARM
51 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
52 #define ISR_STATE_MASK ((uint32)0x000000C0UL) /**< @brief DAIF bit I and F */
53 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
54 #define ISR_STATE_MASK ((uint32)0x00000080UL) /**< @brief CPSR bit I */
55 #else
56 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
57 #define ISR_STATE_MASK ((uint32)0x000000FFUL) /**< @brief BASEPRI[7:0] mask */
58 #else
59 #define ISR_STATE_MASK ((uint32)0x00000001UL) /**< @brief PRIMASK bit 0 */
60 #endif
61 #endif
62 #else
63 #ifdef MCAL_PLATFORM_S12
64 #define ISR_STATE_MASK ((uint32)0x00000010UL) /**< @brief I bit of CCR */
65 #else
66 #define ISR_STATE_MASK ((uint32)0x00008000UL) /**< @brief EE bit of MSR */
67 #endif
68 #endif
69 /*==================================================================================================
70 * LOCAL MACROS
71 ==================================================================================================*/
72 #ifdef MCAL_PLATFORM_ARM
73 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
74 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK))
75 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
76 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK))
77 #else
78 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
79 #endif
80 #else
81 #ifdef MCAL_PLATFORM_S12
82 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
83 #else
84 #define ISR_ON(msr) (uint32)((uint32)(msr) & (uint32)(ISR_STATE_MASK))
85 #endif
86 #endif
87
88 /*==================================================================================================
89 * FILE VERSION CHECKS
90 ==================================================================================================*/
91
92 /*==================================================================================================
93 * LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
94 ==================================================================================================*/
95
96
97 /*==================================================================================================
98 * LOCAL VARIABLES
99 ==================================================================================================*/
100 #define RTE_START_SEC_VAR_CLEARED_32_NO_CACHEABLE
101 #include "Rte_MemMap.h"
102 VAR_SEC_NOCACHE(msr_WDG_EXCLUSIVE_AREA_00) static volatile uint32 msr_WDG_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
103 VAR_SEC_NOCACHE(reentry_guard_WDG_EXCLUSIVE_AREA_00) static volatile uint32 reentry_guard_WDG_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
104 VAR_SEC_NOCACHE(msr_WDG_EXCLUSIVE_AREA_01) static volatile uint32 msr_WDG_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
105 VAR_SEC_NOCACHE(reentry_guard_WDG_EXCLUSIVE_AREA_01) static volatile uint32 reentry_guard_WDG_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
106 VAR_SEC_NOCACHE(msr_WDG_EXCLUSIVE_AREA_02) static volatile uint32 msr_WDG_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
107 VAR_SEC_NOCACHE(reentry_guard_WDG_EXCLUSIVE_AREA_02) static volatile uint32 reentry_guard_WDG_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
108 VAR_SEC_NOCACHE(msr_WDG_EXCLUSIVE_AREA_03) static volatile uint32 msr_WDG_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
109 VAR_SEC_NOCACHE(reentry_guard_WDG_EXCLUSIVE_AREA_03) static volatile uint32 reentry_guard_WDG_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
110 VAR_SEC_NOCACHE(msr_WDG_EXCLUSIVE_AREA_04) static volatile uint32 msr_WDG_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
111 VAR_SEC_NOCACHE(reentry_guard_WDG_EXCLUSIVE_AREA_04) static volatile uint32 reentry_guard_WDG_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
112 VAR_SEC_NOCACHE(msr_WDG_EXCLUSIVE_AREA_05) static volatile uint32 msr_WDG_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
113 VAR_SEC_NOCACHE(reentry_guard_WDG_EXCLUSIVE_AREA_05) static volatile uint32 reentry_guard_WDG_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
114 VAR_SEC_NOCACHE(msr_WDG_EXCLUSIVE_AREA_06) static volatile uint32 msr_WDG_EXCLUSIVE_AREA_06[NUMBER_OF_CORES];
115 VAR_SEC_NOCACHE(reentry_guard_WDG_EXCLUSIVE_AREA_06) static volatile uint32 reentry_guard_WDG_EXCLUSIVE_AREA_06[NUMBER_OF_CORES];
116 VAR_SEC_NOCACHE(msr_WDG_EXCLUSIVE_AREA_07) static volatile uint32 msr_WDG_EXCLUSIVE_AREA_07[NUMBER_OF_CORES];
117 VAR_SEC_NOCACHE(reentry_guard_WDG_EXCLUSIVE_AREA_07) static volatile uint32 reentry_guard_WDG_EXCLUSIVE_AREA_07[NUMBER_OF_CORES];
118 VAR_SEC_NOCACHE(msr_WDG_EXCLUSIVE_AREA_08) static volatile uint32 msr_WDG_EXCLUSIVE_AREA_08[NUMBER_OF_CORES];
119 VAR_SEC_NOCACHE(reentry_guard_WDG_EXCLUSIVE_AREA_08) static volatile uint32 reentry_guard_WDG_EXCLUSIVE_AREA_08[NUMBER_OF_CORES];
120 VAR_SEC_NOCACHE(msr_WDG_EXCLUSIVE_AREA_09) static volatile uint32 msr_WDG_EXCLUSIVE_AREA_09[NUMBER_OF_CORES];
121 VAR_SEC_NOCACHE(reentry_guard_WDG_EXCLUSIVE_AREA_09) static volatile uint32 reentry_guard_WDG_EXCLUSIVE_AREA_09[NUMBER_OF_CORES];
122 VAR_SEC_NOCACHE(msr_WDG_EXCLUSIVE_AREA_10) static volatile uint32 msr_WDG_EXCLUSIVE_AREA_10[NUMBER_OF_CORES];
123 VAR_SEC_NOCACHE(reentry_guard_WDG_EXCLUSIVE_AREA_10) static volatile uint32 reentry_guard_WDG_EXCLUSIVE_AREA_10[NUMBER_OF_CORES];
124 VAR_SEC_NOCACHE(msr_WDG_EXCLUSIVE_AREA_11) static volatile uint32 msr_WDG_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
125 VAR_SEC_NOCACHE(reentry_guard_WDG_EXCLUSIVE_AREA_11) static volatile uint32 reentry_guard_WDG_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
126 VAR_SEC_NOCACHE(msr_WDG_EXCLUSIVE_AREA_12) static volatile uint32 msr_WDG_EXCLUSIVE_AREA_12[NUMBER_OF_CORES];
127 VAR_SEC_NOCACHE(reentry_guard_WDG_EXCLUSIVE_AREA_12) static volatile uint32 reentry_guard_WDG_EXCLUSIVE_AREA_12[NUMBER_OF_CORES];
128 VAR_SEC_NOCACHE(msr_WDG_EXCLUSIVE_AREA_13) static volatile uint32 msr_WDG_EXCLUSIVE_AREA_13[NUMBER_OF_CORES];
129 VAR_SEC_NOCACHE(reentry_guard_WDG_EXCLUSIVE_AREA_13) static volatile uint32 reentry_guard_WDG_EXCLUSIVE_AREA_13[NUMBER_OF_CORES];
130 VAR_SEC_NOCACHE(msr_WDG_EXCLUSIVE_AREA_14) static volatile uint32 msr_WDG_EXCLUSIVE_AREA_14[NUMBER_OF_CORES];
131 VAR_SEC_NOCACHE(reentry_guard_WDG_EXCLUSIVE_AREA_14) static volatile uint32 reentry_guard_WDG_EXCLUSIVE_AREA_14[NUMBER_OF_CORES];
132
133 #define RTE_STOP_SEC_VAR_CLEARED_32_NO_CACHEABLE
134 #include "Rte_MemMap.h"
135 /*==================================================================================================
136 * GLOBAL CONSTANTS
137 ==================================================================================================*/
138
139
140 /*==================================================================================================
141 * GLOBAL VARIABLES
142 ==================================================================================================*/
143
144 /*==================================================================================================
145 * LOCAL FUNCTION PROTOTYPES
146 ==================================================================================================*/
147
148 #ifndef _COSMIC_C_S32ZE_
149 /*================================================================================================*/
150 /**
151 * @brief This function returns the MSR register value (32 bits).
152 * @details This function returns the MSR register value (32 bits).
153 *
154 * @param[in] void No input parameters
155 * @return uint32 msr This function returns the MSR register value (32 bits).
156 *
157 * @pre None
158 * @post None
159 *
160 */
161 uint32 Wdg_schm_read_msr(void);
162 #endif /*ifndef _COSMIC_C_S32ZE_*/
163 /*==================================================================================================
164 * LOCAL FUNCTIONS
165 ==================================================================================================*/
166 #define RTE_START_SEC_CODE
167 #include "Rte_MemMap.h"
168
169 #if (defined(_GREENHILLS_C_S32ZE_) || defined(_CODEWARRIOR_C_S32ZE_))
170 /*================================================================================================*/
171 /**
172 * @brief This macro returns the MSR register value (32 bits).
173 * @details This macro function implementation returns the MSR register value in r3 (32 bits).
174 *
175 * @pre None
176 * @post None
177 *
178 */
179 #ifdef MCAL_PLATFORM_ARM
180 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
Wdg_schm_read_msr(void)181 ASM_KEYWORD uint32 Wdg_schm_read_msr(void)
182 {
183 mrs x0, S3_3_c4_c2_1
184 }
185 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
Wdg_schm_read_msr(void)186 ASM_KEYWORD uint32 Wdg_schm_read_msr(void)
187 {
188 mrs r0, CPSR
189 }
190 #else
Wdg_schm_read_msr(void)191 ASM_KEYWORD uint32 Wdg_schm_read_msr(void)
192 {
193 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
194 mrs r0, BASEPRI
195 #else
196 mrs r0, PRIMASK
197 #endif
198 }
199 #endif
200 #else
201 #ifdef MCAL_PLATFORM_S12
Wdg_schm_read_msr(void)202 ASM_KEYWORD uint32 Wdg_schm_read_msr(void)
203 {
204 tfr ccr, d6
205 }
206 #else
Wdg_schm_read_msr(void)207 ASM_KEYWORD uint32 Wdg_schm_read_msr(void)
208 {
209 mfmsr r3
210 }
211 #endif
212 #endif
213 #endif /*#ifdef GHS||CW*/
214
215 #ifdef _DIABDATA_C_S32ZE_
216 /**
217 * @brief This function returns the MSR register value (32 bits).
218 * @details This function returns the MSR register value (32 bits).
219 *
220 * @param[in] void No input parameters
221 * @return uint32 msr This function returns the MSR register value (32 bits).
222 *
223 * @pre None
224 * @post None
225 *
226 */
227 #ifdef MCAL_PLATFORM_ARM
Wdg_schm_read_msr(void)228 uint32 Wdg_schm_read_msr(void)
229 {
230 register uint32 reg_tmp;
231 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
232 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
233 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
234 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
235 #else
236 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
237 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
238 #else
239 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
240 #endif
241 #endif
242 return (uint32)reg_tmp;
243 }
244 #else
Wdg_schm_read_msr(void)245 ASM_KEYWORD uint32 Wdg_schm_read_msr(void)
246 {
247 mfmsr r3
248 }
249 #endif /* MCAL_PLATFORM_ARM */
250
251 #endif /* _DIABDATA_C_S32ZE_*/
252
253 #ifdef _COSMIC_C_S32ZE_
254 /*================================================================================================*/
255 /**
256 * @brief This function returns the MSR register value (32 bits).
257 * @details This function returns the MSR register value (32 bits).
258 *
259 * @param[in] void No input parameters
260 * @return uint32 msr This function returns the MSR register value (32 bits).
261 *
262 * @pre None
263 * @post None
264 *
265 */
266
267 #ifdef MCAL_PLATFORM_S12
268 #define Wdg_schm_read_msr() ASM_KEYWORD("tfr ccr, d6")
269 #else
270 #define Wdg_schm_read_msr() ASM_KEYWORD("mfmsr r3")
271 #endif
272
273 #endif /*Cosmic compiler only*/
274
275
276 #ifdef _HITECH_C_S32ZE_
277 /*================================================================================================*/
278 /**
279 * @brief This function returns the MSR register value (32 bits).
280 * @details This function returns the MSR register value (32 bits).
281 *
282 * @param[in] void No input parameters
283 * @return uint32 msr This function returns the MSR register value (32 bits).
284 *
285 * @pre None
286 * @post None
287 *
288 */
Wdg_schm_read_msr(void)289 uint32 Wdg_schm_read_msr(void)
290 {
291 uint32 result;
292 __asm volatile("mfmsr %0" : "=r" (result) :);
293 return result;
294 }
295
296 #endif /*HighTec compiler only*/
297 /*================================================================================================*/
298 #ifdef _LINARO_C_S32ZE_
299 /**
300 * @brief This function returns the MSR register value (32 bits).
301 * @details This function returns the MSR register value (32 bits).
302 *
303 * @param[in] void No input parameters
304 * @return uint32 msr This function returns the MSR register value (32 bits).
305 *
306 * @pre None
307 * @post None
308 *
309 */
Wdg_schm_read_msr(void)310 uint32 Wdg_schm_read_msr(void)
311 {
312 register uint32 reg_tmp;
313 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
314 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
315 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
316 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
317 #else
318 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
319 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
320 #else
321 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
322 #endif
323 #endif
324 return (uint32)reg_tmp;
325 }
326 #endif /* _LINARO_C_S32ZE_*/
327 /*================================================================================================*/
328
329 #ifdef _ARM_DS5_C_S32ZE_
330 /**
331 * @brief This function returns the MSR register value (32 bits).
332 * @details This function returns the MSR register value (32 bits).
333 *
334 * @param[in] void No input parameters
335 * @return uint32 msr This function returns the MSR register value (32 bits).
336 *
337 * @pre None
338 * @post None
339 *
340 */
Wdg_schm_read_msr(void)341 uint32 Wdg_schm_read_msr(void)
342 {
343 register uint32 reg_tmp;
344 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
345 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
346 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
347 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
348 #else
349 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
350 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
351 #else
352 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
353 #endif
354 #endif
355 return (uint32)reg_tmp;
356 }
357 #endif /* _ARM_DS5_C_S32ZE_ */
358
359 #ifdef _IAR_C_S32ZE_
360 /**
361 * @brief This function returns the MSR register value (32 bits).
362 * @details This function returns the MSR register value (32 bits).
363 *
364 * @param[in] void No input parameters
365 * @return uint32 msr This function returns the MSR register value (32 bits).
366 *
367 * @pre None
368 * @post None
369 *
370 */
Wdg_schm_read_msr(void)371 uint32 Wdg_schm_read_msr(void)
372 {
373 register uint32 reg_tmp;
374
375 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
376 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
377 #else
378 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
379 #endif
380
381 return (uint32)reg_tmp;
382 }
383 #endif /* _IAR_C_S32ZE_ */
384
385 #define RTE_STOP_SEC_CODE
386 #include "Rte_MemMap.h"
387
388 /*==================================================================================================
389 * GLOBAL FUNCTIONS
390 ==================================================================================================*/
391 #define RTE_START_SEC_CODE
392 #include "Rte_MemMap.h"
393
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_00(void)394 void SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_00(void)
395 {
396 uint32 msr;
397 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
398
399 if(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_00[u32CoreId])
400 {
401 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
402 msr = OsIf_Trusted_Call_Return(Wdg_schm_read_msr);
403 #else
404 msr = Wdg_schm_read_msr(); /*read MSR (to store interrupts state)*/
405 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
406 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
407 {
408 OsIf_SuspendAllInterrupts();
409 #ifdef _ARM_DS5_C_S32ZE_
410 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
411 #endif
412 }
413 msr_WDG_EXCLUSIVE_AREA_00[u32CoreId] = msr;
414 }
415 reentry_guard_WDG_EXCLUSIVE_AREA_00[u32CoreId]++;
416 }
417
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_00(void)418 void SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_00(void)
419 {
420 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
421
422 reentry_guard_WDG_EXCLUSIVE_AREA_00[u32CoreId]--;
423 if ((ISR_ON(msr_WDG_EXCLUSIVE_AREA_00[u32CoreId]))&&(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_00[u32CoreId])) /*if interrupts were enabled*/
424 {
425 OsIf_ResumeAllInterrupts();
426 #ifdef _ARM_DS5_C_S32ZE_
427 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
428 #endif
429 }
430 }
431
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_01(void)432 void SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_01(void)
433 {
434 uint32 msr;
435 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
436
437 if(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_01[u32CoreId])
438 {
439 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
440 msr = OsIf_Trusted_Call_Return(Wdg_schm_read_msr);
441 #else
442 msr = Wdg_schm_read_msr(); /*read MSR (to store interrupts state)*/
443 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
444 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
445 {
446 OsIf_SuspendAllInterrupts();
447 #ifdef _ARM_DS5_C_S32ZE_
448 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
449 #endif
450 }
451 msr_WDG_EXCLUSIVE_AREA_01[u32CoreId] = msr;
452 }
453 reentry_guard_WDG_EXCLUSIVE_AREA_01[u32CoreId]++;
454 }
455
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_01(void)456 void SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_01(void)
457 {
458 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
459
460 reentry_guard_WDG_EXCLUSIVE_AREA_01[u32CoreId]--;
461 if ((ISR_ON(msr_WDG_EXCLUSIVE_AREA_01[u32CoreId]))&&(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_01[u32CoreId])) /*if interrupts were enabled*/
462 {
463 OsIf_ResumeAllInterrupts();
464 #ifdef _ARM_DS5_C_S32ZE_
465 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
466 #endif
467 }
468 }
469
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_02(void)470 void SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_02(void)
471 {
472 uint32 msr;
473 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
474
475 if(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_02[u32CoreId])
476 {
477 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
478 msr = OsIf_Trusted_Call_Return(Wdg_schm_read_msr);
479 #else
480 msr = Wdg_schm_read_msr(); /*read MSR (to store interrupts state)*/
481 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
482 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
483 {
484 OsIf_SuspendAllInterrupts();
485 #ifdef _ARM_DS5_C_S32ZE_
486 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
487 #endif
488 }
489 msr_WDG_EXCLUSIVE_AREA_02[u32CoreId] = msr;
490 }
491 reentry_guard_WDG_EXCLUSIVE_AREA_02[u32CoreId]++;
492 }
493
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_02(void)494 void SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_02(void)
495 {
496 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
497
498 reentry_guard_WDG_EXCLUSIVE_AREA_02[u32CoreId]--;
499 if ((ISR_ON(msr_WDG_EXCLUSIVE_AREA_02[u32CoreId]))&&(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_02[u32CoreId])) /*if interrupts were enabled*/
500 {
501 OsIf_ResumeAllInterrupts();
502 #ifdef _ARM_DS5_C_S32ZE_
503 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
504 #endif
505 }
506 }
507
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_03(void)508 void SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_03(void)
509 {
510 uint32 msr;
511 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
512
513 if(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_03[u32CoreId])
514 {
515 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
516 msr = OsIf_Trusted_Call_Return(Wdg_schm_read_msr);
517 #else
518 msr = Wdg_schm_read_msr(); /*read MSR (to store interrupts state)*/
519 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
520 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
521 {
522 OsIf_SuspendAllInterrupts();
523 #ifdef _ARM_DS5_C_S32ZE_
524 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
525 #endif
526 }
527 msr_WDG_EXCLUSIVE_AREA_03[u32CoreId] = msr;
528 }
529 reentry_guard_WDG_EXCLUSIVE_AREA_03[u32CoreId]++;
530 }
531
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_03(void)532 void SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_03(void)
533 {
534 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
535
536 reentry_guard_WDG_EXCLUSIVE_AREA_03[u32CoreId]--;
537 if ((ISR_ON(msr_WDG_EXCLUSIVE_AREA_03[u32CoreId]))&&(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_03[u32CoreId])) /*if interrupts were enabled*/
538 {
539 OsIf_ResumeAllInterrupts();
540 #ifdef _ARM_DS5_C_S32ZE_
541 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
542 #endif
543 }
544 }
545
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_04(void)546 void SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_04(void)
547 {
548 uint32 msr;
549 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
550
551 if(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_04[u32CoreId])
552 {
553 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
554 msr = OsIf_Trusted_Call_Return(Wdg_schm_read_msr);
555 #else
556 msr = Wdg_schm_read_msr(); /*read MSR (to store interrupts state)*/
557 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
558 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
559 {
560 OsIf_SuspendAllInterrupts();
561 #ifdef _ARM_DS5_C_S32ZE_
562 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
563 #endif
564 }
565 msr_WDG_EXCLUSIVE_AREA_04[u32CoreId] = msr;
566 }
567 reentry_guard_WDG_EXCLUSIVE_AREA_04[u32CoreId]++;
568 }
569
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_04(void)570 void SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_04(void)
571 {
572 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
573
574 reentry_guard_WDG_EXCLUSIVE_AREA_04[u32CoreId]--;
575 if ((ISR_ON(msr_WDG_EXCLUSIVE_AREA_04[u32CoreId]))&&(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_04[u32CoreId])) /*if interrupts were enabled*/
576 {
577 OsIf_ResumeAllInterrupts();
578 #ifdef _ARM_DS5_C_S32ZE_
579 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
580 #endif
581 }
582 }
583
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_05(void)584 void SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_05(void)
585 {
586 uint32 msr;
587 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
588
589 if(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_05[u32CoreId])
590 {
591 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
592 msr = OsIf_Trusted_Call_Return(Wdg_schm_read_msr);
593 #else
594 msr = Wdg_schm_read_msr(); /*read MSR (to store interrupts state)*/
595 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
596 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
597 {
598 OsIf_SuspendAllInterrupts();
599 #ifdef _ARM_DS5_C_S32ZE_
600 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
601 #endif
602 }
603 msr_WDG_EXCLUSIVE_AREA_05[u32CoreId] = msr;
604 }
605 reentry_guard_WDG_EXCLUSIVE_AREA_05[u32CoreId]++;
606 }
607
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_05(void)608 void SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_05(void)
609 {
610 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
611
612 reentry_guard_WDG_EXCLUSIVE_AREA_05[u32CoreId]--;
613 if ((ISR_ON(msr_WDG_EXCLUSIVE_AREA_05[u32CoreId]))&&(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_05[u32CoreId])) /*if interrupts were enabled*/
614 {
615 OsIf_ResumeAllInterrupts();
616 #ifdef _ARM_DS5_C_S32ZE_
617 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
618 #endif
619 }
620 }
621
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_06(void)622 void SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_06(void)
623 {
624 uint32 msr;
625 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
626
627 if(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_06[u32CoreId])
628 {
629 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
630 msr = OsIf_Trusted_Call_Return(Wdg_schm_read_msr);
631 #else
632 msr = Wdg_schm_read_msr(); /*read MSR (to store interrupts state)*/
633 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
634 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
635 {
636 OsIf_SuspendAllInterrupts();
637 #ifdef _ARM_DS5_C_S32ZE_
638 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
639 #endif
640 }
641 msr_WDG_EXCLUSIVE_AREA_06[u32CoreId] = msr;
642 }
643 reentry_guard_WDG_EXCLUSIVE_AREA_06[u32CoreId]++;
644 }
645
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_06(void)646 void SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_06(void)
647 {
648 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
649
650 reentry_guard_WDG_EXCLUSIVE_AREA_06[u32CoreId]--;
651 if ((ISR_ON(msr_WDG_EXCLUSIVE_AREA_06[u32CoreId]))&&(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_06[u32CoreId])) /*if interrupts were enabled*/
652 {
653 OsIf_ResumeAllInterrupts();
654 #ifdef _ARM_DS5_C_S32ZE_
655 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
656 #endif
657 }
658 }
659
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_07(void)660 void SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_07(void)
661 {
662 uint32 msr;
663 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
664
665 if(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_07[u32CoreId])
666 {
667 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
668 msr = OsIf_Trusted_Call_Return(Wdg_schm_read_msr);
669 #else
670 msr = Wdg_schm_read_msr(); /*read MSR (to store interrupts state)*/
671 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
672 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
673 {
674 OsIf_SuspendAllInterrupts();
675 #ifdef _ARM_DS5_C_S32ZE_
676 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
677 #endif
678 }
679 msr_WDG_EXCLUSIVE_AREA_07[u32CoreId] = msr;
680 }
681 reentry_guard_WDG_EXCLUSIVE_AREA_07[u32CoreId]++;
682 }
683
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_07(void)684 void SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_07(void)
685 {
686 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
687
688 reentry_guard_WDG_EXCLUSIVE_AREA_07[u32CoreId]--;
689 if ((ISR_ON(msr_WDG_EXCLUSIVE_AREA_07[u32CoreId]))&&(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_07[u32CoreId])) /*if interrupts were enabled*/
690 {
691 OsIf_ResumeAllInterrupts();
692 #ifdef _ARM_DS5_C_S32ZE_
693 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
694 #endif
695 }
696 }
697
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_08(void)698 void SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_08(void)
699 {
700 uint32 msr;
701 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
702
703 if(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_08[u32CoreId])
704 {
705 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
706 msr = OsIf_Trusted_Call_Return(Wdg_schm_read_msr);
707 #else
708 msr = Wdg_schm_read_msr(); /*read MSR (to store interrupts state)*/
709 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
710 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
711 {
712 OsIf_SuspendAllInterrupts();
713 #ifdef _ARM_DS5_C_S32ZE_
714 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
715 #endif
716 }
717 msr_WDG_EXCLUSIVE_AREA_08[u32CoreId] = msr;
718 }
719 reentry_guard_WDG_EXCLUSIVE_AREA_08[u32CoreId]++;
720 }
721
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_08(void)722 void SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_08(void)
723 {
724 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
725
726 reentry_guard_WDG_EXCLUSIVE_AREA_08[u32CoreId]--;
727 if ((ISR_ON(msr_WDG_EXCLUSIVE_AREA_08[u32CoreId]))&&(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_08[u32CoreId])) /*if interrupts were enabled*/
728 {
729 OsIf_ResumeAllInterrupts();
730 #ifdef _ARM_DS5_C_S32ZE_
731 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
732 #endif
733 }
734 }
735
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_09(void)736 void SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_09(void)
737 {
738 uint32 msr;
739 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
740
741 if(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_09[u32CoreId])
742 {
743 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
744 msr = OsIf_Trusted_Call_Return(Wdg_schm_read_msr);
745 #else
746 msr = Wdg_schm_read_msr(); /*read MSR (to store interrupts state)*/
747 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
748 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
749 {
750 OsIf_SuspendAllInterrupts();
751 #ifdef _ARM_DS5_C_S32ZE_
752 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
753 #endif
754 }
755 msr_WDG_EXCLUSIVE_AREA_09[u32CoreId] = msr;
756 }
757 reentry_guard_WDG_EXCLUSIVE_AREA_09[u32CoreId]++;
758 }
759
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_09(void)760 void SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_09(void)
761 {
762 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
763
764 reentry_guard_WDG_EXCLUSIVE_AREA_09[u32CoreId]--;
765 if ((ISR_ON(msr_WDG_EXCLUSIVE_AREA_09[u32CoreId]))&&(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_09[u32CoreId])) /*if interrupts were enabled*/
766 {
767 OsIf_ResumeAllInterrupts();
768 #ifdef _ARM_DS5_C_S32ZE_
769 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
770 #endif
771 }
772 }
773
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_10(void)774 void SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_10(void)
775 {
776 uint32 msr;
777 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
778
779 if(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_10[u32CoreId])
780 {
781 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
782 msr = OsIf_Trusted_Call_Return(Wdg_schm_read_msr);
783 #else
784 msr = Wdg_schm_read_msr(); /*read MSR (to store interrupts state)*/
785 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
786 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
787 {
788 OsIf_SuspendAllInterrupts();
789 #ifdef _ARM_DS5_C_S32ZE_
790 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
791 #endif
792 }
793 msr_WDG_EXCLUSIVE_AREA_10[u32CoreId] = msr;
794 }
795 reentry_guard_WDG_EXCLUSIVE_AREA_10[u32CoreId]++;
796 }
797
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_10(void)798 void SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_10(void)
799 {
800 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
801
802 reentry_guard_WDG_EXCLUSIVE_AREA_10[u32CoreId]--;
803 if ((ISR_ON(msr_WDG_EXCLUSIVE_AREA_10[u32CoreId]))&&(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_10[u32CoreId])) /*if interrupts were enabled*/
804 {
805 OsIf_ResumeAllInterrupts();
806 #ifdef _ARM_DS5_C_S32ZE_
807 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
808 #endif
809 }
810 }
811
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_11(void)812 void SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_11(void)
813 {
814 uint32 msr;
815 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
816
817 if(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_11[u32CoreId])
818 {
819 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
820 msr = OsIf_Trusted_Call_Return(Wdg_schm_read_msr);
821 #else
822 msr = Wdg_schm_read_msr(); /*read MSR (to store interrupts state)*/
823 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
824 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
825 {
826 OsIf_SuspendAllInterrupts();
827 #ifdef _ARM_DS5_C_S32ZE_
828 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
829 #endif
830 }
831 msr_WDG_EXCLUSIVE_AREA_11[u32CoreId] = msr;
832 }
833 reentry_guard_WDG_EXCLUSIVE_AREA_11[u32CoreId]++;
834 }
835
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_11(void)836 void SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_11(void)
837 {
838 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
839
840 reentry_guard_WDG_EXCLUSIVE_AREA_11[u32CoreId]--;
841 if ((ISR_ON(msr_WDG_EXCLUSIVE_AREA_11[u32CoreId]))&&(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_11[u32CoreId])) /*if interrupts were enabled*/
842 {
843 OsIf_ResumeAllInterrupts();
844 #ifdef _ARM_DS5_C_S32ZE_
845 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
846 #endif
847 }
848 }
849
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_12(void)850 void SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_12(void)
851 {
852 uint32 msr;
853 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
854
855 if(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_12[u32CoreId])
856 {
857 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
858 msr = OsIf_Trusted_Call_Return(Wdg_schm_read_msr);
859 #else
860 msr = Wdg_schm_read_msr(); /*read MSR (to store interrupts state)*/
861 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
862 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
863 {
864 OsIf_SuspendAllInterrupts();
865 #ifdef _ARM_DS5_C_S32ZE_
866 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
867 #endif
868 }
869 msr_WDG_EXCLUSIVE_AREA_12[u32CoreId] = msr;
870 }
871 reentry_guard_WDG_EXCLUSIVE_AREA_12[u32CoreId]++;
872 }
873
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_12(void)874 void SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_12(void)
875 {
876 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
877
878 reentry_guard_WDG_EXCLUSIVE_AREA_12[u32CoreId]--;
879 if ((ISR_ON(msr_WDG_EXCLUSIVE_AREA_12[u32CoreId]))&&(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_12[u32CoreId])) /*if interrupts were enabled*/
880 {
881 OsIf_ResumeAllInterrupts();
882 #ifdef _ARM_DS5_C_S32ZE_
883 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
884 #endif
885 }
886 }
887
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_13(void)888 void SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_13(void)
889 {
890 uint32 msr;
891 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
892
893 if(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_13[u32CoreId])
894 {
895 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
896 msr = OsIf_Trusted_Call_Return(Wdg_schm_read_msr);
897 #else
898 msr = Wdg_schm_read_msr(); /*read MSR (to store interrupts state)*/
899 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
900 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
901 {
902 OsIf_SuspendAllInterrupts();
903 #ifdef _ARM_DS5_C_S32ZE_
904 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
905 #endif
906 }
907 msr_WDG_EXCLUSIVE_AREA_13[u32CoreId] = msr;
908 }
909 reentry_guard_WDG_EXCLUSIVE_AREA_13[u32CoreId]++;
910 }
911
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_13(void)912 void SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_13(void)
913 {
914 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
915
916 reentry_guard_WDG_EXCLUSIVE_AREA_13[u32CoreId]--;
917 if ((ISR_ON(msr_WDG_EXCLUSIVE_AREA_13[u32CoreId]))&&(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_13[u32CoreId])) /*if interrupts were enabled*/
918 {
919 OsIf_ResumeAllInterrupts();
920 #ifdef _ARM_DS5_C_S32ZE_
921 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
922 #endif
923 }
924 }
925
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_14(void)926 void SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_14(void)
927 {
928 uint32 msr;
929 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
930
931 if(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_14[u32CoreId])
932 {
933 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
934 msr = OsIf_Trusted_Call_Return(Wdg_schm_read_msr);
935 #else
936 msr = Wdg_schm_read_msr(); /*read MSR (to store interrupts state)*/
937 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
938 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
939 {
940 OsIf_SuspendAllInterrupts();
941 #ifdef _ARM_DS5_C_S32ZE_
942 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
943 #endif
944 }
945 msr_WDG_EXCLUSIVE_AREA_14[u32CoreId] = msr;
946 }
947 reentry_guard_WDG_EXCLUSIVE_AREA_14[u32CoreId]++;
948 }
949
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_14(void)950 void SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_14(void)
951 {
952 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
953
954 reentry_guard_WDG_EXCLUSIVE_AREA_14[u32CoreId]--;
955 if ((ISR_ON(msr_WDG_EXCLUSIVE_AREA_14[u32CoreId]))&&(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_14[u32CoreId])) /*if interrupts were enabled*/
956 {
957 OsIf_ResumeAllInterrupts();
958 #ifdef _ARM_DS5_C_S32ZE_
959 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
960 #endif
961 }
962 }
963
964
965 #ifdef MCAL_TESTING_ENVIRONMENT
966 /**
967 @brief This function checks that all entered exclusive areas were also exited.
968 @details This function checks that all entered exclusive areas were also exited. The check
969 is done by verifying that all reentry_guard_* static variables are back to the
970 zero value.
971
972 @param[in] void No input parameters
973 @return void This function does not return a value. Test asserts are used instead.
974
975 @pre None
976 @post None
977
978 @remarks Covers
979 @remarks Implements
980 */
SchM_Check_wdg(void)981 void SchM_Check_wdg(void)
982 {
983 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
984
985 EU_ASSERT(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_00[u32CoreId]);
986 reentry_guard_WDG_EXCLUSIVE_AREA_00[u32CoreId] = 0UL; /*reset reentry_guard_WDG_EXCLUSIVE_AREA_00 for the next test in the suite*/
987
988 EU_ASSERT(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_01[u32CoreId]);
989 reentry_guard_WDG_EXCLUSIVE_AREA_01[u32CoreId] = 0UL; /*reset reentry_guard_WDG_EXCLUSIVE_AREA_01 for the next test in the suite*/
990
991 EU_ASSERT(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_02[u32CoreId]);
992 reentry_guard_WDG_EXCLUSIVE_AREA_02[u32CoreId] = 0UL; /*reset reentry_guard_WDG_EXCLUSIVE_AREA_02 for the next test in the suite*/
993
994 EU_ASSERT(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_03[u32CoreId]);
995 reentry_guard_WDG_EXCLUSIVE_AREA_03[u32CoreId] = 0UL; /*reset reentry_guard_WDG_EXCLUSIVE_AREA_03 for the next test in the suite*/
996
997 EU_ASSERT(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_04[u32CoreId]);
998 reentry_guard_WDG_EXCLUSIVE_AREA_04[u32CoreId] = 0UL; /*reset reentry_guard_WDG_EXCLUSIVE_AREA_04 for the next test in the suite*/
999
1000 EU_ASSERT(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_05[u32CoreId]);
1001 reentry_guard_WDG_EXCLUSIVE_AREA_05[u32CoreId] = 0UL; /*reset reentry_guard_WDG_EXCLUSIVE_AREA_05 for the next test in the suite*/
1002
1003 EU_ASSERT(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_06[u32CoreId]);
1004 reentry_guard_WDG_EXCLUSIVE_AREA_06[u32CoreId] = 0UL; /*reset reentry_guard_WDG_EXCLUSIVE_AREA_06 for the next test in the suite*/
1005
1006 EU_ASSERT(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_07[u32CoreId]);
1007 reentry_guard_WDG_EXCLUSIVE_AREA_07[u32CoreId] = 0UL; /*reset reentry_guard_WDG_EXCLUSIVE_AREA_07 for the next test in the suite*/
1008
1009 EU_ASSERT(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_08[u32CoreId]);
1010 reentry_guard_WDG_EXCLUSIVE_AREA_08[u32CoreId] = 0UL; /*reset reentry_guard_WDG_EXCLUSIVE_AREA_08 for the next test in the suite*/
1011
1012 EU_ASSERT(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_09[u32CoreId]);
1013 reentry_guard_WDG_EXCLUSIVE_AREA_09[u32CoreId] = 0UL; /*reset reentry_guard_WDG_EXCLUSIVE_AREA_09 for the next test in the suite*/
1014
1015 EU_ASSERT(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_10[u32CoreId]);
1016 reentry_guard_WDG_EXCLUSIVE_AREA_10[u32CoreId] = 0UL; /*reset reentry_guard_WDG_EXCLUSIVE_AREA_10 for the next test in the suite*/
1017
1018 EU_ASSERT(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_11[u32CoreId]);
1019 reentry_guard_WDG_EXCLUSIVE_AREA_11[u32CoreId] = 0UL; /*reset reentry_guard_WDG_EXCLUSIVE_AREA_11 for the next test in the suite*/
1020
1021 EU_ASSERT(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_12[u32CoreId]);
1022 reentry_guard_WDG_EXCLUSIVE_AREA_12[u32CoreId] = 0UL; /*reset reentry_guard_WDG_EXCLUSIVE_AREA_12 for the next test in the suite*/
1023
1024 EU_ASSERT(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_13[u32CoreId]);
1025 reentry_guard_WDG_EXCLUSIVE_AREA_13[u32CoreId] = 0UL; /*reset reentry_guard_WDG_EXCLUSIVE_AREA_13 for the next test in the suite*/
1026
1027 EU_ASSERT(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_14[u32CoreId]);
1028 reentry_guard_WDG_EXCLUSIVE_AREA_14[u32CoreId] = 0UL; /*reset reentry_guard_WDG_EXCLUSIVE_AREA_14 for the next test in the suite*/
1029
1030
1031 }
1032 #endif /*MCAL_TESTING_ENVIRONMENT*/
1033
1034 #define RTE_STOP_SEC_CODE
1035 #include "Rte_MemMap.h"
1036
1037 #ifdef __cplusplus
1038 }
1039 #endif
1040
1041 /** @} */
1042
