1 /*
2 * Copyright 2021-2023 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /**
8 * @file SchM_Spi.c
9 * @version 1.0.0
10 *
11 * @brief AUTOSAR Rte - module implementation
12 * @details This module implements stubs for the AUTOSAR Rte
13 * This file contains sample code only. It is not part of the production code deliverables.
14 *
15 * @addtogroup RTE_MODULE
16 * @{
17 */
18
19 #ifdef __cplusplus
20 extern "C"{
21 #endif
22
23 /*==================================================================================================
24 * INCLUDE FILES
25 * 1) system and project includes
26 * 2) needed interfaces from external units
27 * 3) internal and external interfaces from this unit
28 ==================================================================================================*/
29 #include "Std_Types.h"
30 #include "Mcal.h"
31 #include "OsIf.h"
32 #include "SchM_Spi.h"
33 #ifdef MCAL_TESTING_ENVIRONMENT
34 #include "EUnit.h" /* EUnit Test Suite */
35 #endif
36
37 /*==================================================================================================
38 * SOURCE FILE VERSION INFORMATION
39 ==================================================================================================*/
40 #define SCHM_SPI_AR_RELEASE_MAJOR_VERSION_C 4
41 #define SCHM_SPI_AR_RELEASE_MINOR_VERSION_C 7
42 #define SCHM_SPI_AR_RELEASE_REVISION_VERSION_C 0
43 #define SCHM_SPI_SW_MAJOR_VERSION_C 1
44 #define SCHM_SPI_SW_MINOR_VERSION_C 0
45 #define SCHM_SPI_SW_PATCH_VERSION_C 0
46
47 /*==================================================================================================
48 * LOCAL CONSTANTS
49 ==================================================================================================*/
50 #ifdef MCAL_PLATFORM_ARM
51 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
52 #define ISR_STATE_MASK ((uint32)0x000000C0UL) /**< @brief DAIF bit I and F */
53 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
54 #define ISR_STATE_MASK ((uint32)0x00000080UL) /**< @brief CPSR bit I */
55 #else
56 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
57 #define ISR_STATE_MASK ((uint32)0x000000FFUL) /**< @brief BASEPRI[7:0] mask */
58 #else
59 #define ISR_STATE_MASK ((uint32)0x00000001UL) /**< @brief PRIMASK bit 0 */
60 #endif
61 #endif
62 #else
63 #ifdef MCAL_PLATFORM_S12
64 #define ISR_STATE_MASK ((uint32)0x00000010UL) /**< @brief I bit of CCR */
65 #else
66 #define ISR_STATE_MASK ((uint32)0x00008000UL) /**< @brief EE bit of MSR */
67 #endif
68 #endif
69 /*==================================================================================================
70 * LOCAL MACROS
71 ==================================================================================================*/
72 #ifdef MCAL_PLATFORM_ARM
73 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
74 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK))
75 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
76 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK))
77 #else
78 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
79 #endif
80 #else
81 #ifdef MCAL_PLATFORM_S12
82 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
83 #else
84 #define ISR_ON(msr) (uint32)((uint32)(msr) & (uint32)(ISR_STATE_MASK))
85 #endif
86 #endif
87
88 /*==================================================================================================
89 * FILE VERSION CHECKS
90 ==================================================================================================*/
91
92 /*==================================================================================================
93 * LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
94 ==================================================================================================*/
95
96
97 /*==================================================================================================
98 * LOCAL VARIABLES
99 ==================================================================================================*/
100 #define RTE_START_SEC_VAR_CLEARED_32_NO_CACHEABLE
101 #include "Rte_MemMap.h"
102 VAR_SEC_NOCACHE(msr_SPI_EXCLUSIVE_AREA_00) static volatile uint32 msr_SPI_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
103 VAR_SEC_NOCACHE(reentry_guard_SPI_EXCLUSIVE_AREA_00) static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
104 VAR_SEC_NOCACHE(msr_SPI_EXCLUSIVE_AREA_01) static volatile uint32 msr_SPI_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
105 VAR_SEC_NOCACHE(reentry_guard_SPI_EXCLUSIVE_AREA_01) static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
106 VAR_SEC_NOCACHE(msr_SPI_EXCLUSIVE_AREA_02) static volatile uint32 msr_SPI_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
107 VAR_SEC_NOCACHE(reentry_guard_SPI_EXCLUSIVE_AREA_02) static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
108 VAR_SEC_NOCACHE(msr_SPI_EXCLUSIVE_AREA_03) static volatile uint32 msr_SPI_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
109 VAR_SEC_NOCACHE(reentry_guard_SPI_EXCLUSIVE_AREA_03) static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
110 VAR_SEC_NOCACHE(msr_SPI_EXCLUSIVE_AREA_04) static volatile uint32 msr_SPI_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
111 VAR_SEC_NOCACHE(reentry_guard_SPI_EXCLUSIVE_AREA_04) static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
112 VAR_SEC_NOCACHE(msr_SPI_EXCLUSIVE_AREA_05) static volatile uint32 msr_SPI_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
113 VAR_SEC_NOCACHE(reentry_guard_SPI_EXCLUSIVE_AREA_05) static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
114 VAR_SEC_NOCACHE(msr_SPI_EXCLUSIVE_AREA_06) static volatile uint32 msr_SPI_EXCLUSIVE_AREA_06[NUMBER_OF_CORES];
115 VAR_SEC_NOCACHE(reentry_guard_SPI_EXCLUSIVE_AREA_06) static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_06[NUMBER_OF_CORES];
116 VAR_SEC_NOCACHE(msr_SPI_EXCLUSIVE_AREA_07) static volatile uint32 msr_SPI_EXCLUSIVE_AREA_07[NUMBER_OF_CORES];
117 VAR_SEC_NOCACHE(reentry_guard_SPI_EXCLUSIVE_AREA_07) static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_07[NUMBER_OF_CORES];
118 VAR_SEC_NOCACHE(msr_SPI_EXCLUSIVE_AREA_08) static volatile uint32 msr_SPI_EXCLUSIVE_AREA_08[NUMBER_OF_CORES];
119 VAR_SEC_NOCACHE(reentry_guard_SPI_EXCLUSIVE_AREA_08) static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_08[NUMBER_OF_CORES];
120 VAR_SEC_NOCACHE(msr_SPI_EXCLUSIVE_AREA_09) static volatile uint32 msr_SPI_EXCLUSIVE_AREA_09[NUMBER_OF_CORES];
121 VAR_SEC_NOCACHE(reentry_guard_SPI_EXCLUSIVE_AREA_09) static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_09[NUMBER_OF_CORES];
122 VAR_SEC_NOCACHE(msr_SPI_EXCLUSIVE_AREA_10) static volatile uint32 msr_SPI_EXCLUSIVE_AREA_10[NUMBER_OF_CORES];
123 VAR_SEC_NOCACHE(reentry_guard_SPI_EXCLUSIVE_AREA_10) static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_10[NUMBER_OF_CORES];
124 VAR_SEC_NOCACHE(msr_SPI_EXCLUSIVE_AREA_11) static volatile uint32 msr_SPI_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
125 VAR_SEC_NOCACHE(reentry_guard_SPI_EXCLUSIVE_AREA_11) static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
126 VAR_SEC_NOCACHE(msr_SPI_EXCLUSIVE_AREA_12) static volatile uint32 msr_SPI_EXCLUSIVE_AREA_12[NUMBER_OF_CORES];
127 VAR_SEC_NOCACHE(reentry_guard_SPI_EXCLUSIVE_AREA_12) static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_12[NUMBER_OF_CORES];
128 VAR_SEC_NOCACHE(msr_SPI_EXCLUSIVE_AREA_13) static volatile uint32 msr_SPI_EXCLUSIVE_AREA_13[NUMBER_OF_CORES];
129 VAR_SEC_NOCACHE(reentry_guard_SPI_EXCLUSIVE_AREA_13) static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_13[NUMBER_OF_CORES];
130 VAR_SEC_NOCACHE(msr_SPI_EXCLUSIVE_AREA_14) static volatile uint32 msr_SPI_EXCLUSIVE_AREA_14[NUMBER_OF_CORES];
131 VAR_SEC_NOCACHE(reentry_guard_SPI_EXCLUSIVE_AREA_14) static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_14[NUMBER_OF_CORES];
132 VAR_SEC_NOCACHE(msr_SPI_EXCLUSIVE_AREA_15) static volatile uint32 msr_SPI_EXCLUSIVE_AREA_15[NUMBER_OF_CORES];
133 VAR_SEC_NOCACHE(reentry_guard_SPI_EXCLUSIVE_AREA_15) static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_15[NUMBER_OF_CORES];
134 VAR_SEC_NOCACHE(msr_SPI_EXCLUSIVE_AREA_16) static volatile uint32 msr_SPI_EXCLUSIVE_AREA_16[NUMBER_OF_CORES];
135 VAR_SEC_NOCACHE(reentry_guard_SPI_EXCLUSIVE_AREA_16) static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_16[NUMBER_OF_CORES];
136 VAR_SEC_NOCACHE(msr_SPI_EXCLUSIVE_AREA_17) static volatile uint32 msr_SPI_EXCLUSIVE_AREA_17[NUMBER_OF_CORES];
137 VAR_SEC_NOCACHE(reentry_guard_SPI_EXCLUSIVE_AREA_17) static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_17[NUMBER_OF_CORES];
138 VAR_SEC_NOCACHE(msr_SPI_EXCLUSIVE_AREA_18) static volatile uint32 msr_SPI_EXCLUSIVE_AREA_18[NUMBER_OF_CORES];
139 VAR_SEC_NOCACHE(reentry_guard_SPI_EXCLUSIVE_AREA_18) static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_18[NUMBER_OF_CORES];
140
141 #define RTE_STOP_SEC_VAR_CLEARED_32_NO_CACHEABLE
142 #include "Rte_MemMap.h"
143 /*==================================================================================================
144 * GLOBAL CONSTANTS
145 ==================================================================================================*/
146
147
148 /*==================================================================================================
149 * GLOBAL VARIABLES
150 ==================================================================================================*/
151
152 /*==================================================================================================
153 * LOCAL FUNCTION PROTOTYPES
154 ==================================================================================================*/
155
156 #ifndef _COSMIC_C_S32ZE_
157 /*================================================================================================*/
158 /**
159 * @brief This function returns the MSR register value (32 bits).
160 * @details This function returns the MSR register value (32 bits).
161 *
162 * @param[in] void No input parameters
163 * @return uint32 msr This function returns the MSR register value (32 bits).
164 *
165 * @pre None
166 * @post None
167 *
168 */
169 uint32 Spi_schm_read_msr(void);
170 #endif /*ifndef _COSMIC_C_S32ZE_*/
171 /*==================================================================================================
172 * LOCAL FUNCTIONS
173 ==================================================================================================*/
174 #define RTE_START_SEC_CODE
175 #include "Rte_MemMap.h"
176
177 #if (defined(_GREENHILLS_C_S32ZE_) || defined(_CODEWARRIOR_C_S32ZE_))
178 /*================================================================================================*/
179 /**
180 * @brief This macro returns the MSR register value (32 bits).
181 * @details This macro function implementation returns the MSR register value in r3 (32 bits).
182 *
183 * @pre None
184 * @post None
185 *
186 */
187 #ifdef MCAL_PLATFORM_ARM
188 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
Spi_schm_read_msr(void)189 ASM_KEYWORD uint32 Spi_schm_read_msr(void)
190 {
191 mrs x0, S3_3_c4_c2_1
192 }
193 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
Spi_schm_read_msr(void)194 ASM_KEYWORD uint32 Spi_schm_read_msr(void)
195 {
196 mrs r0, CPSR
197 }
198 #else
Spi_schm_read_msr(void)199 ASM_KEYWORD uint32 Spi_schm_read_msr(void)
200 {
201 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
202 mrs r0, BASEPRI
203 #else
204 mrs r0, PRIMASK
205 #endif
206 }
207 #endif
208 #else
209 #ifdef MCAL_PLATFORM_S12
Spi_schm_read_msr(void)210 ASM_KEYWORD uint32 Spi_schm_read_msr(void)
211 {
212 tfr ccr, d6
213 }
214 #else
Spi_schm_read_msr(void)215 ASM_KEYWORD uint32 Spi_schm_read_msr(void)
216 {
217 mfmsr r3
218 }
219 #endif
220 #endif
221 #endif /*#ifdef GHS||CW*/
222
223 #ifdef _DIABDATA_C_S32ZE_
224 /**
225 * @brief This function returns the MSR register value (32 bits).
226 * @details This function returns the MSR register value (32 bits).
227 *
228 * @param[in] void No input parameters
229 * @return uint32 msr This function returns the MSR register value (32 bits).
230 *
231 * @pre None
232 * @post None
233 *
234 */
235 #ifdef MCAL_PLATFORM_ARM
Spi_schm_read_msr(void)236 uint32 Spi_schm_read_msr(void)
237 {
238 register uint32 reg_tmp;
239 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
240 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
241 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
242 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
243 #else
244 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
245 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
246 #else
247 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
248 #endif
249 #endif
250 return (uint32)reg_tmp;
251 }
252 #else
Spi_schm_read_msr(void)253 ASM_KEYWORD uint32 Spi_schm_read_msr(void)
254 {
255 mfmsr r3
256 }
257 #endif /* MCAL_PLATFORM_ARM */
258
259 #endif /* _DIABDATA_C_S32ZE_*/
260
261 #ifdef _COSMIC_C_S32ZE_
262 /*================================================================================================*/
263 /**
264 * @brief This function returns the MSR register value (32 bits).
265 * @details This function returns the MSR register value (32 bits).
266 *
267 * @param[in] void No input parameters
268 * @return uint32 msr This function returns the MSR register value (32 bits).
269 *
270 * @pre None
271 * @post None
272 *
273 */
274
275 #ifdef MCAL_PLATFORM_S12
276 #define Spi_schm_read_msr() ASM_KEYWORD("tfr ccr, d6")
277 #else
278 #define Spi_schm_read_msr() ASM_KEYWORD("mfmsr r3")
279 #endif
280
281 #endif /*Cosmic compiler only*/
282
283
284 #ifdef _HITECH_C_S32ZE_
285 /*================================================================================================*/
286 /**
287 * @brief This function returns the MSR register value (32 bits).
288 * @details This function returns the MSR register value (32 bits).
289 *
290 * @param[in] void No input parameters
291 * @return uint32 msr This function returns the MSR register value (32 bits).
292 *
293 * @pre None
294 * @post None
295 *
296 */
Spi_schm_read_msr(void)297 uint32 Spi_schm_read_msr(void)
298 {
299 uint32 result;
300 __asm volatile("mfmsr %0" : "=r" (result) :);
301 return result;
302 }
303
304 #endif /*HighTec compiler only*/
305 /*================================================================================================*/
306 #ifdef _LINARO_C_S32ZE_
307 /**
308 * @brief This function returns the MSR register value (32 bits).
309 * @details This function returns the MSR register value (32 bits).
310 *
311 * @param[in] void No input parameters
312 * @return uint32 msr This function returns the MSR register value (32 bits).
313 *
314 * @pre None
315 * @post None
316 *
317 */
Spi_schm_read_msr(void)318 uint32 Spi_schm_read_msr(void)
319 {
320 register uint32 reg_tmp;
321 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
322 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
323 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
324 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
325 #else
326 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
327 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
328 #else
329 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
330 #endif
331 #endif
332 return (uint32)reg_tmp;
333 }
334 #endif /* _LINARO_C_S32ZE_*/
335 /*================================================================================================*/
336
337 #ifdef _ARM_DS5_C_S32ZE_
338 /**
339 * @brief This function returns the MSR register value (32 bits).
340 * @details This function returns the MSR register value (32 bits).
341 *
342 * @param[in] void No input parameters
343 * @return uint32 msr This function returns the MSR register value (32 bits).
344 *
345 * @pre None
346 * @post None
347 *
348 */
Spi_schm_read_msr(void)349 uint32 Spi_schm_read_msr(void)
350 {
351 register uint32 reg_tmp;
352 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
353 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
354 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
355 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
356 #else
357 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
358 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
359 #else
360 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
361 #endif
362 #endif
363 return (uint32)reg_tmp;
364 }
365 #endif /* _ARM_DS5_C_S32ZE_ */
366
367 #ifdef _IAR_C_S32ZE_
368 /**
369 * @brief This function returns the MSR register value (32 bits).
370 * @details This function returns the MSR register value (32 bits).
371 *
372 * @param[in] void No input parameters
373 * @return uint32 msr This function returns the MSR register value (32 bits).
374 *
375 * @pre None
376 * @post None
377 *
378 */
Spi_schm_read_msr(void)379 uint32 Spi_schm_read_msr(void)
380 {
381 register uint32 reg_tmp;
382
383 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
384 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
385 #else
386 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
387 #endif
388
389 return (uint32)reg_tmp;
390 }
391 #endif /* _IAR_C_S32ZE_ */
392
393 #define RTE_STOP_SEC_CODE
394 #include "Rte_MemMap.h"
395
396 /*==================================================================================================
397 * GLOBAL FUNCTIONS
398 ==================================================================================================*/
399 #define RTE_START_SEC_CODE
400 #include "Rte_MemMap.h"
401
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_00(void)402 void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_00(void)
403 {
404 uint32 msr;
405 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
406
407 if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_00[u32CoreId])
408 {
409 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
410 msr = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
411 #else
412 msr = Spi_schm_read_msr(); /*read MSR (to store interrupts state)*/
413 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
414 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
415 {
416 OsIf_SuspendAllInterrupts();
417 #ifdef _ARM_DS5_C_S32ZE_
418 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
419 #endif
420 }
421 msr_SPI_EXCLUSIVE_AREA_00[u32CoreId] = msr;
422 }
423 reentry_guard_SPI_EXCLUSIVE_AREA_00[u32CoreId]++;
424 }
425
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_00(void)426 void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_00(void)
427 {
428 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
429
430 reentry_guard_SPI_EXCLUSIVE_AREA_00[u32CoreId]--;
431 if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_00[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_00[u32CoreId])) /*if interrupts were enabled*/
432 {
433 OsIf_ResumeAllInterrupts();
434 #ifdef _ARM_DS5_C_S32ZE_
435 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
436 #endif
437 }
438 }
439
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_01(void)440 void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_01(void)
441 {
442 uint32 msr;
443 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
444
445 if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_01[u32CoreId])
446 {
447 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
448 msr = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
449 #else
450 msr = Spi_schm_read_msr(); /*read MSR (to store interrupts state)*/
451 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
452 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
453 {
454 OsIf_SuspendAllInterrupts();
455 #ifdef _ARM_DS5_C_S32ZE_
456 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
457 #endif
458 }
459 msr_SPI_EXCLUSIVE_AREA_01[u32CoreId] = msr;
460 }
461 reentry_guard_SPI_EXCLUSIVE_AREA_01[u32CoreId]++;
462 }
463
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_01(void)464 void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_01(void)
465 {
466 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
467
468 reentry_guard_SPI_EXCLUSIVE_AREA_01[u32CoreId]--;
469 if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_01[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_01[u32CoreId])) /*if interrupts were enabled*/
470 {
471 OsIf_ResumeAllInterrupts();
472 #ifdef _ARM_DS5_C_S32ZE_
473 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
474 #endif
475 }
476 }
477
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_02(void)478 void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_02(void)
479 {
480 uint32 msr;
481 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
482
483 if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_02[u32CoreId])
484 {
485 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
486 msr = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
487 #else
488 msr = Spi_schm_read_msr(); /*read MSR (to store interrupts state)*/
489 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
490 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
491 {
492 OsIf_SuspendAllInterrupts();
493 #ifdef _ARM_DS5_C_S32ZE_
494 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
495 #endif
496 }
497 msr_SPI_EXCLUSIVE_AREA_02[u32CoreId] = msr;
498 }
499 reentry_guard_SPI_EXCLUSIVE_AREA_02[u32CoreId]++;
500 }
501
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_02(void)502 void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_02(void)
503 {
504 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
505
506 reentry_guard_SPI_EXCLUSIVE_AREA_02[u32CoreId]--;
507 if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_02[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_02[u32CoreId])) /*if interrupts were enabled*/
508 {
509 OsIf_ResumeAllInterrupts();
510 #ifdef _ARM_DS5_C_S32ZE_
511 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
512 #endif
513 }
514 }
515
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_03(void)516 void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_03(void)
517 {
518 uint32 msr;
519 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
520
521 if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_03[u32CoreId])
522 {
523 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
524 msr = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
525 #else
526 msr = Spi_schm_read_msr(); /*read MSR (to store interrupts state)*/
527 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
528 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
529 {
530 OsIf_SuspendAllInterrupts();
531 #ifdef _ARM_DS5_C_S32ZE_
532 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
533 #endif
534 }
535 msr_SPI_EXCLUSIVE_AREA_03[u32CoreId] = msr;
536 }
537 reentry_guard_SPI_EXCLUSIVE_AREA_03[u32CoreId]++;
538 }
539
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_03(void)540 void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_03(void)
541 {
542 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
543
544 reentry_guard_SPI_EXCLUSIVE_AREA_03[u32CoreId]--;
545 if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_03[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_03[u32CoreId])) /*if interrupts were enabled*/
546 {
547 OsIf_ResumeAllInterrupts();
548 #ifdef _ARM_DS5_C_S32ZE_
549 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
550 #endif
551 }
552 }
553
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_04(void)554 void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_04(void)
555 {
556 uint32 msr;
557 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
558
559 if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_04[u32CoreId])
560 {
561 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
562 msr = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
563 #else
564 msr = Spi_schm_read_msr(); /*read MSR (to store interrupts state)*/
565 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
566 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
567 {
568 OsIf_SuspendAllInterrupts();
569 #ifdef _ARM_DS5_C_S32ZE_
570 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
571 #endif
572 }
573 msr_SPI_EXCLUSIVE_AREA_04[u32CoreId] = msr;
574 }
575 reentry_guard_SPI_EXCLUSIVE_AREA_04[u32CoreId]++;
576 }
577
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_04(void)578 void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_04(void)
579 {
580 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
581
582 reentry_guard_SPI_EXCLUSIVE_AREA_04[u32CoreId]--;
583 if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_04[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_04[u32CoreId])) /*if interrupts were enabled*/
584 {
585 OsIf_ResumeAllInterrupts();
586 #ifdef _ARM_DS5_C_S32ZE_
587 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
588 #endif
589 }
590 }
591
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_05(void)592 void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_05(void)
593 {
594 uint32 msr;
595 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
596
597 if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_05[u32CoreId])
598 {
599 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
600 msr = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
601 #else
602 msr = Spi_schm_read_msr(); /*read MSR (to store interrupts state)*/
603 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
604 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
605 {
606 OsIf_SuspendAllInterrupts();
607 #ifdef _ARM_DS5_C_S32ZE_
608 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
609 #endif
610 }
611 msr_SPI_EXCLUSIVE_AREA_05[u32CoreId] = msr;
612 }
613 reentry_guard_SPI_EXCLUSIVE_AREA_05[u32CoreId]++;
614 }
615
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_05(void)616 void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_05(void)
617 {
618 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
619
620 reentry_guard_SPI_EXCLUSIVE_AREA_05[u32CoreId]--;
621 if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_05[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_05[u32CoreId])) /*if interrupts were enabled*/
622 {
623 OsIf_ResumeAllInterrupts();
624 #ifdef _ARM_DS5_C_S32ZE_
625 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
626 #endif
627 }
628 }
629
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_06(void)630 void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_06(void)
631 {
632 uint32 msr;
633 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
634
635 if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_06[u32CoreId])
636 {
637 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
638 msr = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
639 #else
640 msr = Spi_schm_read_msr(); /*read MSR (to store interrupts state)*/
641 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
642 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
643 {
644 OsIf_SuspendAllInterrupts();
645 #ifdef _ARM_DS5_C_S32ZE_
646 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
647 #endif
648 }
649 msr_SPI_EXCLUSIVE_AREA_06[u32CoreId] = msr;
650 }
651 reentry_guard_SPI_EXCLUSIVE_AREA_06[u32CoreId]++;
652 }
653
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_06(void)654 void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_06(void)
655 {
656 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
657
658 reentry_guard_SPI_EXCLUSIVE_AREA_06[u32CoreId]--;
659 if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_06[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_06[u32CoreId])) /*if interrupts were enabled*/
660 {
661 OsIf_ResumeAllInterrupts();
662 #ifdef _ARM_DS5_C_S32ZE_
663 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
664 #endif
665 }
666 }
667
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_07(void)668 void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_07(void)
669 {
670 uint32 msr;
671 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
672
673 if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_07[u32CoreId])
674 {
675 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
676 msr = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
677 #else
678 msr = Spi_schm_read_msr(); /*read MSR (to store interrupts state)*/
679 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
680 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
681 {
682 OsIf_SuspendAllInterrupts();
683 #ifdef _ARM_DS5_C_S32ZE_
684 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
685 #endif
686 }
687 msr_SPI_EXCLUSIVE_AREA_07[u32CoreId] = msr;
688 }
689 reentry_guard_SPI_EXCLUSIVE_AREA_07[u32CoreId]++;
690 }
691
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_07(void)692 void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_07(void)
693 {
694 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
695
696 reentry_guard_SPI_EXCLUSIVE_AREA_07[u32CoreId]--;
697 if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_07[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_07[u32CoreId])) /*if interrupts were enabled*/
698 {
699 OsIf_ResumeAllInterrupts();
700 #ifdef _ARM_DS5_C_S32ZE_
701 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
702 #endif
703 }
704 }
705
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_08(void)706 void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_08(void)
707 {
708 uint32 msr;
709 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
710
711 if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_08[u32CoreId])
712 {
713 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
714 msr = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
715 #else
716 msr = Spi_schm_read_msr(); /*read MSR (to store interrupts state)*/
717 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
718 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
719 {
720 OsIf_SuspendAllInterrupts();
721 #ifdef _ARM_DS5_C_S32ZE_
722 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
723 #endif
724 }
725 msr_SPI_EXCLUSIVE_AREA_08[u32CoreId] = msr;
726 }
727 reentry_guard_SPI_EXCLUSIVE_AREA_08[u32CoreId]++;
728 }
729
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_08(void)730 void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_08(void)
731 {
732 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
733
734 reentry_guard_SPI_EXCLUSIVE_AREA_08[u32CoreId]--;
735 if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_08[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_08[u32CoreId])) /*if interrupts were enabled*/
736 {
737 OsIf_ResumeAllInterrupts();
738 #ifdef _ARM_DS5_C_S32ZE_
739 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
740 #endif
741 }
742 }
743
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_09(void)744 void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_09(void)
745 {
746 uint32 msr;
747 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
748
749 if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_09[u32CoreId])
750 {
751 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
752 msr = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
753 #else
754 msr = Spi_schm_read_msr(); /*read MSR (to store interrupts state)*/
755 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
756 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
757 {
758 OsIf_SuspendAllInterrupts();
759 #ifdef _ARM_DS5_C_S32ZE_
760 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
761 #endif
762 }
763 msr_SPI_EXCLUSIVE_AREA_09[u32CoreId] = msr;
764 }
765 reentry_guard_SPI_EXCLUSIVE_AREA_09[u32CoreId]++;
766 }
767
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_09(void)768 void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_09(void)
769 {
770 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
771
772 reentry_guard_SPI_EXCLUSIVE_AREA_09[u32CoreId]--;
773 if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_09[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_09[u32CoreId])) /*if interrupts were enabled*/
774 {
775 OsIf_ResumeAllInterrupts();
776 #ifdef _ARM_DS5_C_S32ZE_
777 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
778 #endif
779 }
780 }
781
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_10(void)782 void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_10(void)
783 {
784 uint32 msr;
785 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
786
787 if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_10[u32CoreId])
788 {
789 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
790 msr = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
791 #else
792 msr = Spi_schm_read_msr(); /*read MSR (to store interrupts state)*/
793 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
794 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
795 {
796 OsIf_SuspendAllInterrupts();
797 #ifdef _ARM_DS5_C_S32ZE_
798 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
799 #endif
800 }
801 msr_SPI_EXCLUSIVE_AREA_10[u32CoreId] = msr;
802 }
803 reentry_guard_SPI_EXCLUSIVE_AREA_10[u32CoreId]++;
804 }
805
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_10(void)806 void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_10(void)
807 {
808 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
809
810 reentry_guard_SPI_EXCLUSIVE_AREA_10[u32CoreId]--;
811 if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_10[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_10[u32CoreId])) /*if interrupts were enabled*/
812 {
813 OsIf_ResumeAllInterrupts();
814 #ifdef _ARM_DS5_C_S32ZE_
815 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
816 #endif
817 }
818 }
819
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_11(void)820 void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_11(void)
821 {
822 uint32 msr;
823 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
824
825 if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_11[u32CoreId])
826 {
827 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
828 msr = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
829 #else
830 msr = Spi_schm_read_msr(); /*read MSR (to store interrupts state)*/
831 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
832 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
833 {
834 OsIf_SuspendAllInterrupts();
835 #ifdef _ARM_DS5_C_S32ZE_
836 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
837 #endif
838 }
839 msr_SPI_EXCLUSIVE_AREA_11[u32CoreId] = msr;
840 }
841 reentry_guard_SPI_EXCLUSIVE_AREA_11[u32CoreId]++;
842 }
843
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_11(void)844 void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_11(void)
845 {
846 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
847
848 reentry_guard_SPI_EXCLUSIVE_AREA_11[u32CoreId]--;
849 if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_11[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_11[u32CoreId])) /*if interrupts were enabled*/
850 {
851 OsIf_ResumeAllInterrupts();
852 #ifdef _ARM_DS5_C_S32ZE_
853 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
854 #endif
855 }
856 }
857
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_12(void)858 void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_12(void)
859 {
860 uint32 msr;
861 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
862
863 if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_12[u32CoreId])
864 {
865 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
866 msr = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
867 #else
868 msr = Spi_schm_read_msr(); /*read MSR (to store interrupts state)*/
869 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
870 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
871 {
872 OsIf_SuspendAllInterrupts();
873 #ifdef _ARM_DS5_C_S32ZE_
874 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
875 #endif
876 }
877 msr_SPI_EXCLUSIVE_AREA_12[u32CoreId] = msr;
878 }
879 reentry_guard_SPI_EXCLUSIVE_AREA_12[u32CoreId]++;
880 }
881
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_12(void)882 void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_12(void)
883 {
884 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
885
886 reentry_guard_SPI_EXCLUSIVE_AREA_12[u32CoreId]--;
887 if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_12[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_12[u32CoreId])) /*if interrupts were enabled*/
888 {
889 OsIf_ResumeAllInterrupts();
890 #ifdef _ARM_DS5_C_S32ZE_
891 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
892 #endif
893 }
894 }
895
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_13(void)896 void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_13(void)
897 {
898 uint32 msr;
899 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
900
901 if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_13[u32CoreId])
902 {
903 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
904 msr = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
905 #else
906 msr = Spi_schm_read_msr(); /*read MSR (to store interrupts state)*/
907 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
908 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
909 {
910 OsIf_SuspendAllInterrupts();
911 #ifdef _ARM_DS5_C_S32ZE_
912 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
913 #endif
914 }
915 msr_SPI_EXCLUSIVE_AREA_13[u32CoreId] = msr;
916 }
917 reentry_guard_SPI_EXCLUSIVE_AREA_13[u32CoreId]++;
918 }
919
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_13(void)920 void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_13(void)
921 {
922 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
923
924 reentry_guard_SPI_EXCLUSIVE_AREA_13[u32CoreId]--;
925 if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_13[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_13[u32CoreId])) /*if interrupts were enabled*/
926 {
927 OsIf_ResumeAllInterrupts();
928 #ifdef _ARM_DS5_C_S32ZE_
929 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
930 #endif
931 }
932 }
933
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_14(void)934 void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_14(void)
935 {
936 uint32 msr;
937 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
938
939 if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_14[u32CoreId])
940 {
941 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
942 msr = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
943 #else
944 msr = Spi_schm_read_msr(); /*read MSR (to store interrupts state)*/
945 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
946 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
947 {
948 OsIf_SuspendAllInterrupts();
949 #ifdef _ARM_DS5_C_S32ZE_
950 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
951 #endif
952 }
953 msr_SPI_EXCLUSIVE_AREA_14[u32CoreId] = msr;
954 }
955 reentry_guard_SPI_EXCLUSIVE_AREA_14[u32CoreId]++;
956 }
957
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_14(void)958 void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_14(void)
959 {
960 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
961
962 reentry_guard_SPI_EXCLUSIVE_AREA_14[u32CoreId]--;
963 if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_14[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_14[u32CoreId])) /*if interrupts were enabled*/
964 {
965 OsIf_ResumeAllInterrupts();
966 #ifdef _ARM_DS5_C_S32ZE_
967 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
968 #endif
969 }
970 }
971
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_15(void)972 void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_15(void)
973 {
974 uint32 msr;
975 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
976
977 if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_15[u32CoreId])
978 {
979 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
980 msr = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
981 #else
982 msr = Spi_schm_read_msr(); /*read MSR (to store interrupts state)*/
983 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
984 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
985 {
986 OsIf_SuspendAllInterrupts();
987 #ifdef _ARM_DS5_C_S32ZE_
988 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
989 #endif
990 }
991 msr_SPI_EXCLUSIVE_AREA_15[u32CoreId] = msr;
992 }
993 reentry_guard_SPI_EXCLUSIVE_AREA_15[u32CoreId]++;
994 }
995
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_15(void)996 void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_15(void)
997 {
998 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
999
1000 reentry_guard_SPI_EXCLUSIVE_AREA_15[u32CoreId]--;
1001 if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_15[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_15[u32CoreId])) /*if interrupts were enabled*/
1002 {
1003 OsIf_ResumeAllInterrupts();
1004 #ifdef _ARM_DS5_C_S32ZE_
1005 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1006 #endif
1007 }
1008 }
1009
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_16(void)1010 void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_16(void)
1011 {
1012 uint32 msr;
1013 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1014
1015 if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_16[u32CoreId])
1016 {
1017 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1018 msr = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
1019 #else
1020 msr = Spi_schm_read_msr(); /*read MSR (to store interrupts state)*/
1021 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1022 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1023 {
1024 OsIf_SuspendAllInterrupts();
1025 #ifdef _ARM_DS5_C_S32ZE_
1026 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1027 #endif
1028 }
1029 msr_SPI_EXCLUSIVE_AREA_16[u32CoreId] = msr;
1030 }
1031 reentry_guard_SPI_EXCLUSIVE_AREA_16[u32CoreId]++;
1032 }
1033
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_16(void)1034 void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_16(void)
1035 {
1036 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1037
1038 reentry_guard_SPI_EXCLUSIVE_AREA_16[u32CoreId]--;
1039 if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_16[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_16[u32CoreId])) /*if interrupts were enabled*/
1040 {
1041 OsIf_ResumeAllInterrupts();
1042 #ifdef _ARM_DS5_C_S32ZE_
1043 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1044 #endif
1045 }
1046 }
1047
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_17(void)1048 void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_17(void)
1049 {
1050 uint32 msr;
1051 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1052
1053 if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_17[u32CoreId])
1054 {
1055 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1056 msr = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
1057 #else
1058 msr = Spi_schm_read_msr(); /*read MSR (to store interrupts state)*/
1059 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1060 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1061 {
1062 OsIf_SuspendAllInterrupts();
1063 #ifdef _ARM_DS5_C_S32ZE_
1064 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1065 #endif
1066 }
1067 msr_SPI_EXCLUSIVE_AREA_17[u32CoreId] = msr;
1068 }
1069 reentry_guard_SPI_EXCLUSIVE_AREA_17[u32CoreId]++;
1070 }
1071
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_17(void)1072 void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_17(void)
1073 {
1074 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1075
1076 reentry_guard_SPI_EXCLUSIVE_AREA_17[u32CoreId]--;
1077 if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_17[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_17[u32CoreId])) /*if interrupts were enabled*/
1078 {
1079 OsIf_ResumeAllInterrupts();
1080 #ifdef _ARM_DS5_C_S32ZE_
1081 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1082 #endif
1083 }
1084 }
1085
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_18(void)1086 void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_18(void)
1087 {
1088 uint32 msr;
1089 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1090
1091 if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_18[u32CoreId])
1092 {
1093 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1094 msr = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
1095 #else
1096 msr = Spi_schm_read_msr(); /*read MSR (to store interrupts state)*/
1097 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1098 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1099 {
1100 OsIf_SuspendAllInterrupts();
1101 #ifdef _ARM_DS5_C_S32ZE_
1102 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1103 #endif
1104 }
1105 msr_SPI_EXCLUSIVE_AREA_18[u32CoreId] = msr;
1106 }
1107 reentry_guard_SPI_EXCLUSIVE_AREA_18[u32CoreId]++;
1108 }
1109
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_18(void)1110 void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_18(void)
1111 {
1112 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1113
1114 reentry_guard_SPI_EXCLUSIVE_AREA_18[u32CoreId]--;
1115 if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_18[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_18[u32CoreId])) /*if interrupts were enabled*/
1116 {
1117 OsIf_ResumeAllInterrupts();
1118 #ifdef _ARM_DS5_C_S32ZE_
1119 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1120 #endif
1121 }
1122 }
1123
1124
1125 #ifdef MCAL_TESTING_ENVIRONMENT
1126 /**
1127 @brief This function checks that all entered exclusive areas were also exited.
1128 @details This function checks that all entered exclusive areas were also exited. The check
1129 is done by verifying that all reentry_guard_* static variables are back to the
1130 zero value.
1131
1132 @param[in] void No input parameters
1133 @return void This function does not return a value. Test asserts are used instead.
1134
1135 @pre None
1136 @post None
1137
1138 @remarks Covers
1139 @remarks Implements
1140 */
SchM_Check_spi(void)1141 void SchM_Check_spi(void)
1142 {
1143 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1144
1145 EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_00[u32CoreId]);
1146 reentry_guard_SPI_EXCLUSIVE_AREA_00[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_00 for the next test in the suite*/
1147
1148 EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_01[u32CoreId]);
1149 reentry_guard_SPI_EXCLUSIVE_AREA_01[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_01 for the next test in the suite*/
1150
1151 EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_02[u32CoreId]);
1152 reentry_guard_SPI_EXCLUSIVE_AREA_02[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_02 for the next test in the suite*/
1153
1154 EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_03[u32CoreId]);
1155 reentry_guard_SPI_EXCLUSIVE_AREA_03[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_03 for the next test in the suite*/
1156
1157 EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_04[u32CoreId]);
1158 reentry_guard_SPI_EXCLUSIVE_AREA_04[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_04 for the next test in the suite*/
1159
1160 EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_05[u32CoreId]);
1161 reentry_guard_SPI_EXCLUSIVE_AREA_05[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_05 for the next test in the suite*/
1162
1163 EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_06[u32CoreId]);
1164 reentry_guard_SPI_EXCLUSIVE_AREA_06[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_06 for the next test in the suite*/
1165
1166 EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_07[u32CoreId]);
1167 reentry_guard_SPI_EXCLUSIVE_AREA_07[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_07 for the next test in the suite*/
1168
1169 EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_08[u32CoreId]);
1170 reentry_guard_SPI_EXCLUSIVE_AREA_08[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_08 for the next test in the suite*/
1171
1172 EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_09[u32CoreId]);
1173 reentry_guard_SPI_EXCLUSIVE_AREA_09[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_09 for the next test in the suite*/
1174
1175 EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_10[u32CoreId]);
1176 reentry_guard_SPI_EXCLUSIVE_AREA_10[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_10 for the next test in the suite*/
1177
1178 EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_11[u32CoreId]);
1179 reentry_guard_SPI_EXCLUSIVE_AREA_11[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_11 for the next test in the suite*/
1180
1181 EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_12[u32CoreId]);
1182 reentry_guard_SPI_EXCLUSIVE_AREA_12[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_12 for the next test in the suite*/
1183
1184 EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_13[u32CoreId]);
1185 reentry_guard_SPI_EXCLUSIVE_AREA_13[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_13 for the next test in the suite*/
1186
1187 EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_14[u32CoreId]);
1188 reentry_guard_SPI_EXCLUSIVE_AREA_14[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_14 for the next test in the suite*/
1189
1190 EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_15[u32CoreId]);
1191 reentry_guard_SPI_EXCLUSIVE_AREA_15[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_15 for the next test in the suite*/
1192
1193 EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_16[u32CoreId]);
1194 reentry_guard_SPI_EXCLUSIVE_AREA_16[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_16 for the next test in the suite*/
1195
1196 EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_17[u32CoreId]);
1197 reentry_guard_SPI_EXCLUSIVE_AREA_17[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_17 for the next test in the suite*/
1198
1199 EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_18[u32CoreId]);
1200 reentry_guard_SPI_EXCLUSIVE_AREA_18[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_18 for the next test in the suite*/
1201
1202
1203 }
1204 #endif /*MCAL_TESTING_ENVIRONMENT*/
1205
1206 #define RTE_STOP_SEC_CODE
1207 #include "Rte_MemMap.h"
1208
1209 #ifdef __cplusplus
1210 }
1211 #endif
1212
1213 /** @} */
1214
