Home
last modified time | relevance | path

Searched refs:Reserved (Results 1 – 21 of 21) sorted by relevance

/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX9352/iar/
Dstartup_MIMX9352_cm33.s64 DCD 0 ;Reserved
65 DCD 0 ;Reserved
66 DCD 0 ;Reserved
69 DCD 0 ;Reserved
76 DCD Reserved18_IRQHandler ;Reserved interrupt
99 DCD Reserved41_IRQHandler ;Reserved interrupt
100 DCD Reserved42_IRQHandler ;Reserved interrupt
101 DCD Reserved43_IRQHandler ;Reserved interrupt
115 DCD Reserved57_IRQHandler ;Reserved interrupt
116 DCD Reserved58_IRQHandler ;Reserved interrupt
[all …]
/hal_nxp-3.6.0/mcux/middleware/mcux-sdk-middleware-usb/host/class/
Dusb_host_cdc_rndis.c159 message->Reserved = 0U; in USB_HostRndisResetMsg()
Dusb_host_cdc_rndis.h203 uint32_t Reserved; member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8QM6/gcc/
DMIMX8QM6xxxFF_cm4_core0_ddr_ram.ld30 /* Reserved for PFU fetches, which is six 16-bit Thumb instructions */
DMIMX8QM6xxxFF_cm4_core0_flash.ld30 /* Reserved for PFU fetches, which is six 16-bit Thumb instructions */
DMIMX8QM6xxxFF_cm4_core1_ddr_ram.ld30 /* Reserved for PFU fetches, which is six 16-bit Thumb instructions */
DMIMX8QM6xxxFF_cm4_core1_flash.ld30 /* Reserved for PFU fetches, which is six 16-bit Thumb instructions */
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8DX6/gcc/
DMIMX8DX6xxxxx_cm4_ddr_ram.ld32 /* Reserved for PFU fetches, which is six 16-bit Thumb instructions */
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8DX2/gcc/
DMIMX8DX2xxxxx_cm4_ddr_ram.ld32 /* Reserved for PFU fetches, which is six 16-bit Thumb instructions */
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8DX1/gcc/
DMIMX8DX1xxxxx_cm4_ddr_ram.ld32 /* Reserved for PFU fetches, which is six 16-bit Thumb instructions */
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8QX4/gcc/
DMIMX8QX4xxxxx_cm4_ddr_ram.ld30 /* Reserved for PFU fetches, which is six 16-bit Thumb instructions */
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8QX3/gcc/
DMIMX8QX3xxxxx_cm4_ddr_ram.ld30 /* Reserved for PFU fetches, which is six 16-bit Thumb instructions */
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8DX3/gcc/
DMIMX8DX3xxxxx_cm4_ddr_ram.ld30 /* Reserved for PFU fetches, which is six 16-bit Thumb instructions */
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8QX2/gcc/
DMIMX8QX2xxxxx_cm4_ddr_ram.ld32 /* Reserved for PFU fetches, which is six 16-bit Thumb instructions */
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8QX1/gcc/
DMIMX8QX1xxxxx_cm4_ddr_ram.ld32 /* Reserved for PFU fetches, which is six 16-bit Thumb instructions */
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8DX4/gcc/
DMIMX8DX4xxxxx_cm4_ddr_ram.ld30 /* Reserved for PFU fetches, which is six 16-bit Thumb instructions */
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8DX5/gcc/
DMIMX8DX5xxxxx_cm4_ddr_ram.ld32 /* Reserved for PFU fetches, which is six 16-bit Thumb instructions */
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8UX6/gcc/
DMIMX8UX6xxxxx_cm4_ddr_ram.ld33 /* Reserved for PFU fetches, which is six 16-bit Thumb instructions */
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8QX5/gcc/
DMIMX8QX5xxxxx_cm4_ddr_ram.ld32 /* Reserved for PFU fetches, which is six 16-bit Thumb instructions */
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8QX6/gcc/
DMIMX8QX6xxxxx_cm4_ddr_ram.ld32 /* Reserved for PFU fetches, which is six 16-bit Thumb instructions */
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8UX5/gcc/
DMIMX8UX5xxxxx_cm4_ddr_ram.ld33 /* Reserved for PFU fetches, which is six 16-bit Thumb instructions */