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Searched refs:RegValue (Results 1 – 20 of 20) sorted by relevance

/hal_nxp-3.6.0/s32/drivers/s32k3/Fls/include/
DQspi_Ip_HwAccess.h91 uint32 RegValue = (uint32)BaseAddr->MCR; in Qspi_Ip_GetClrTxStatus() local
93 RegValue = (RegValue & QuadSPI_MCR_CLR_TXF_MASK) >> QuadSPI_MCR_CLR_TXF_SHIFT; in Qspi_Ip_GetClrTxStatus()
94 return (0U == RegValue)? TRUE : FALSE; in Qspi_Ip_GetClrTxStatus()
113 uint32 RegValue = (uint32)BaseAddr->SPTRCLR; in Qspi_Ip_GetClrAhbStatus() local
115 RegValue = (RegValue & QuadSPI_SPTRCLR_ABRT_CLR_MASK) >> QuadSPI_SPTRCLR_ABRT_CLR_SHIFT; in Qspi_Ip_GetClrAhbStatus()
116 return (0U == RegValue)? TRUE : FALSE; in Qspi_Ip_GetClrAhbStatus()
247 uint32 RegValue = (uint32)BaseAddr->MCR; in Qspi_Ip_SetIdleLineValuesA() local
250 RegValue &= (uint32)(~(QuadSPI_MCR_ISD2FA_MASK | QuadSPI_MCR_ISD3FA_MASK)); in Qspi_Ip_SetIdleLineValuesA()
251 RegValue |= (QuadSPI_MCR_ISD2FA(Iofa2IdleValue) | QuadSPI_MCR_ISD3FA(Iofa3IdleValue)); in Qspi_Ip_SetIdleLineValuesA()
254 BaseAddr->MCR = (uint32)RegValue; in Qspi_Ip_SetIdleLineValuesA()
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/hal_nxp-3.6.0/s32/drivers/s32k1/Mcu/src/
DClock_Ip_Selector.c507 uint32 RegValue; in Clock_Ip_ResetScgRunSel_TrustedCall() local
512 RegValue = IP_SCG->RCCR; in Clock_Ip_ResetScgRunSel_TrustedCall()
513 RegValue &= ~SCG_RCCR_SCS_MASK; in Clock_Ip_ResetScgRunSel_TrustedCall()
514 RegValue |= SCG_RCCR_SCS(SelectorValue); in Clock_Ip_ResetScgRunSel_TrustedCall()
515 IP_SCG->RCCR = RegValue; in Clock_Ip_ResetScgRunSel_TrustedCall()
520 uint32 RegValue; in Clock_Ip_SetScgRunSel_TrustedCall() local
523 RegValue = IP_SCG->RCCR; in Clock_Ip_SetScgRunSel_TrustedCall()
524 RegValue &= ~SCG_RCCR_SCS_MASK; in Clock_Ip_SetScgRunSel_TrustedCall()
525 RegValue |= SCG_RCCR_SCS(SelectorValue); in Clock_Ip_SetScgRunSel_TrustedCall()
526 IP_SCG->RCCR = RegValue; in Clock_Ip_SetScgRunSel_TrustedCall()
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DClock_Ip_Divider.c465 uint32 RegValue; in Clock_Ip_SetScgAsyncDiv1_TrustedCall() local
470 RegValue = Clock_Ip_apxScgPeriphAsyncDivs[Instance]->ASYNC_DIV; in Clock_Ip_SetScgAsyncDiv1_TrustedCall()
471 RegValue &= ~SCG_SIRCDIV_SIRCDIV1_MASK; in Clock_Ip_SetScgAsyncDiv1_TrustedCall()
472 RegValue |= (DividerValue << SCG_SIRCDIV_SIRCDIV1_SHIFT); in Clock_Ip_SetScgAsyncDiv1_TrustedCall()
473 Clock_Ip_apxScgPeriphAsyncDivs[Instance]->ASYNC_DIV = RegValue; in Clock_Ip_SetScgAsyncDiv1_TrustedCall()
480 uint32 RegValue; in Clock_Ip_SetScgAsyncDiv2_TrustedCall() local
484 RegValue = Clock_Ip_apxScgPeriphAsyncDivs[Instance]->ASYNC_DIV; in Clock_Ip_SetScgAsyncDiv2_TrustedCall()
485 RegValue &= ~SCG_SIRCDIV_SIRCDIV2_MASK; in Clock_Ip_SetScgAsyncDiv2_TrustedCall()
486 RegValue |= (DividerValue << SCG_SIRCDIV_SIRCDIV2_SHIFT); in Clock_Ip_SetScgAsyncDiv2_TrustedCall()
487 Clock_Ip_apxScgPeriphAsyncDivs[Instance]->ASYNC_DIV = RegValue; in Clock_Ip_SetScgAsyncDiv2_TrustedCall()
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DClock_Ip_Gate.c389 uint32 RegValue; in Clock_Ip_ClockSetSimLPO1KEnable_TrustedCall() local
391 RegValue = IP_SIM->LPOCLKS; in Clock_Ip_ClockSetSimLPO1KEnable_TrustedCall()
392 RegValue &= ~SIM_LPOCLKS_LPO1KCLKEN_MASK; in Clock_Ip_ClockSetSimLPO1KEnable_TrustedCall()
393 RegValue |= ((uint32)(Config->Enable) << SIM_LPOCLKS_LPO1KCLKEN_SHIFT); in Clock_Ip_ClockSetSimLPO1KEnable_TrustedCall()
394 IP_SIM->LPOCLKS = RegValue; in Clock_Ip_ClockSetSimLPO1KEnable_TrustedCall()
402 uint32 RegValue; in Clock_Ip_ClockSetSimLPO32KEnable_TrustedCall() local
404 RegValue = IP_SIM->LPOCLKS; in Clock_Ip_ClockSetSimLPO32KEnable_TrustedCall()
405 RegValue &= ~SIM_LPOCLKS_LPO32KCLKEN_MASK; in Clock_Ip_ClockSetSimLPO32KEnable_TrustedCall()
406 RegValue |= ((uint32)(Config->Enable) << SIM_LPOCLKS_LPO32KCLKEN_SHIFT); in Clock_Ip_ClockSetSimLPO32KEnable_TrustedCall()
407 IP_SIM->LPOCLKS = RegValue; in Clock_Ip_ClockSetSimLPO32KEnable_TrustedCall()
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DClock_Ip_IntOsc.c182 uint32 RegValue; in Clock_Ip_SetFircDivSelHSEb() local
228 RegValue = IP_CONFIGURATION_GPR->CONFIG_REG_GPR; in Clock_Ip_SetFircDivSelHSEb()
229 RegValue &= ~CONFIGURATION_GPR_CONFIG_REG_GPR_FIRC_DIV_SEL_MASK; in Clock_Ip_SetFircDivSelHSEb()
230 RegValue |= CONFIGURATION_GPR_CONFIG_REG_GPR_FIRC_DIV_SEL(DividerValue); in Clock_Ip_SetFircDivSelHSEb()
231 IP_CONFIGURATION_GPR->CONFIG_REG_GPR = RegValue; in Clock_Ip_SetFircDivSelHSEb()
247 (void)RegValue; in Clock_Ip_SetFircDivSelHSEb()
380 uint32 RegValue; in SetInputSouceSytemClock() local
387 RegValue = IP_SCG->RCCR; in SetInputSouceSytemClock()
388 RegValue &= ~SCG_RCCR_SCS_MASK; in SetInputSouceSytemClock()
389 RegValue |= (SourceClock << SCG_RCCR_SCS_SHIFT); in SetInputSouceSytemClock()
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DClock_Ip_Specific.c415 uint32 RegValue; in Clock_Ip_EnableCmu0Gate_TrustedCall() local
417 RegValue = IP_PCC->PCCn[Clock_Ip_au8ClockFeatures[CMU0_CLK][CLOCK_IP_GATE_INDEX]]; in Clock_Ip_EnableCmu0Gate_TrustedCall()
418 RegValue &= ~PCC_PCCn_CGC_MASK; in Clock_Ip_EnableCmu0Gate_TrustedCall()
419 RegValue |= PCC_PCCn_CGC_MASK; in Clock_Ip_EnableCmu0Gate_TrustedCall()
420 IP_PCC->PCCn[Clock_Ip_au8ClockFeatures[CMU0_CLK][CLOCK_IP_GATE_INDEX]] = RegValue; in Clock_Ip_EnableCmu0Gate_TrustedCall()
428 uint32 RegValue; in Clock_Ip_EnableCmu1Gate_TrustedCall() local
430 RegValue = IP_PCC->PCCn[Clock_Ip_au8ClockFeatures[CMU1_CLK][CLOCK_IP_GATE_INDEX]]; in Clock_Ip_EnableCmu1Gate_TrustedCall()
431 RegValue &= ~PCC_PCCn_CGC_MASK; in Clock_Ip_EnableCmu1Gate_TrustedCall()
432 RegValue |= PCC_PCCn_CGC_MASK; in Clock_Ip_EnableCmu1Gate_TrustedCall()
433 IP_PCC->PCCn[Clock_Ip_au8ClockFeatures[CMU1_CLK][CLOCK_IP_GATE_INDEX]] = RegValue; in Clock_Ip_EnableCmu1Gate_TrustedCall()
/hal_nxp-3.6.0/s32/drivers/s32ze/Mcu/src/
DClock_Ip_Divider.c146 uint32 RegValue; in Clock_Ip_SetCgmXDeDivStatWithoutPhase() local
160 RegValue = Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex]; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
165 RegValue &= ~DividerMask; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
166 RegValue |= (((Config->Value-1U) << DividerShift) & DividerMask); in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
171 RegValue &= ~MC_CGM_MUX_2_DC_2_DIV_FMT_MASK; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
175 RegValue &= ~MC_CGM_MUX_2_DC_2_DIV_FMT_MASK; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
184 RegValue |= MC_CGM_MUX_DC_DE_MASK; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
188 RegValue &= ~MC_CGM_MUX_DC_DE_MASK; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
191 Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex] = RegValue; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
215 (void)RegValue; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
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DClock_Ip_Selector.c184 uint32 RegValue; in Clock_Ip_SetCgmXCscCssClkswSwip() local
211 RegValue = Clock_Ip_apxCgm[Instance][SelectorIndex]->CSC; in Clock_Ip_SetCgmXCscCssClkswSwip()
212 RegValue &= ~SelectorMask; in Clock_Ip_SetCgmXCscCssClkswSwip()
213 RegValue |= (SelectorValue << SelectorShift) & SelectorMask; in Clock_Ip_SetCgmXCscCssClkswSwip()
214 RegValue |= (MC_CGM_MUX_CSC_CLK_SW_MASK); /* Clock switch operation is requested */ in Clock_Ip_SetCgmXCscCssClkswSwip()
215 Clock_Ip_apxCgm[Instance][SelectorIndex]->CSC = RegValue; in Clock_Ip_SetCgmXCscCssClkswSwip()
269 (void)RegValue; in Clock_Ip_SetCgmXCscCssClkswSwip()
288 uint32 RegValue; in Clock_Ip_ResetCgmXCscCssCsGrip() local
315 RegValue = Clock_Ip_apxCgm[Instance][SelectorIndex]->CSC; in Clock_Ip_ResetCgmXCscCssCsGrip()
316 RegValue &= ~SelectorMask; in Clock_Ip_ResetCgmXCscCssCsGrip()
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DClock_Ip_Pll.c454 uint32 RegValue; in Clock_Ip_ResetLfastPLL() local
472 RegValue = Clock_Ip_apxLfastPll[Instance].PllInstance->PLLCR; in Clock_Ip_ResetLfastPLL()
473 RegValue &= ~(CLOCK_IP_LFASTPLL_PLLCR_RESERVED_RWBIT_MASK); in Clock_Ip_ResetLfastPLL()
474 RegValue |= 0xC0000000U; in Clock_Ip_ResetLfastPLL()
476 RegValue &= (~((uint32)LFAST_PLLCR_FBDIV_MASK)); in Clock_Ip_ResetLfastPLL()
477 RegValue |= LFAST_PLLCR_FBDIV((uint8)(Config->MulFactorDiv)); in Clock_Ip_ResetLfastPLL()
479 RegValue &= (~((uint32)LFAST_PLLCR_PREDIV_MASK)); in Clock_Ip_ResetLfastPLL()
480 RegValue |= LFAST_PLLCR_PREDIV((uint8)(Config->Predivider - 1U)); in Clock_Ip_ResetLfastPLL()
482 RegValue &= (~((uint32)LFAST_PLLCR_FDIVEN_MASK)); in Clock_Ip_ResetLfastPLL()
484 RegValue &= (~((uint32)LFAST_PLLCR_LPCFG_MASK)); in Clock_Ip_ResetLfastPLL()
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DClock_Ip_Specific.c251 uint32 RegValue; in Clock_Ip_SpecificPlatformInitClock() local
262 RegValue = IP_CORE_PLL->PLLDV; in Clock_Ip_SpecificPlatformInitClock()
263 RegValue &= ~(PLLDIG_PLLDV_RDIV_MASK | PLLDIG_PLLDV_MFI_MASK); in Clock_Ip_SpecificPlatformInitClock()
264 …IP_CORE_PLL->PLLDV = (RegValue | (PLLDIG_PLLDV_RDIV(1U) | PLLDIG_PLLDV_MFI(30U)) ); /* /1… in Clock_Ip_SpecificPlatformInitClock()
273 RegValue = IP_PERIPH_PLL->PLLDV; in Clock_Ip_SpecificPlatformInitClock()
274 RegValue &= ~(PLLDIG_PLLDV_RDIV_MASK | PLLDIG_PLLDV_MFI_MASK); in Clock_Ip_SpecificPlatformInitClock()
275 …IP_PERIPH_PLL->PLLDV = (RegValue | (PLLDIG_PLLDV_RDIV(1U) | PLLDIG_PLLDV_MFI(30U)) ); /* … in Clock_Ip_SpecificPlatformInitClock()
306 RegValue = IP_CORE_PLL->PLLDV; in Clock_Ip_SpecificPlatformInitClock()
307 RegValue &= ~(PLLDIG_PLLDV_RDIV_MASK | PLLDIG_PLLDV_MFI_MASK); in Clock_Ip_SpecificPlatformInitClock()
308 …IP_CORE_PLL->PLLDV = (RegValue | (PLLDIG_PLLDV_RDIV(1U) | PLLDIG_PLLDV_MFI(30U)) ); /* /1… in Clock_Ip_SpecificPlatformInitClock()
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/hal_nxp-3.6.0/s32/drivers/s32k3/Mcu/src/
DClock_Ip_Divider.c145 uint32 RegValue; in Clock_Ip_SetCgmXDeDivStatWithoutPhase() local
163 RegValue = Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex]; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
164 RegValue &= ~DividerMask; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
165 RegValue |= (((Config->Value-1U) << DividerShift) & DividerMask); in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
166 Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex] = RegValue; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
219 (void)RegValue; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
234 uint32 RegValue; in Clock_Ip_SetPllPll0divDeDivOutput() local
245 RegValue = Clock_Ip_apxPll[Instance].PllInstance->PLLODIV[DividerIndex]; in Clock_Ip_SetPllPll0divDeDivOutput()
246 RegValue |= PLL_PLLODIV_DE_MASK; in Clock_Ip_SetPllPll0divDeDivOutput()
247 RegValue &= ~PLL_PLLODIV_DIV_MASK; in Clock_Ip_SetPllPll0divDeDivOutput()
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DPower_Ip_MC_RGM.c206 static void Power_Ip_MC_RGM_ClearFesResetFlags(uint32 RegValue);
207 static void Power_Ip_MC_RGM_ClearDesResetFlags(uint32 RegValue);
225 static void Power_Ip_MC_RGM_ClearFesResetFlags(uint32 RegValue) in Power_Ip_MC_RGM_ClearFesResetFlags() argument
231 uint32 RegValueTemp = RegValue; in Power_Ip_MC_RGM_ClearFesResetFlags()
266 static void Power_Ip_MC_RGM_ClearDesResetFlags(uint32 RegValue) in Power_Ip_MC_RGM_ClearDesResetFlags() argument
272 uint32 RegValueTemp = RegValue; in Power_Ip_MC_RGM_ClearDesResetFlags()
516 uint32 RegValue = 0U; in Power_Ip_MC_RGM_GetResetReason() local
521 RegValue = Power_Ip_pxMC_RGM->DES & MC_RGM_DES_RWBITS_MASK32; in Power_Ip_MC_RGM_GetResetReason()
524 if ((uint32)0U != RegValue) in Power_Ip_MC_RGM_GetResetReason()
526 DesResetStatus = RegValue; in Power_Ip_MC_RGM_GetResetReason()
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DClock_Ip_Selector.c182 uint32 RegValue; in Clock_Ip_SetCgmXCscCssClkswSwip() local
209 RegValue = Clock_Ip_apxCgm[Instance][SelectorIndex]->CSC; in Clock_Ip_SetCgmXCscCssClkswSwip()
210 RegValue &= ~SelectorMask; in Clock_Ip_SetCgmXCscCssClkswSwip()
211 RegValue |= (SelectorValue << SelectorShift) & SelectorMask; in Clock_Ip_SetCgmXCscCssClkswSwip()
212 RegValue |= (MC_CGM_MUX_CSC_CLK_SW_MASK); /* Clock switch operation is requested */ in Clock_Ip_SetCgmXCscCssClkswSwip()
213 Clock_Ip_apxCgm[Instance][SelectorIndex]->CSC = RegValue; in Clock_Ip_SetCgmXCscCssClkswSwip()
267 (void)RegValue; in Clock_Ip_SetCgmXCscCssClkswSwip()
314 uint32 RegValue; in Clock_Ip_SetCgmXCscCssClkswRampupRampdownSwip() local
341 RegValue = Clock_Ip_apxCgm[Instance][SelectorIndex]->CSC; in Clock_Ip_SetCgmXCscCssClkswRampupRampdownSwip()
342 RegValue &= ~SelectorMask; in Clock_Ip_SetCgmXCscCssClkswRampupRampdownSwip()
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DClock_Ip_IntOsc.c208 uint32 RegValue; in Clock_Ip_SetFircDivSelHSEb() local
254 RegValue = IP_CONFIGURATION_GPR->CONFIG_REG_GPR; in Clock_Ip_SetFircDivSelHSEb()
255 RegValue &= ~CONFIGURATION_GPR_CONFIG_REG_GPR_FIRC_DIV_SEL_MASK; in Clock_Ip_SetFircDivSelHSEb()
256 RegValue |= CONFIGURATION_GPR_CONFIG_REG_GPR_FIRC_DIV_SEL(DividerValue); in Clock_Ip_SetFircDivSelHSEb()
257 IP_CONFIGURATION_GPR->CONFIG_REG_GPR = RegValue; in Clock_Ip_SetFircDivSelHSEb()
273 (void)RegValue; in Clock_Ip_SetFircDivSelHSEb()
DClock_Ip_Specific.c375 uint32 RegValue; in Clock_Ip_CodeInRamSetFlashWaitStates() local
421 RegValue = IP_FLASH->CTL; in Clock_Ip_CodeInRamSetFlashWaitStates()
422 RegValue &= ~FLASH_CTL_RWSL_MASK; in Clock_Ip_CodeInRamSetFlashWaitStates()
423 RegValue &= ~FLASH_CTL_RWSC_MASK; in Clock_Ip_CodeInRamSetFlashWaitStates()
424 RegValue |= FLASH_CTL_RWSC(RwscSetting); in Clock_Ip_CodeInRamSetFlashWaitStates()
434 IP_FLASH->CTL = RegValue; in Clock_Ip_CodeInRamSetFlashWaitStates()
DPower_Ip_PMC.c437 uint32 RegValue; in Power_Ip_PMC_VoltageErrorIsr() local
441 RegValue = IP_PMC->LVSC; in Power_Ip_PMC_VoltageErrorIsr()
443 VoltageIsrEnabled = RegValue & PMC_LVSC_OV_UV_IRQ_FLAGS_MASK32; in Power_Ip_PMC_VoltageErrorIsr()
448 VoltageIsrStatus = RegValue & PMC_LVSC_OV_UV_STATUS_FLAGS_MASK32; in Power_Ip_PMC_VoltageErrorIsr()
450 RegValue = IP_PMC->CONFIG; in Power_Ip_PMC_VoltageErrorIsr()
452 if (PMC_CONFIG_LVD_INTERRUPTS_DISABLE == (RegValue & PMC_CONFIG_LVDIE_MASK)) in Power_Ip_PMC_VoltageErrorIsr()
461 if (PMC_CONFIG_HVD_INTERRUPTS_DISABLE == (RegValue & PMC_CONFIG_HVDIE_MASK)) in Power_Ip_PMC_VoltageErrorIsr()
/hal_nxp-3.6.0/s32/drivers/s32k3/Mcl/src/
DTrgmux_Ip_HwAcc.c113 uint32 RegValue; in hwAcc_Init() local
120 RegValue = pTrgmux->TRGMUXn[RegIdx] & TRGMUX_TRGMUXn_LK_MASK; in hwAcc_Init()
121 if(TRGMUX_TRGMUXn_LK_MASK == RegValue) in hwAcc_Init()
141 uint32 RegValue; in hwAcc_SetInputForOutput() local
144 RegValue = pTrgmux->TRGMUXn[TRGMUX_IP_REG_IDX(Output)]; in hwAcc_SetInputForOutput()
145 …RegValue &= ~((uint32)TRGMUX_TRGMUXn_SEL0_MASK << (TRGMUX_TRGMUXn_SEL1_SHIFT * TRGMUX_IP_REG_SELEC… in hwAcc_SetInputForOutput()
146 …RegValue |= ((uint32)Input) << ((uint8)(TRGMUX_TRGMUXn_SEL1_SHIFT * TRGMUX_IP_REG_SELECTION_IDX(O… in hwAcc_SetInputForOutput()
147 pTrgmux->TRGMUXn[TRGMUX_IP_REG_IDX(Output)] = RegValue; in hwAcc_SetInputForOutput()
DLcu_Ip.c360 uint32 RegValue; in Lcu_Ip_SetSyncInputSwOverrideEnable() local
409 RegValue = Lcu_Ip_paxBaseInst[LCU_IP_HW_INST_0]->SWEN; in Lcu_Ip_SetSyncInputSwOverrideEnable()
410 RegValue &= ~MaskValue[LCU_IP_HW_INST_0]; in Lcu_Ip_SetSyncInputSwOverrideEnable()
411 RegValue |= DataValue[LCU_IP_HW_INST_0]; in Lcu_Ip_SetSyncInputSwOverrideEnable()
412 Lcu_Ip_paxBaseInst[LCU_IP_HW_INST_0]->SWEN = RegValue; in Lcu_Ip_SetSyncInputSwOverrideEnable()
422 RegValue = Lcu_Ip_paxBaseInst[LCU_IP_HW_INST_1]->SWEN; in Lcu_Ip_SetSyncInputSwOverrideEnable()
423 RegValue &= ~MaskValue[LCU_IP_HW_INST_1]; in Lcu_Ip_SetSyncInputSwOverrideEnable()
424 RegValue |= DataValue[LCU_IP_HW_INST_1]; in Lcu_Ip_SetSyncInputSwOverrideEnable()
425 Lcu_Ip_paxBaseInst[LCU_IP_HW_INST_1]->SWEN = RegValue; in Lcu_Ip_SetSyncInputSwOverrideEnable()
452 uint32 RegValue; in Lcu_Ip_SetSyncInputSwOverrideValue() local
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/hal_nxp-3.6.0/s32/drivers/s32ze/Eth_NETC/src/
DNetc_Eth_Ip.c1772 uint32 RegValue; in Netc_Eth_Ip_ConfigPortTimeGateScheduling() local
1786 RegValue = IP_NETC__ENETC0_PORT->PTGSCR; in Netc_Eth_Ip_ConfigPortTimeGateScheduling()
1787 …if ((RegValue & ENETC_PORT_PTGSCR_TGE_MASK) != ENETC_PORT_PTGSCR_TGE_MASK) /* time gating is … in Netc_Eth_Ip_ConfigPortTimeGateScheduling()
1801 RegValue |= ENETC_PORT_PTGSCR_TGE(1U); /* Enable time gating */ in Netc_Eth_Ip_ConfigPortTimeGateScheduling()
1813 RegValue &= ~ENETC_PORT_PTGSCR_TGE(1U); /* Disable time gating */ in Netc_Eth_Ip_ConfigPortTimeGateScheduling()
1820 IP_NETC__ENETC0_PORT->PTGSCR = RegValue; in Netc_Eth_Ip_ConfigPortTimeGateScheduling()
/hal_nxp-3.6.0/s32/drivers/s32ze/EthSwt_NETC/src/
DNetc_EthSwt_Ip.c3619 uint32 RegValue; local
3634 RegValue = Netc_EthSwt_Ip_SW0_PortxBaseAddr[SwitchPortIdx]->PTGSCR;
3635 …if ((RegValue & SW_PORT0_PTGSCR_TGE_MASK) != SW_PORT0_PTGSCR_TGE_MASK) /* time gating is disa…
3649 RegValue |= SW_PORT0_PTGSCR_TGE(1U); /* Enable time gating */
3661 RegValue &= ~SW_PORT0_PTGSCR_TGE(1U); /* Disable time gating */
3668 Netc_EthSwt_Ip_SW0_PortxBaseAddr[SwitchPortIdx]->PTGSCR = RegValue;