1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2023 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_RTU_MRU.h 10 * @version 2.1 11 * @date 2023-07-20 12 * @brief Peripheral Access Layer for S32Z2_RTU_MRU 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_RTU_MRU_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_RTU_MRU_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- RTU_MRU Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup RTU_MRU_Peripheral_Access_Layer RTU_MRU Peripheral Access Layer 68 * @{ 69 */ 70 71 /** RTU_MRU - Size of Registers Arrays */ 72 #define RTU_MRU_CHXCONFIG_COUNT 12u 73 #define RTU_MRU_NOTIFY_COUNT 2u 74 75 /** RTU_MRU - Register Layout Typedef */ 76 typedef struct { 77 struct { /* offset: 0x0, array step: 0x10 */ 78 __IO uint32_t CH_CFG0; /**< Channel (x) Configuration 0, array offset: 0x0, array step: 0x10 */ 79 __IO uint32_t CH_CFG1; /**< Channel (x) Configuration 1, array offset: 0x4, array step: 0x10 */ 80 __IO uint32_t CH_MBSTAT; /**< Channel (x) Mailbox Status, array offset: 0x8, array step: 0x10 */ 81 uint8_t RESERVED_0[4]; 82 } CHXCONFIG[RTU_MRU_CHXCONFIG_COUNT]; 83 uint8_t RESERVED_0[320]; 84 __I uint32_t NOTIFY[RTU_MRU_NOTIFY_COUNT]; /**< Notification 0 Status..Notification 1 Status, array offset: 0x200, array step: 0x4 */ 85 uint8_t RESERVED_1[3576]; 86 __IO uint32_t CH1_MB0; /**< Channel (x) Mailbox (n), offset: 0x1000 */ 87 __IO uint32_t CH1_MB1; /**< Channel (x) Mailbox (n), offset: 0x1004 */ 88 uint8_t RESERVED_2[4088]; 89 __IO uint32_t CH2_MB0; /**< Channel (x) Mailbox (n), offset: 0x2000 */ 90 __IO uint32_t CH2_MB1; /**< Channel (x) Mailbox (n), offset: 0x2004 */ 91 uint8_t RESERVED_3[4088]; 92 __IO uint32_t CH3_MB0; /**< Channel (x) Mailbox (n), offset: 0x3000 */ 93 __IO uint32_t CH3_MB1; /**< Channel (x) Mailbox (n), offset: 0x3004 */ 94 uint8_t RESERVED_4[4088]; 95 __IO uint32_t CH4_MB0; /**< Channel (x) Mailbox (n), offset: 0x4000 */ 96 __IO uint32_t CH4_MB1; /**< Channel (x) Mailbox (n), offset: 0x4004 */ 97 uint8_t RESERVED_5[4088]; 98 __IO uint32_t CH5_MB0; /**< Channel (x) Mailbox (n), offset: 0x5000 */ 99 __IO uint32_t CH5_MB1; /**< Channel (x) Mailbox (n), offset: 0x5004 */ 100 uint8_t RESERVED_6[4088]; 101 __IO uint32_t CH6_MB0; /**< Channel (x) Mailbox (n), offset: 0x6000 */ 102 __IO uint32_t CH6_MB1; /**< Channel (x) Mailbox (n), offset: 0x6004 */ 103 uint8_t RESERVED_7[4088]; 104 __IO uint32_t CH7_MB0; /**< Channel (x) Mailbox (n), offset: 0x7000 */ 105 __IO uint32_t CH7_MB1; /**< Channel (x) Mailbox (n), offset: 0x7004 */ 106 uint8_t RESERVED_8[4088]; 107 __IO uint32_t CH8_MB0; /**< Channel (x) Mailbox (n), offset: 0x8000 */ 108 __IO uint32_t CH8_MB1; /**< Channel (x) Mailbox (n), offset: 0x8004 */ 109 __IO uint32_t CH8_MB2; /**< Channel (x) Mailbox (n), offset: 0x8008 */ 110 __IO uint32_t CH8_MB3; /**< Channel (x) Mailbox (n), offset: 0x800C */ 111 __IO uint32_t CH8_MB4; /**< Channel (x) Mailbox (n), offset: 0x8010 */ 112 __IO uint32_t CH8_MB5; /**< Channel (x) Mailbox (n), offset: 0x8014 */ 113 __IO uint32_t CH8_MB6; /**< Channel (x) Mailbox (n), offset: 0x8018 */ 114 __IO uint32_t CH8_MB7; /**< Channel (x) Mailbox (n), offset: 0x801C */ 115 uint8_t RESERVED_9[4064]; 116 __IO uint32_t CH9_MB0; /**< Channel (x) Mailbox (n), offset: 0x9000 */ 117 __IO uint32_t CH9_MB1; /**< Channel (x) Mailbox (n), offset: 0x9004 */ 118 __IO uint32_t CH9_MB2; /**< Channel (x) Mailbox (n), offset: 0x9008 */ 119 __IO uint32_t CH9_MB3; /**< Channel (x) Mailbox (n), offset: 0x900C */ 120 uint8_t RESERVED_10[4080]; 121 __IO uint32_t CH10_MB0; /**< Channel (x) Mailbox (n), offset: 0xA000 */ 122 __IO uint32_t CH10_MB1; /**< Channel (x) Mailbox (n), offset: 0xA004 */ 123 __IO uint32_t CH10_MB2; /**< Channel (x) Mailbox (n), offset: 0xA008 */ 124 __IO uint32_t CH10_MB3; /**< Channel (x) Mailbox (n), offset: 0xA00C */ 125 uint8_t RESERVED_11[4080]; 126 __IO uint32_t CH11_MB0; /**< Channel (x) Mailbox (n), offset: 0xB000 */ 127 __IO uint32_t CH11_MB1; /**< Channel (x) Mailbox (n), offset: 0xB004 */ 128 __IO uint32_t CH11_MB2; /**< Channel (x) Mailbox (n), offset: 0xB008 */ 129 __IO uint32_t CH11_MB3; /**< Channel (x) Mailbox (n), offset: 0xB00C */ 130 uint8_t RESERVED_12[4080]; 131 __IO uint32_t CH12_MB0; /**< Channel (x) Mailbox (n), offset: 0xC000 */ 132 __IO uint32_t CH12_MB1; /**< Channel (x) Mailbox (n), offset: 0xC004 */ 133 __IO uint32_t CH12_MB2; /**< Channel (x) Mailbox (n), offset: 0xC008 */ 134 __IO uint32_t CH12_MB3; /**< Channel (x) Mailbox (n), offset: 0xC00C */ 135 } RTU_MRU_Type, *RTU_MRU_MemMapPtr; 136 137 /** Number of instances of the RTU_MRU module. */ 138 #define RTU_MRU_INSTANCE_COUNT (8) 139 140 /* RTU_MRU - Peripheral instance base addresses */ 141 /** Peripheral RTU0__MRU_0 base address */ 142 #define IP_RTU0__MRU_0_BASE (0x76070000u) 143 /** Peripheral RTU0__MRU_0 base pointer */ 144 #define IP_RTU0__MRU_0 ((RTU_MRU_Type *)IP_RTU0__MRU_0_BASE) 145 /** Peripheral RTU0__MRU_1 base address */ 146 #define IP_RTU0__MRU_1_BASE (0x76090000u) 147 /** Peripheral RTU0__MRU_1 base pointer */ 148 #define IP_RTU0__MRU_1 ((RTU_MRU_Type *)IP_RTU0__MRU_1_BASE) 149 /** Peripheral RTU0__MRU_2 base address */ 150 #define IP_RTU0__MRU_2_BASE (0x76270000u) 151 /** Peripheral RTU0__MRU_2 base pointer */ 152 #define IP_RTU0__MRU_2 ((RTU_MRU_Type *)IP_RTU0__MRU_2_BASE) 153 /** Peripheral RTU0__MRU_3 base address */ 154 #define IP_RTU0__MRU_3_BASE (0x76290000u) 155 /** Peripheral RTU0__MRU_3 base pointer */ 156 #define IP_RTU0__MRU_3 ((RTU_MRU_Type *)IP_RTU0__MRU_3_BASE) 157 /** Peripheral RTU1__MRU_0 base address */ 158 #define IP_RTU1__MRU_0_BASE (0x76870000u) 159 /** Peripheral RTU1__MRU_0 base pointer */ 160 #define IP_RTU1__MRU_0 ((RTU_MRU_Type *)IP_RTU1__MRU_0_BASE) 161 /** Peripheral RTU1__MRU_1 base address */ 162 #define IP_RTU1__MRU_1_BASE (0x76890000u) 163 /** Peripheral RTU1__MRU_1 base pointer */ 164 #define IP_RTU1__MRU_1 ((RTU_MRU_Type *)IP_RTU1__MRU_1_BASE) 165 /** Peripheral RTU1__MRU_2 base address */ 166 #define IP_RTU1__MRU_2_BASE (0x76A70000u) 167 /** Peripheral RTU1__MRU_2 base pointer */ 168 #define IP_RTU1__MRU_2 ((RTU_MRU_Type *)IP_RTU1__MRU_2_BASE) 169 /** Peripheral RTU1__MRU_3 base address */ 170 #define IP_RTU1__MRU_3_BASE (0x76A90000u) 171 /** Peripheral RTU1__MRU_3 base pointer */ 172 #define IP_RTU1__MRU_3 ((RTU_MRU_Type *)IP_RTU1__MRU_3_BASE) 173 /** Array initializer of RTU_MRU peripheral base addresses */ 174 #define IP_RTU_MRU_BASE_ADDRS { IP_RTU0__MRU_0_BASE, IP_RTU0__MRU_1_BASE, IP_RTU0__MRU_2_BASE, IP_RTU0__MRU_3_BASE, IP_RTU1__MRU_0_BASE, IP_RTU1__MRU_1_BASE, IP_RTU1__MRU_2_BASE, IP_RTU1__MRU_3_BASE } 175 /** Array initializer of RTU_MRU peripheral base pointers */ 176 #define IP_RTU_MRU_BASE_PTRS { IP_RTU0__MRU_0, IP_RTU0__MRU_1, IP_RTU0__MRU_2, IP_RTU0__MRU_3, IP_RTU1__MRU_0, IP_RTU1__MRU_1, IP_RTU1__MRU_2, IP_RTU1__MRU_3 } 177 178 /* ---------------------------------------------------------------------------- 179 -- RTU_MRU Register Masks 180 ---------------------------------------------------------------------------- */ 181 182 /*! 183 * @addtogroup RTU_MRU_Register_Masks RTU_MRU Register Masks 184 * @{ 185 */ 186 187 /*! @name CH_CFG0 - Channel (x) Configuration 0 */ 188 /*! @{ */ 189 190 #define RTU_MRU_CH_CFG0_CHE_MASK (0x1U) 191 #define RTU_MRU_CH_CFG0_CHE_SHIFT (0U) 192 #define RTU_MRU_CH_CFG0_CHE_WIDTH (1U) 193 #define RTU_MRU_CH_CFG0_CHE(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH_CFG0_CHE_SHIFT)) & RTU_MRU_CH_CFG0_CHE_MASK) 194 195 #define RTU_MRU_CH_CFG0_CHR_MASK (0x2U) 196 #define RTU_MRU_CH_CFG0_CHR_SHIFT (1U) 197 #define RTU_MRU_CH_CFG0_CHR_WIDTH (1U) 198 #define RTU_MRU_CH_CFG0_CHR(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH_CFG0_CHR_SHIFT)) & RTU_MRU_CH_CFG0_CHR_MASK) 199 200 #define RTU_MRU_CH_CFG0_IE_MASK (0x4U) 201 #define RTU_MRU_CH_CFG0_IE_SHIFT (2U) 202 #define RTU_MRU_CH_CFG0_IE_WIDTH (1U) 203 #define RTU_MRU_CH_CFG0_IE(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH_CFG0_IE_SHIFT)) & RTU_MRU_CH_CFG0_IE_MASK) 204 205 #define RTU_MRU_CH_CFG0_MBE0_MASK (0x10000U) 206 #define RTU_MRU_CH_CFG0_MBE0_SHIFT (16U) 207 #define RTU_MRU_CH_CFG0_MBE0_WIDTH (1U) 208 #define RTU_MRU_CH_CFG0_MBE0(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH_CFG0_MBE0_SHIFT)) & RTU_MRU_CH_CFG0_MBE0_MASK) 209 210 #define RTU_MRU_CH_CFG0_MBE1_MASK (0x20000U) 211 #define RTU_MRU_CH_CFG0_MBE1_SHIFT (17U) 212 #define RTU_MRU_CH_CFG0_MBE1_WIDTH (1U) 213 #define RTU_MRU_CH_CFG0_MBE1(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH_CFG0_MBE1_SHIFT)) & RTU_MRU_CH_CFG0_MBE1_MASK) 214 215 #define RTU_MRU_CH_CFG0_MBE2_MASK (0x40000U) 216 #define RTU_MRU_CH_CFG0_MBE2_SHIFT (18U) 217 #define RTU_MRU_CH_CFG0_MBE2_WIDTH (1U) 218 #define RTU_MRU_CH_CFG0_MBE2(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH_CFG0_MBE2_SHIFT)) & RTU_MRU_CH_CFG0_MBE2_MASK) 219 220 #define RTU_MRU_CH_CFG0_MBE3_MASK (0x80000U) 221 #define RTU_MRU_CH_CFG0_MBE3_SHIFT (19U) 222 #define RTU_MRU_CH_CFG0_MBE3_WIDTH (1U) 223 #define RTU_MRU_CH_CFG0_MBE3(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH_CFG0_MBE3_SHIFT)) & RTU_MRU_CH_CFG0_MBE3_MASK) 224 225 #define RTU_MRU_CH_CFG0_MBE4_MASK (0x100000U) 226 #define RTU_MRU_CH_CFG0_MBE4_SHIFT (20U) 227 #define RTU_MRU_CH_CFG0_MBE4_WIDTH (1U) 228 #define RTU_MRU_CH_CFG0_MBE4(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH_CFG0_MBE4_SHIFT)) & RTU_MRU_CH_CFG0_MBE4_MASK) 229 230 #define RTU_MRU_CH_CFG0_MBE5_MASK (0x200000U) 231 #define RTU_MRU_CH_CFG0_MBE5_SHIFT (21U) 232 #define RTU_MRU_CH_CFG0_MBE5_WIDTH (1U) 233 #define RTU_MRU_CH_CFG0_MBE5(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH_CFG0_MBE5_SHIFT)) & RTU_MRU_CH_CFG0_MBE5_MASK) 234 235 #define RTU_MRU_CH_CFG0_MBE6_MASK (0x400000U) 236 #define RTU_MRU_CH_CFG0_MBE6_SHIFT (22U) 237 #define RTU_MRU_CH_CFG0_MBE6_WIDTH (1U) 238 #define RTU_MRU_CH_CFG0_MBE6(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH_CFG0_MBE6_SHIFT)) & RTU_MRU_CH_CFG0_MBE6_MASK) 239 240 #define RTU_MRU_CH_CFG0_MBE7_MASK (0x800000U) 241 #define RTU_MRU_CH_CFG0_MBE7_SHIFT (23U) 242 #define RTU_MRU_CH_CFG0_MBE7_WIDTH (1U) 243 #define RTU_MRU_CH_CFG0_MBE7(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH_CFG0_MBE7_SHIFT)) & RTU_MRU_CH_CFG0_MBE7_MASK) 244 /*! @} */ 245 246 /*! @name CH_CFG1 - Channel (x) Configuration 1 */ 247 /*! @{ */ 248 249 #define RTU_MRU_CH_CFG1_MBIC0_MASK (0x10000U) 250 #define RTU_MRU_CH_CFG1_MBIC0_SHIFT (16U) 251 #define RTU_MRU_CH_CFG1_MBIC0_WIDTH (1U) 252 #define RTU_MRU_CH_CFG1_MBIC0(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH_CFG1_MBIC0_SHIFT)) & RTU_MRU_CH_CFG1_MBIC0_MASK) 253 254 #define RTU_MRU_CH_CFG1_MBIC1_MASK (0x20000U) 255 #define RTU_MRU_CH_CFG1_MBIC1_SHIFT (17U) 256 #define RTU_MRU_CH_CFG1_MBIC1_WIDTH (1U) 257 #define RTU_MRU_CH_CFG1_MBIC1(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH_CFG1_MBIC1_SHIFT)) & RTU_MRU_CH_CFG1_MBIC1_MASK) 258 259 #define RTU_MRU_CH_CFG1_MBIC2_MASK (0x40000U) 260 #define RTU_MRU_CH_CFG1_MBIC2_SHIFT (18U) 261 #define RTU_MRU_CH_CFG1_MBIC2_WIDTH (1U) 262 #define RTU_MRU_CH_CFG1_MBIC2(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH_CFG1_MBIC2_SHIFT)) & RTU_MRU_CH_CFG1_MBIC2_MASK) 263 264 #define RTU_MRU_CH_CFG1_MBIC3_MASK (0x80000U) 265 #define RTU_MRU_CH_CFG1_MBIC3_SHIFT (19U) 266 #define RTU_MRU_CH_CFG1_MBIC3_WIDTH (1U) 267 #define RTU_MRU_CH_CFG1_MBIC3(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH_CFG1_MBIC3_SHIFT)) & RTU_MRU_CH_CFG1_MBIC3_MASK) 268 269 #define RTU_MRU_CH_CFG1_MBIC4_MASK (0x100000U) 270 #define RTU_MRU_CH_CFG1_MBIC4_SHIFT (20U) 271 #define RTU_MRU_CH_CFG1_MBIC4_WIDTH (1U) 272 #define RTU_MRU_CH_CFG1_MBIC4(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH_CFG1_MBIC4_SHIFT)) & RTU_MRU_CH_CFG1_MBIC4_MASK) 273 274 #define RTU_MRU_CH_CFG1_MBIC5_MASK (0x200000U) 275 #define RTU_MRU_CH_CFG1_MBIC5_SHIFT (21U) 276 #define RTU_MRU_CH_CFG1_MBIC5_WIDTH (1U) 277 #define RTU_MRU_CH_CFG1_MBIC5(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH_CFG1_MBIC5_SHIFT)) & RTU_MRU_CH_CFG1_MBIC5_MASK) 278 279 #define RTU_MRU_CH_CFG1_MBIC6_MASK (0x400000U) 280 #define RTU_MRU_CH_CFG1_MBIC6_SHIFT (22U) 281 #define RTU_MRU_CH_CFG1_MBIC6_WIDTH (1U) 282 #define RTU_MRU_CH_CFG1_MBIC6(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH_CFG1_MBIC6_SHIFT)) & RTU_MRU_CH_CFG1_MBIC6_MASK) 283 284 #define RTU_MRU_CH_CFG1_MBIC7_MASK (0x800000U) 285 #define RTU_MRU_CH_CFG1_MBIC7_SHIFT (23U) 286 #define RTU_MRU_CH_CFG1_MBIC7_WIDTH (1U) 287 #define RTU_MRU_CH_CFG1_MBIC7(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH_CFG1_MBIC7_SHIFT)) & RTU_MRU_CH_CFG1_MBIC7_MASK) 288 /*! @} */ 289 290 /*! @name CH_MBSTAT - Channel (x) Mailbox Status */ 291 /*! @{ */ 292 293 #define RTU_MRU_CH_MBSTAT_MBS0_MASK (0x10000U) 294 #define RTU_MRU_CH_MBSTAT_MBS0_SHIFT (16U) 295 #define RTU_MRU_CH_MBSTAT_MBS0_WIDTH (1U) 296 #define RTU_MRU_CH_MBSTAT_MBS0(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH_MBSTAT_MBS0_SHIFT)) & RTU_MRU_CH_MBSTAT_MBS0_MASK) 297 298 #define RTU_MRU_CH_MBSTAT_MBS1_MASK (0x20000U) 299 #define RTU_MRU_CH_MBSTAT_MBS1_SHIFT (17U) 300 #define RTU_MRU_CH_MBSTAT_MBS1_WIDTH (1U) 301 #define RTU_MRU_CH_MBSTAT_MBS1(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH_MBSTAT_MBS1_SHIFT)) & RTU_MRU_CH_MBSTAT_MBS1_MASK) 302 303 #define RTU_MRU_CH_MBSTAT_MBS2_MASK (0x40000U) 304 #define RTU_MRU_CH_MBSTAT_MBS2_SHIFT (18U) 305 #define RTU_MRU_CH_MBSTAT_MBS2_WIDTH (1U) 306 #define RTU_MRU_CH_MBSTAT_MBS2(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH_MBSTAT_MBS2_SHIFT)) & RTU_MRU_CH_MBSTAT_MBS2_MASK) 307 308 #define RTU_MRU_CH_MBSTAT_MBS3_MASK (0x80000U) 309 #define RTU_MRU_CH_MBSTAT_MBS3_SHIFT (19U) 310 #define RTU_MRU_CH_MBSTAT_MBS3_WIDTH (1U) 311 #define RTU_MRU_CH_MBSTAT_MBS3(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH_MBSTAT_MBS3_SHIFT)) & RTU_MRU_CH_MBSTAT_MBS3_MASK) 312 313 #define RTU_MRU_CH_MBSTAT_MBS4_MASK (0x100000U) 314 #define RTU_MRU_CH_MBSTAT_MBS4_SHIFT (20U) 315 #define RTU_MRU_CH_MBSTAT_MBS4_WIDTH (1U) 316 #define RTU_MRU_CH_MBSTAT_MBS4(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH_MBSTAT_MBS4_SHIFT)) & RTU_MRU_CH_MBSTAT_MBS4_MASK) 317 318 #define RTU_MRU_CH_MBSTAT_MBS5_MASK (0x200000U) 319 #define RTU_MRU_CH_MBSTAT_MBS5_SHIFT (21U) 320 #define RTU_MRU_CH_MBSTAT_MBS5_WIDTH (1U) 321 #define RTU_MRU_CH_MBSTAT_MBS5(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH_MBSTAT_MBS5_SHIFT)) & RTU_MRU_CH_MBSTAT_MBS5_MASK) 322 323 #define RTU_MRU_CH_MBSTAT_MBS6_MASK (0x400000U) 324 #define RTU_MRU_CH_MBSTAT_MBS6_SHIFT (22U) 325 #define RTU_MRU_CH_MBSTAT_MBS6_WIDTH (1U) 326 #define RTU_MRU_CH_MBSTAT_MBS6(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH_MBSTAT_MBS6_SHIFT)) & RTU_MRU_CH_MBSTAT_MBS6_MASK) 327 328 #define RTU_MRU_CH_MBSTAT_MBS7_MASK (0x800000U) 329 #define RTU_MRU_CH_MBSTAT_MBS7_SHIFT (23U) 330 #define RTU_MRU_CH_MBSTAT_MBS7_WIDTH (1U) 331 #define RTU_MRU_CH_MBSTAT_MBS7(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH_MBSTAT_MBS7_SHIFT)) & RTU_MRU_CH_MBSTAT_MBS7_MASK) 332 /*! @} */ 333 334 /*! @name NOTIFY - Notification 0 Status..Notification 1 Status */ 335 /*! @{ */ 336 337 #define RTU_MRU_NOTIFY_CH1_IS0_MASK (0x1U) 338 #define RTU_MRU_NOTIFY_CH1_IS0_SHIFT (0U) 339 #define RTU_MRU_NOTIFY_CH1_IS0_WIDTH (1U) 340 #define RTU_MRU_NOTIFY_CH1_IS0(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_NOTIFY_CH1_IS0_SHIFT)) & RTU_MRU_NOTIFY_CH1_IS0_MASK) 341 342 #define RTU_MRU_NOTIFY_CH1_IS1_MASK (0x1U) 343 #define RTU_MRU_NOTIFY_CH1_IS1_SHIFT (0U) 344 #define RTU_MRU_NOTIFY_CH1_IS1_WIDTH (1U) 345 #define RTU_MRU_NOTIFY_CH1_IS1(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_NOTIFY_CH1_IS1_SHIFT)) & RTU_MRU_NOTIFY_CH1_IS1_MASK) 346 347 #define RTU_MRU_NOTIFY_CH2_IS0_MASK (0x2U) 348 #define RTU_MRU_NOTIFY_CH2_IS0_SHIFT (1U) 349 #define RTU_MRU_NOTIFY_CH2_IS0_WIDTH (1U) 350 #define RTU_MRU_NOTIFY_CH2_IS0(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_NOTIFY_CH2_IS0_SHIFT)) & RTU_MRU_NOTIFY_CH2_IS0_MASK) 351 352 #define RTU_MRU_NOTIFY_CH2_IS1_MASK (0x2U) 353 #define RTU_MRU_NOTIFY_CH2_IS1_SHIFT (1U) 354 #define RTU_MRU_NOTIFY_CH2_IS1_WIDTH (1U) 355 #define RTU_MRU_NOTIFY_CH2_IS1(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_NOTIFY_CH2_IS1_SHIFT)) & RTU_MRU_NOTIFY_CH2_IS1_MASK) 356 357 #define RTU_MRU_NOTIFY_CH3_IS0_MASK (0x4U) 358 #define RTU_MRU_NOTIFY_CH3_IS0_SHIFT (2U) 359 #define RTU_MRU_NOTIFY_CH3_IS0_WIDTH (1U) 360 #define RTU_MRU_NOTIFY_CH3_IS0(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_NOTIFY_CH3_IS0_SHIFT)) & RTU_MRU_NOTIFY_CH3_IS0_MASK) 361 362 #define RTU_MRU_NOTIFY_CH3_IS1_MASK (0x4U) 363 #define RTU_MRU_NOTIFY_CH3_IS1_SHIFT (2U) 364 #define RTU_MRU_NOTIFY_CH3_IS1_WIDTH (1U) 365 #define RTU_MRU_NOTIFY_CH3_IS1(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_NOTIFY_CH3_IS1_SHIFT)) & RTU_MRU_NOTIFY_CH3_IS1_MASK) 366 367 #define RTU_MRU_NOTIFY_CH4_IS0_MASK (0x8U) 368 #define RTU_MRU_NOTIFY_CH4_IS0_SHIFT (3U) 369 #define RTU_MRU_NOTIFY_CH4_IS0_WIDTH (1U) 370 #define RTU_MRU_NOTIFY_CH4_IS0(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_NOTIFY_CH4_IS0_SHIFT)) & RTU_MRU_NOTIFY_CH4_IS0_MASK) 371 372 #define RTU_MRU_NOTIFY_CH4_IS1_MASK (0x8U) 373 #define RTU_MRU_NOTIFY_CH4_IS1_SHIFT (3U) 374 #define RTU_MRU_NOTIFY_CH4_IS1_WIDTH (1U) 375 #define RTU_MRU_NOTIFY_CH4_IS1(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_NOTIFY_CH4_IS1_SHIFT)) & RTU_MRU_NOTIFY_CH4_IS1_MASK) 376 377 #define RTU_MRU_NOTIFY_CH5_IS0_MASK (0x10U) 378 #define RTU_MRU_NOTIFY_CH5_IS0_SHIFT (4U) 379 #define RTU_MRU_NOTIFY_CH5_IS0_WIDTH (1U) 380 #define RTU_MRU_NOTIFY_CH5_IS0(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_NOTIFY_CH5_IS0_SHIFT)) & RTU_MRU_NOTIFY_CH5_IS0_MASK) 381 382 #define RTU_MRU_NOTIFY_CH5_IS1_MASK (0x10U) 383 #define RTU_MRU_NOTIFY_CH5_IS1_SHIFT (4U) 384 #define RTU_MRU_NOTIFY_CH5_IS1_WIDTH (1U) 385 #define RTU_MRU_NOTIFY_CH5_IS1(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_NOTIFY_CH5_IS1_SHIFT)) & RTU_MRU_NOTIFY_CH5_IS1_MASK) 386 387 #define RTU_MRU_NOTIFY_CH6_IS0_MASK (0x20U) 388 #define RTU_MRU_NOTIFY_CH6_IS0_SHIFT (5U) 389 #define RTU_MRU_NOTIFY_CH6_IS0_WIDTH (1U) 390 #define RTU_MRU_NOTIFY_CH6_IS0(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_NOTIFY_CH6_IS0_SHIFT)) & RTU_MRU_NOTIFY_CH6_IS0_MASK) 391 392 #define RTU_MRU_NOTIFY_CH6_IS1_MASK (0x20U) 393 #define RTU_MRU_NOTIFY_CH6_IS1_SHIFT (5U) 394 #define RTU_MRU_NOTIFY_CH6_IS1_WIDTH (1U) 395 #define RTU_MRU_NOTIFY_CH6_IS1(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_NOTIFY_CH6_IS1_SHIFT)) & RTU_MRU_NOTIFY_CH6_IS1_MASK) 396 397 #define RTU_MRU_NOTIFY_CH7_IS0_MASK (0x40U) 398 #define RTU_MRU_NOTIFY_CH7_IS0_SHIFT (6U) 399 #define RTU_MRU_NOTIFY_CH7_IS0_WIDTH (1U) 400 #define RTU_MRU_NOTIFY_CH7_IS0(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_NOTIFY_CH7_IS0_SHIFT)) & RTU_MRU_NOTIFY_CH7_IS0_MASK) 401 402 #define RTU_MRU_NOTIFY_CH7_IS1_MASK (0x40U) 403 #define RTU_MRU_NOTIFY_CH7_IS1_SHIFT (6U) 404 #define RTU_MRU_NOTIFY_CH7_IS1_WIDTH (1U) 405 #define RTU_MRU_NOTIFY_CH7_IS1(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_NOTIFY_CH7_IS1_SHIFT)) & RTU_MRU_NOTIFY_CH7_IS1_MASK) 406 407 #define RTU_MRU_NOTIFY_CH8_IS0_MASK (0x80U) 408 #define RTU_MRU_NOTIFY_CH8_IS0_SHIFT (7U) 409 #define RTU_MRU_NOTIFY_CH8_IS0_WIDTH (1U) 410 #define RTU_MRU_NOTIFY_CH8_IS0(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_NOTIFY_CH8_IS0_SHIFT)) & RTU_MRU_NOTIFY_CH8_IS0_MASK) 411 412 #define RTU_MRU_NOTIFY_CH8_IS1_MASK (0x80U) 413 #define RTU_MRU_NOTIFY_CH8_IS1_SHIFT (7U) 414 #define RTU_MRU_NOTIFY_CH8_IS1_WIDTH (1U) 415 #define RTU_MRU_NOTIFY_CH8_IS1(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_NOTIFY_CH8_IS1_SHIFT)) & RTU_MRU_NOTIFY_CH8_IS1_MASK) 416 417 #define RTU_MRU_NOTIFY_CH9_IS0_MASK (0x100U) 418 #define RTU_MRU_NOTIFY_CH9_IS0_SHIFT (8U) 419 #define RTU_MRU_NOTIFY_CH9_IS0_WIDTH (1U) 420 #define RTU_MRU_NOTIFY_CH9_IS0(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_NOTIFY_CH9_IS0_SHIFT)) & RTU_MRU_NOTIFY_CH9_IS0_MASK) 421 422 #define RTU_MRU_NOTIFY_CH9_IS1_MASK (0x100U) 423 #define RTU_MRU_NOTIFY_CH9_IS1_SHIFT (8U) 424 #define RTU_MRU_NOTIFY_CH9_IS1_WIDTH (1U) 425 #define RTU_MRU_NOTIFY_CH9_IS1(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_NOTIFY_CH9_IS1_SHIFT)) & RTU_MRU_NOTIFY_CH9_IS1_MASK) 426 427 #define RTU_MRU_NOTIFY_CH10_IS0_MASK (0x200U) 428 #define RTU_MRU_NOTIFY_CH10_IS0_SHIFT (9U) 429 #define RTU_MRU_NOTIFY_CH10_IS0_WIDTH (1U) 430 #define RTU_MRU_NOTIFY_CH10_IS0(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_NOTIFY_CH10_IS0_SHIFT)) & RTU_MRU_NOTIFY_CH10_IS0_MASK) 431 432 #define RTU_MRU_NOTIFY_CH10_IS1_MASK (0x200U) 433 #define RTU_MRU_NOTIFY_CH10_IS1_SHIFT (9U) 434 #define RTU_MRU_NOTIFY_CH10_IS1_WIDTH (1U) 435 #define RTU_MRU_NOTIFY_CH10_IS1(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_NOTIFY_CH10_IS1_SHIFT)) & RTU_MRU_NOTIFY_CH10_IS1_MASK) 436 437 #define RTU_MRU_NOTIFY_CH11_IS0_MASK (0x400U) 438 #define RTU_MRU_NOTIFY_CH11_IS0_SHIFT (10U) 439 #define RTU_MRU_NOTIFY_CH11_IS0_WIDTH (1U) 440 #define RTU_MRU_NOTIFY_CH11_IS0(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_NOTIFY_CH11_IS0_SHIFT)) & RTU_MRU_NOTIFY_CH11_IS0_MASK) 441 442 #define RTU_MRU_NOTIFY_CH11_IS1_MASK (0x400U) 443 #define RTU_MRU_NOTIFY_CH11_IS1_SHIFT (10U) 444 #define RTU_MRU_NOTIFY_CH11_IS1_WIDTH (1U) 445 #define RTU_MRU_NOTIFY_CH11_IS1(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_NOTIFY_CH11_IS1_SHIFT)) & RTU_MRU_NOTIFY_CH11_IS1_MASK) 446 447 #define RTU_MRU_NOTIFY_CH12_IS0_MASK (0x800U) 448 #define RTU_MRU_NOTIFY_CH12_IS0_SHIFT (11U) 449 #define RTU_MRU_NOTIFY_CH12_IS0_WIDTH (1U) 450 #define RTU_MRU_NOTIFY_CH12_IS0(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_NOTIFY_CH12_IS0_SHIFT)) & RTU_MRU_NOTIFY_CH12_IS0_MASK) 451 452 #define RTU_MRU_NOTIFY_CH12_IS1_MASK (0x800U) 453 #define RTU_MRU_NOTIFY_CH12_IS1_SHIFT (11U) 454 #define RTU_MRU_NOTIFY_CH12_IS1_WIDTH (1U) 455 #define RTU_MRU_NOTIFY_CH12_IS1(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_NOTIFY_CH12_IS1_SHIFT)) & RTU_MRU_NOTIFY_CH12_IS1_MASK) 456 /*! @} */ 457 458 /*! @name CH1_MB0 - Channel (x) Mailbox (n) */ 459 /*! @{ */ 460 461 #define RTU_MRU_CH1_MB0_MBD_MASK (0xFFFFFFFFU) 462 #define RTU_MRU_CH1_MB0_MBD_SHIFT (0U) 463 #define RTU_MRU_CH1_MB0_MBD_WIDTH (32U) 464 #define RTU_MRU_CH1_MB0_MBD(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH1_MB0_MBD_SHIFT)) & RTU_MRU_CH1_MB0_MBD_MASK) 465 /*! @} */ 466 467 /*! @name CH1_MB1 - Channel (x) Mailbox (n) */ 468 /*! @{ */ 469 470 #define RTU_MRU_CH1_MB1_MBD_MASK (0xFFFFFFFFU) 471 #define RTU_MRU_CH1_MB1_MBD_SHIFT (0U) 472 #define RTU_MRU_CH1_MB1_MBD_WIDTH (32U) 473 #define RTU_MRU_CH1_MB1_MBD(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH1_MB1_MBD_SHIFT)) & RTU_MRU_CH1_MB1_MBD_MASK) 474 /*! @} */ 475 476 /*! @name CH2_MB0 - Channel (x) Mailbox (n) */ 477 /*! @{ */ 478 479 #define RTU_MRU_CH2_MB0_MBD_MASK (0xFFFFFFFFU) 480 #define RTU_MRU_CH2_MB0_MBD_SHIFT (0U) 481 #define RTU_MRU_CH2_MB0_MBD_WIDTH (32U) 482 #define RTU_MRU_CH2_MB0_MBD(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH2_MB0_MBD_SHIFT)) & RTU_MRU_CH2_MB0_MBD_MASK) 483 /*! @} */ 484 485 /*! @name CH2_MB1 - Channel (x) Mailbox (n) */ 486 /*! @{ */ 487 488 #define RTU_MRU_CH2_MB1_MBD_MASK (0xFFFFFFFFU) 489 #define RTU_MRU_CH2_MB1_MBD_SHIFT (0U) 490 #define RTU_MRU_CH2_MB1_MBD_WIDTH (32U) 491 #define RTU_MRU_CH2_MB1_MBD(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH2_MB1_MBD_SHIFT)) & RTU_MRU_CH2_MB1_MBD_MASK) 492 /*! @} */ 493 494 /*! @name CH3_MB0 - Channel (x) Mailbox (n) */ 495 /*! @{ */ 496 497 #define RTU_MRU_CH3_MB0_MBD_MASK (0xFFFFFFFFU) 498 #define RTU_MRU_CH3_MB0_MBD_SHIFT (0U) 499 #define RTU_MRU_CH3_MB0_MBD_WIDTH (32U) 500 #define RTU_MRU_CH3_MB0_MBD(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH3_MB0_MBD_SHIFT)) & RTU_MRU_CH3_MB0_MBD_MASK) 501 /*! @} */ 502 503 /*! @name CH3_MB1 - Channel (x) Mailbox (n) */ 504 /*! @{ */ 505 506 #define RTU_MRU_CH3_MB1_MBD_MASK (0xFFFFFFFFU) 507 #define RTU_MRU_CH3_MB1_MBD_SHIFT (0U) 508 #define RTU_MRU_CH3_MB1_MBD_WIDTH (32U) 509 #define RTU_MRU_CH3_MB1_MBD(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH3_MB1_MBD_SHIFT)) & RTU_MRU_CH3_MB1_MBD_MASK) 510 /*! @} */ 511 512 /*! @name CH4_MB0 - Channel (x) Mailbox (n) */ 513 /*! @{ */ 514 515 #define RTU_MRU_CH4_MB0_MBD_MASK (0xFFFFFFFFU) 516 #define RTU_MRU_CH4_MB0_MBD_SHIFT (0U) 517 #define RTU_MRU_CH4_MB0_MBD_WIDTH (32U) 518 #define RTU_MRU_CH4_MB0_MBD(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH4_MB0_MBD_SHIFT)) & RTU_MRU_CH4_MB0_MBD_MASK) 519 /*! @} */ 520 521 /*! @name CH4_MB1 - Channel (x) Mailbox (n) */ 522 /*! @{ */ 523 524 #define RTU_MRU_CH4_MB1_MBD_MASK (0xFFFFFFFFU) 525 #define RTU_MRU_CH4_MB1_MBD_SHIFT (0U) 526 #define RTU_MRU_CH4_MB1_MBD_WIDTH (32U) 527 #define RTU_MRU_CH4_MB1_MBD(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH4_MB1_MBD_SHIFT)) & RTU_MRU_CH4_MB1_MBD_MASK) 528 /*! @} */ 529 530 /*! @name CH5_MB0 - Channel (x) Mailbox (n) */ 531 /*! @{ */ 532 533 #define RTU_MRU_CH5_MB0_MBD_MASK (0xFFFFFFFFU) 534 #define RTU_MRU_CH5_MB0_MBD_SHIFT (0U) 535 #define RTU_MRU_CH5_MB0_MBD_WIDTH (32U) 536 #define RTU_MRU_CH5_MB0_MBD(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH5_MB0_MBD_SHIFT)) & RTU_MRU_CH5_MB0_MBD_MASK) 537 /*! @} */ 538 539 /*! @name CH5_MB1 - Channel (x) Mailbox (n) */ 540 /*! @{ */ 541 542 #define RTU_MRU_CH5_MB1_MBD_MASK (0xFFFFFFFFU) 543 #define RTU_MRU_CH5_MB1_MBD_SHIFT (0U) 544 #define RTU_MRU_CH5_MB1_MBD_WIDTH (32U) 545 #define RTU_MRU_CH5_MB1_MBD(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH5_MB1_MBD_SHIFT)) & RTU_MRU_CH5_MB1_MBD_MASK) 546 /*! @} */ 547 548 /*! @name CH6_MB0 - Channel (x) Mailbox (n) */ 549 /*! @{ */ 550 551 #define RTU_MRU_CH6_MB0_MBD_MASK (0xFFFFFFFFU) 552 #define RTU_MRU_CH6_MB0_MBD_SHIFT (0U) 553 #define RTU_MRU_CH6_MB0_MBD_WIDTH (32U) 554 #define RTU_MRU_CH6_MB0_MBD(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH6_MB0_MBD_SHIFT)) & RTU_MRU_CH6_MB0_MBD_MASK) 555 /*! @} */ 556 557 /*! @name CH6_MB1 - Channel (x) Mailbox (n) */ 558 /*! @{ */ 559 560 #define RTU_MRU_CH6_MB1_MBD_MASK (0xFFFFFFFFU) 561 #define RTU_MRU_CH6_MB1_MBD_SHIFT (0U) 562 #define RTU_MRU_CH6_MB1_MBD_WIDTH (32U) 563 #define RTU_MRU_CH6_MB1_MBD(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH6_MB1_MBD_SHIFT)) & RTU_MRU_CH6_MB1_MBD_MASK) 564 /*! @} */ 565 566 /*! @name CH7_MB0 - Channel (x) Mailbox (n) */ 567 /*! @{ */ 568 569 #define RTU_MRU_CH7_MB0_MBD_MASK (0xFFFFFFFFU) 570 #define RTU_MRU_CH7_MB0_MBD_SHIFT (0U) 571 #define RTU_MRU_CH7_MB0_MBD_WIDTH (32U) 572 #define RTU_MRU_CH7_MB0_MBD(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH7_MB0_MBD_SHIFT)) & RTU_MRU_CH7_MB0_MBD_MASK) 573 /*! @} */ 574 575 /*! @name CH7_MB1 - Channel (x) Mailbox (n) */ 576 /*! @{ */ 577 578 #define RTU_MRU_CH7_MB1_MBD_MASK (0xFFFFFFFFU) 579 #define RTU_MRU_CH7_MB1_MBD_SHIFT (0U) 580 #define RTU_MRU_CH7_MB1_MBD_WIDTH (32U) 581 #define RTU_MRU_CH7_MB1_MBD(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH7_MB1_MBD_SHIFT)) & RTU_MRU_CH7_MB1_MBD_MASK) 582 /*! @} */ 583 584 /*! @name CH8_MB0 - Channel (x) Mailbox (n) */ 585 /*! @{ */ 586 587 #define RTU_MRU_CH8_MB0_MBD_MASK (0xFFFFFFFFU) 588 #define RTU_MRU_CH8_MB0_MBD_SHIFT (0U) 589 #define RTU_MRU_CH8_MB0_MBD_WIDTH (32U) 590 #define RTU_MRU_CH8_MB0_MBD(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH8_MB0_MBD_SHIFT)) & RTU_MRU_CH8_MB0_MBD_MASK) 591 /*! @} */ 592 593 /*! @name CH8_MB1 - Channel (x) Mailbox (n) */ 594 /*! @{ */ 595 596 #define RTU_MRU_CH8_MB1_MBD_MASK (0xFFFFFFFFU) 597 #define RTU_MRU_CH8_MB1_MBD_SHIFT (0U) 598 #define RTU_MRU_CH8_MB1_MBD_WIDTH (32U) 599 #define RTU_MRU_CH8_MB1_MBD(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH8_MB1_MBD_SHIFT)) & RTU_MRU_CH8_MB1_MBD_MASK) 600 /*! @} */ 601 602 /*! @name CH8_MB2 - Channel (x) Mailbox (n) */ 603 /*! @{ */ 604 605 #define RTU_MRU_CH8_MB2_MBD_MASK (0xFFFFFFFFU) 606 #define RTU_MRU_CH8_MB2_MBD_SHIFT (0U) 607 #define RTU_MRU_CH8_MB2_MBD_WIDTH (32U) 608 #define RTU_MRU_CH8_MB2_MBD(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH8_MB2_MBD_SHIFT)) & RTU_MRU_CH8_MB2_MBD_MASK) 609 /*! @} */ 610 611 /*! @name CH8_MB3 - Channel (x) Mailbox (n) */ 612 /*! @{ */ 613 614 #define RTU_MRU_CH8_MB3_MBD_MASK (0xFFFFFFFFU) 615 #define RTU_MRU_CH8_MB3_MBD_SHIFT (0U) 616 #define RTU_MRU_CH8_MB3_MBD_WIDTH (32U) 617 #define RTU_MRU_CH8_MB3_MBD(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH8_MB3_MBD_SHIFT)) & RTU_MRU_CH8_MB3_MBD_MASK) 618 /*! @} */ 619 620 /*! @name CH8_MB4 - Channel (x) Mailbox (n) */ 621 /*! @{ */ 622 623 #define RTU_MRU_CH8_MB4_MBD_MASK (0xFFFFFFFFU) 624 #define RTU_MRU_CH8_MB4_MBD_SHIFT (0U) 625 #define RTU_MRU_CH8_MB4_MBD_WIDTH (32U) 626 #define RTU_MRU_CH8_MB4_MBD(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH8_MB4_MBD_SHIFT)) & RTU_MRU_CH8_MB4_MBD_MASK) 627 /*! @} */ 628 629 /*! @name CH8_MB5 - Channel (x) Mailbox (n) */ 630 /*! @{ */ 631 632 #define RTU_MRU_CH8_MB5_MBD_MASK (0xFFFFFFFFU) 633 #define RTU_MRU_CH8_MB5_MBD_SHIFT (0U) 634 #define RTU_MRU_CH8_MB5_MBD_WIDTH (32U) 635 #define RTU_MRU_CH8_MB5_MBD(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH8_MB5_MBD_SHIFT)) & RTU_MRU_CH8_MB5_MBD_MASK) 636 /*! @} */ 637 638 /*! @name CH8_MB6 - Channel (x) Mailbox (n) */ 639 /*! @{ */ 640 641 #define RTU_MRU_CH8_MB6_MBD_MASK (0xFFFFFFFFU) 642 #define RTU_MRU_CH8_MB6_MBD_SHIFT (0U) 643 #define RTU_MRU_CH8_MB6_MBD_WIDTH (32U) 644 #define RTU_MRU_CH8_MB6_MBD(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH8_MB6_MBD_SHIFT)) & RTU_MRU_CH8_MB6_MBD_MASK) 645 /*! @} */ 646 647 /*! @name CH8_MB7 - Channel (x) Mailbox (n) */ 648 /*! @{ */ 649 650 #define RTU_MRU_CH8_MB7_MBD_MASK (0xFFFFFFFFU) 651 #define RTU_MRU_CH8_MB7_MBD_SHIFT (0U) 652 #define RTU_MRU_CH8_MB7_MBD_WIDTH (32U) 653 #define RTU_MRU_CH8_MB7_MBD(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH8_MB7_MBD_SHIFT)) & RTU_MRU_CH8_MB7_MBD_MASK) 654 /*! @} */ 655 656 /*! @name CH9_MB0 - Channel (x) Mailbox (n) */ 657 /*! @{ */ 658 659 #define RTU_MRU_CH9_MB0_MBD_MASK (0xFFFFFFFFU) 660 #define RTU_MRU_CH9_MB0_MBD_SHIFT (0U) 661 #define RTU_MRU_CH9_MB0_MBD_WIDTH (32U) 662 #define RTU_MRU_CH9_MB0_MBD(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH9_MB0_MBD_SHIFT)) & RTU_MRU_CH9_MB0_MBD_MASK) 663 /*! @} */ 664 665 /*! @name CH9_MB1 - Channel (x) Mailbox (n) */ 666 /*! @{ */ 667 668 #define RTU_MRU_CH9_MB1_MBD_MASK (0xFFFFFFFFU) 669 #define RTU_MRU_CH9_MB1_MBD_SHIFT (0U) 670 #define RTU_MRU_CH9_MB1_MBD_WIDTH (32U) 671 #define RTU_MRU_CH9_MB1_MBD(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH9_MB1_MBD_SHIFT)) & RTU_MRU_CH9_MB1_MBD_MASK) 672 /*! @} */ 673 674 /*! @name CH9_MB2 - Channel (x) Mailbox (n) */ 675 /*! @{ */ 676 677 #define RTU_MRU_CH9_MB2_MBD_MASK (0xFFFFFFFFU) 678 #define RTU_MRU_CH9_MB2_MBD_SHIFT (0U) 679 #define RTU_MRU_CH9_MB2_MBD_WIDTH (32U) 680 #define RTU_MRU_CH9_MB2_MBD(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH9_MB2_MBD_SHIFT)) & RTU_MRU_CH9_MB2_MBD_MASK) 681 /*! @} */ 682 683 /*! @name CH9_MB3 - Channel (x) Mailbox (n) */ 684 /*! @{ */ 685 686 #define RTU_MRU_CH9_MB3_MBD_MASK (0xFFFFFFFFU) 687 #define RTU_MRU_CH9_MB3_MBD_SHIFT (0U) 688 #define RTU_MRU_CH9_MB3_MBD_WIDTH (32U) 689 #define RTU_MRU_CH9_MB3_MBD(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH9_MB3_MBD_SHIFT)) & RTU_MRU_CH9_MB3_MBD_MASK) 690 /*! @} */ 691 692 /*! @name CH10_MB0 - Channel (x) Mailbox (n) */ 693 /*! @{ */ 694 695 #define RTU_MRU_CH10_MB0_MBD_MASK (0xFFFFFFFFU) 696 #define RTU_MRU_CH10_MB0_MBD_SHIFT (0U) 697 #define RTU_MRU_CH10_MB0_MBD_WIDTH (32U) 698 #define RTU_MRU_CH10_MB0_MBD(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH10_MB0_MBD_SHIFT)) & RTU_MRU_CH10_MB0_MBD_MASK) 699 /*! @} */ 700 701 /*! @name CH10_MB1 - Channel (x) Mailbox (n) */ 702 /*! @{ */ 703 704 #define RTU_MRU_CH10_MB1_MBD_MASK (0xFFFFFFFFU) 705 #define RTU_MRU_CH10_MB1_MBD_SHIFT (0U) 706 #define RTU_MRU_CH10_MB1_MBD_WIDTH (32U) 707 #define RTU_MRU_CH10_MB1_MBD(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH10_MB1_MBD_SHIFT)) & RTU_MRU_CH10_MB1_MBD_MASK) 708 /*! @} */ 709 710 /*! @name CH10_MB2 - Channel (x) Mailbox (n) */ 711 /*! @{ */ 712 713 #define RTU_MRU_CH10_MB2_MBD_MASK (0xFFFFFFFFU) 714 #define RTU_MRU_CH10_MB2_MBD_SHIFT (0U) 715 #define RTU_MRU_CH10_MB2_MBD_WIDTH (32U) 716 #define RTU_MRU_CH10_MB2_MBD(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH10_MB2_MBD_SHIFT)) & RTU_MRU_CH10_MB2_MBD_MASK) 717 /*! @} */ 718 719 /*! @name CH10_MB3 - Channel (x) Mailbox (n) */ 720 /*! @{ */ 721 722 #define RTU_MRU_CH10_MB3_MBD_MASK (0xFFFFFFFFU) 723 #define RTU_MRU_CH10_MB3_MBD_SHIFT (0U) 724 #define RTU_MRU_CH10_MB3_MBD_WIDTH (32U) 725 #define RTU_MRU_CH10_MB3_MBD(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH10_MB3_MBD_SHIFT)) & RTU_MRU_CH10_MB3_MBD_MASK) 726 /*! @} */ 727 728 /*! @name CH11_MB0 - Channel (x) Mailbox (n) */ 729 /*! @{ */ 730 731 #define RTU_MRU_CH11_MB0_MBD_MASK (0xFFFFFFFFU) 732 #define RTU_MRU_CH11_MB0_MBD_SHIFT (0U) 733 #define RTU_MRU_CH11_MB0_MBD_WIDTH (32U) 734 #define RTU_MRU_CH11_MB0_MBD(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH11_MB0_MBD_SHIFT)) & RTU_MRU_CH11_MB0_MBD_MASK) 735 /*! @} */ 736 737 /*! @name CH11_MB1 - Channel (x) Mailbox (n) */ 738 /*! @{ */ 739 740 #define RTU_MRU_CH11_MB1_MBD_MASK (0xFFFFFFFFU) 741 #define RTU_MRU_CH11_MB1_MBD_SHIFT (0U) 742 #define RTU_MRU_CH11_MB1_MBD_WIDTH (32U) 743 #define RTU_MRU_CH11_MB1_MBD(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH11_MB1_MBD_SHIFT)) & RTU_MRU_CH11_MB1_MBD_MASK) 744 /*! @} */ 745 746 /*! @name CH11_MB2 - Channel (x) Mailbox (n) */ 747 /*! @{ */ 748 749 #define RTU_MRU_CH11_MB2_MBD_MASK (0xFFFFFFFFU) 750 #define RTU_MRU_CH11_MB2_MBD_SHIFT (0U) 751 #define RTU_MRU_CH11_MB2_MBD_WIDTH (32U) 752 #define RTU_MRU_CH11_MB2_MBD(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH11_MB2_MBD_SHIFT)) & RTU_MRU_CH11_MB2_MBD_MASK) 753 /*! @} */ 754 755 /*! @name CH11_MB3 - Channel (x) Mailbox (n) */ 756 /*! @{ */ 757 758 #define RTU_MRU_CH11_MB3_MBD_MASK (0xFFFFFFFFU) 759 #define RTU_MRU_CH11_MB3_MBD_SHIFT (0U) 760 #define RTU_MRU_CH11_MB3_MBD_WIDTH (32U) 761 #define RTU_MRU_CH11_MB3_MBD(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH11_MB3_MBD_SHIFT)) & RTU_MRU_CH11_MB3_MBD_MASK) 762 /*! @} */ 763 764 /*! @name CH12_MB0 - Channel (x) Mailbox (n) */ 765 /*! @{ */ 766 767 #define RTU_MRU_CH12_MB0_MBD_MASK (0xFFFFFFFFU) 768 #define RTU_MRU_CH12_MB0_MBD_SHIFT (0U) 769 #define RTU_MRU_CH12_MB0_MBD_WIDTH (32U) 770 #define RTU_MRU_CH12_MB0_MBD(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH12_MB0_MBD_SHIFT)) & RTU_MRU_CH12_MB0_MBD_MASK) 771 /*! @} */ 772 773 /*! @name CH12_MB1 - Channel (x) Mailbox (n) */ 774 /*! @{ */ 775 776 #define RTU_MRU_CH12_MB1_MBD_MASK (0xFFFFFFFFU) 777 #define RTU_MRU_CH12_MB1_MBD_SHIFT (0U) 778 #define RTU_MRU_CH12_MB1_MBD_WIDTH (32U) 779 #define RTU_MRU_CH12_MB1_MBD(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH12_MB1_MBD_SHIFT)) & RTU_MRU_CH12_MB1_MBD_MASK) 780 /*! @} */ 781 782 /*! @name CH12_MB2 - Channel (x) Mailbox (n) */ 783 /*! @{ */ 784 785 #define RTU_MRU_CH12_MB2_MBD_MASK (0xFFFFFFFFU) 786 #define RTU_MRU_CH12_MB2_MBD_SHIFT (0U) 787 #define RTU_MRU_CH12_MB2_MBD_WIDTH (32U) 788 #define RTU_MRU_CH12_MB2_MBD(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH12_MB2_MBD_SHIFT)) & RTU_MRU_CH12_MB2_MBD_MASK) 789 /*! @} */ 790 791 /*! @name CH12_MB3 - Channel (x) Mailbox (n) */ 792 /*! @{ */ 793 794 #define RTU_MRU_CH12_MB3_MBD_MASK (0xFFFFFFFFU) 795 #define RTU_MRU_CH12_MB3_MBD_SHIFT (0U) 796 #define RTU_MRU_CH12_MB3_MBD_WIDTH (32U) 797 #define RTU_MRU_CH12_MB3_MBD(x) (((uint32_t)(((uint32_t)(x)) << RTU_MRU_CH12_MB3_MBD_SHIFT)) & RTU_MRU_CH12_MB3_MBD_MASK) 798 /*! @} */ 799 800 /*! 801 * @} 802 */ /* end of group RTU_MRU_Register_Masks */ 803 804 /*! 805 * @} 806 */ /* end of group RTU_MRU_Peripheral_Access_Layer */ 807 808 #endif /* #if !defined(S32Z2_RTU_MRU_H_) */ 809
