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Searched refs:RSTGT_W (Results 1 – 25 of 72) sorted by relevance

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/hal_nxp-3.6.0/imx/drivers/
Drdc_semaphore.c165 semaphore->RSTGT_W = 0xE2; in RDC_SEMAPHORE_Reset()
166 semaphore->RSTGT_W = 0x1D | RDC_SEMAPHORE_RSTGT_W_RSTGTN(index); in RDC_SEMAPHORE_Reset()
181 base->RSTGT_W = 0xE2; in RDC_SEMAPHORE_ResetAll()
182 base->RSTGT_W = 0x1D | RDC_SEMAPHORE_RSTGT_W_RSTGTN_MASK; in RDC_SEMAPHORE_ResetAll()
/hal_nxp-3.6.0/mcux/mcux-sdk/drivers/sema42/
Dfsl_sema42.c204 base->RSTGT_W = SEMA42_RSTGT_W_RSTGDP(SEMA42_GATE_RESET_PATTERN_1); in SEMA42_ResetGate()
206 …base->RSTGT_W = SEMA42_RSTGT_W_RSTGDP(SEMA42_GATE_RESET_PATTERN_2) | SEMA42_RSTGT_W_RSTGTN(gateNum… in SEMA42_ResetGate()
/hal_nxp-3.6.0/mcux/mcux-sdk/drivers/rdc_sema42/
Dfsl_rdc_sema42.c227 base->RSTGT_W = RDC_SEMAPHORE_RSTGT_W_RSTGDP(RDC_SEMA42_GATE_RESET_PATTERN_1); in RDC_SEMA42_ResetGate()
229 base->RSTGT_W = in RDC_SEMA42_ResetGate()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/K32L3A60/
DK32L3A60_cm0plus.h16138 __O uint16_t RSTGT_W; /**< Reset Gate Write, offset: 0x42 */ member
DK32L3A60_cm4.h16088 __O uint16_t RSTGT_W; /**< Reset Gate Write, offset: 0x42 */ member
/hal_nxp-3.6.0/imx/devices/MCIMX6X/
DMCIMX6X_M4.h31674 …__IO uint16_t RSTGT_W; /**< Reset Gate Write,offset: 0x40 */ member
31690 #define RDC_SEMAPHORE_RSTGT_W_REG(base) ((base)->RSTGT_W)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h20468 __O uint16_t RSTGT_W; /**< Reset Gate Write, offset: 0x42 */ member
DMIMXRT685S_cm33.h30208 __O uint16_t RSTGT_W; /**< Reset Gate Write, offset: 0x42 */ member
/hal_nxp-3.6.0/imx/devices/MCIMX7D/
DMCIMX7D_M4.h38860 …__IO uint16_t RSTGT_W; /**< Reset Gate Write,offset: 0x40 */ member
38876 #define RDC_SEMAPHORE_RSTGT_W_REG(base) ((base)->RSTGT_W)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MCIMX7U3/
DMCIMX7U3_cm4.h27817 __O uint16_t RSTGT_W; /**< Reset Gate Write, offset: 0x42 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MCIMX7U5/
DMCIMX7U5_cm4.h27818 __O uint16_t RSTGT_W; /**< Reset Gate Write, offset: 0x42 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h30208 __O uint16_t RSTGT_W; /**< Reset Gate Write, offset: 0x42 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h32554 __O uint16_t RSTGT_W; /**< Reset Gate Write, offset: 0x42 */ member
DMIMXRT595S_cm33.h42187 __O uint16_t RSTGT_W; /**< Reset Gate Write, offset: 0x42 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h40560 __O uint16_t RSTGT_W; /**< Reset Gate Write, offset: 0x42 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h42186 __O uint16_t RSTGT_W; /**< Reset Gate Write, offset: 0x42 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MN2/
DMIMX8MN2_cm7.h44111 __IO uint16_t RSTGT_W; /**< Reset Gate Write, offset: 0x40 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MN5/
DMIMX8MN5_cm7.h44113 __IO uint16_t RSTGT_W; /**< Reset Gate Write, offset: 0x40 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MN3/
DMIMX8MN3_cm7.h44113 __IO uint16_t RSTGT_W; /**< Reset Gate Write, offset: 0x40 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MN4/
DMIMX8MN4_cm7.h44111 __IO uint16_t RSTGT_W; /**< Reset Gate Write, offset: 0x40 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MN1/
DMIMX8MN1_cm7.h44113 __IO uint16_t RSTGT_W; /**< Reset Gate Write, offset: 0x40 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MN6/
DMIMX8MN6_ca53.h44125 __IO uint16_t RSTGT_W; /**< Reset Gate Write, offset: 0x40 */ member
DMIMX8MN6_cm7.h44111 __IO uint16_t RSTGT_W; /**< Reset Gate Write, offset: 0x40 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MQ5/
DMIMX8MQ5_cm4.h45199 __IO uint16_t RSTGT_W; /**< Reset Gate Write, offset: 0x40 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MD6/
DMIMX8MD6_cm4.h47372 __IO uint16_t RSTGT_W; /**< Reset Gate Write, offset: 0x40 */ member

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